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PRESENTED BY: NISHANT YADAV(0802EC10ME13) PRACHI TYAGI(0802EC10ME15

)

€ € € € € € Introduction to LEON Overview of AMBA About DMAC Interfaces State machine Programmer¶s model .

two UARTs. flexible memory controller. interrupt controller. 6. € € 1. . watchdog. 5.€ € LEON is a 32-bit CPU microprocessor core based on SPARC V8. hardware multiplier and divider. It is designed for embedded applications with the following features on-chip: separate instruction and data caches. 4. 16-bit I/O port and a. It is described in VHDL. 3. It was originally designed by the European Space Research and Technology Centre(ESTEC )and after that by Gaisler Research. two 24-bit timers. 2.

.€ Additional modules can easily be added using the on-chip AMBA AHB/APB buses.

or cache read operations are written back to the register file. 2.The LEON integer unit uses a single instruction issue pipeline with 5 stages: 1. DE (Decode): The instruction is decoded and the operands are read. the fetch is forwarded to the memory controller. Operands come from the register file. Otherwise. 3. 5. logical. logical. FE (Instruction Fetch): If the instruction cache is enabled. the instruction is fetched directly from the instruction cache. The instruction is valid at the end of this stage and is latched inside the IU. and shift operations are performed. WR (Write): The result of any ALU. EX (Execute): ALU. € . shift. ME (Memory): Data cache is accessed. 4.

The Advanced Microcontroller Bus Architecture (AMBA) specification defines an on chip communications standard for designing high performance embedded microcontrollers. 2. AHB supports the efficient connection of processors. on-chip memories and off-chip external memory. The AHB acts as the high-performance system backbone bus. 2. € 1. . 3. Advanced High-performance Bus (AHB) The AMBA AHB is for high-performance system modules. Two distinct buses are defined within the AMBA specification: the Advanced High-performance Bus (AHB) the Advanced Peripheral Bus (APB).€ € 1.

The AMBA APB is for low-power peripherals. AMBA APB is optimized for minimal power consumption and reduced interface. 2.Advanced Peripheral Bus (APB) 1. .

half word.Read from slave data bus HREADY . error.Size of the transfer (byte. LOW=read.Slave select (simply a decode of the address bus) HRDATA[31:0] .Active LOW.Transfer type HWRITE . retry etc) .When HIGH indicates the bus is free HRESP[1:0] . HIGH=write. HSIZE[2:0] .€ € € € € € € € € € € HCLK .32bit system address bus HTRANS[1:0] . word etc«) HBURST[2:0] . Resets the system and bus.Transfer response (OK.This clock times all bus transfers HRESETn .Write to slave data bus HSELx .Burst type HWDATA[31:0] . HADDR[31:0] .Transfer direction.

€ Direct Memory Access (DMA) allows devices to transfer data without subjecting the processor a heavy overhead. € But it can continue to work on any work which does not require bus access. € During this time the processor would be unavailable for any other tasks involving processor bus access. . € DMA transfers are essential for high performance embedded systems where large chunks of data need to be transferred from the input/output devices to or from the primary memory.

The number of these channels is configurable from 1 up to 8. . The DMAC is configurable for each valid AHB data bus width up to 32 bits.0 bus with a big-endian data format. € € € The DMAC is for an AMBA AHB 2. A block transfer consists of several successive single transfers.€ The DMAC is an advanced microcontroller bus architecture (AMBA) compliant peripheral. € The burst length as well as the number of transfers is programmable. ƒ ƒ Single transfer consists of a read burst and a subsequent write burst. The DMAC has several independent DMA channels. € The DMAC supports single transfers as well as a block transfer.

€ The controller supports all four possible kinds of transfer ƒ ƒ ƒ ƒ Peripheral Memory Peripheral Memory Memory Peripheral Peripheral Memory € A transfer can be triggered by sending a software command from the CPU or by asserting of a request signal DREQ. . € The controller asserts an acknowledge signal DACK as a response on a hardware request.

ƒ ƒ When a programmed number of single transfers are completed. When a peripheral breaks a block transfer by asserting the signal EOP. EOP. When an error has occurred during the transfer. .€ A peripheral device can break a block by asserting an ³end of process´ signal. € The controller can generate an interrupt request signals on four different events: ƒ ƒ When a block transfer is completed.

Interrupt AMBA APB DREQ0 DACK0 EOP0 DREQ1 DACK1 EOP1 General Register APB Slave Interface Channel 0 Channel Arbiter DMA Handshake Signals Multiplexer Channel 1 DMA Engine AMBA AHB DREQn DACKn EOPn Channel n .

. ‡ Interrupt interface.The DMAC contains the following interfaces: ‡ APB slave interfaces ‡ AHB master interface ‡ Peripheral request interfaces . ‡ Reset initialization interface .

DMAC block diagram .

DMA CONTROLLER STATE MACHINE .

PROGRAMMERS MODEL .

to send instructions to a thread when debugging the program code 2. system firmware to send instructions to the DMA manager thread as Issuing instructions to the DMAC using an APB interface € . for each DMA channel thread.Control registers Use these registers to control the DMAC. € Debug registers These registers enable: 1. € AXI and loop counter status registers These registers provide the AXI bus transfer status and the loop counter status. € DMA channel thread status registers These registers provide the status of the DMA channel threads.

Configuration registers These registers enable system firmware to discover the configuration of the DMAC and control the behavior of the watchdog. . € Component ID registers € These registers enable system firmware to identify an AMBA peripheral.