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ZXG10-BSC(V2.

0)
System Structure Introduction
BSS in Mobile Communications

Mobile
Phone

BTS
BSC
BSC in PLMN
MSC/VLR PSTN

MAP-E

MSC/VLR HLR
MS MAP-D
Um
BTS MAP-C
Abis A MAP-H
BSC Gs
SMC
Gb Gr Gd
MAP-F
Gf
EIR SGSN

Gn Gp
GGSN GGSN
Gi
Other PLMN
PDN TE
ZXG10-BSS Structure
BTS Q3
BIE BIE
MS Um Abis OMC

SM SM TC MSC

BSC
Ater A

PLMN
BTS
SGSN
BIE BIE Gb PDN
Abis
Protocol Stack of CS Typed-BSC

MS BTS BSC MSC


CC CC
MM MM
RR BSSAP BSSAP
RR RR
BTSM BTSM SCCP SCCP
MTP3 MTP3
LAPDm LAPDm LAPD LAPD
MTP2 MTP2
Um Abis A
Main Functions of BSC
• Abis interface
• CS functioning
• PS functioning
• Land equipment operation & management and
No.7 signaling interconnecting
• RR management
• TRAU(TC)
• SM
Logical Structure of BSCV2.0
RMM1

RMM2
……

SCM OMM

RMM7

RMM8
Structure of ZXG10-BSC V2.0
PCU
Abis 8M× 2 Gb
BIU#11 8M× 2
2M× 8
RMM#1 RMU
A
8M× 2 TCU AIU
BIU#12

TCU AIU
N
S 8M× 2
8M× 2 8M× 2
8M× 2 U TCU AIU
E1 N F
F N S E1 S
BIU#81 S S M M
M M U U
RMM#8 RMU U U TCU AIU
BIU#82
TC
BIE 2M× 16
SCM SCU OMM
Hardware Structure of ZXG10-BSC V2.0
Gb
PCU
RMUk
SMB SYCK
E1× 4
E1× 4 BIU AIU
TIC #1 TCU DRT TIC A
#1
Abis TIC #2 #1 #2 DRT
AIPP #8
BIPP #1(2× 8M)
#6 #8 TIC
TIC TCPP DRT
BOSN #1
#2 #n
BIPP TCPP

DRT DTI

k=<8
MPMP LAPD
n=<15
MPMP MPPP MTP LAPD
S
MP M MP MON S
E MP M MP
M PEPD E
M
RMU1 SCU

Note:BSC(V2) is compatible with color of Of BSC(V1)


SCU Communication
Management Structure
MP0 SMEM MP1 SCU

AT BUS

MPMP MPPP MTP PEPD MON

Asynch.
HDLC Serial PS
HDLC
PCU Bus
MSC SYCK
B
O S
DSNI
S M D FSPP/ BIPP
TCPP
N B R D AIPP NSPP
T T 485
485
I
RS- PS
TIC TIC
HDLC 485
SYCK
COMI
DRT
TIC
RMU Communication
Management Structure

RMU
MP0 SMEM MP1

AT BUS

MPMP LAPD PEPD

LAPD LAPD

OMU TRU
ZXG10-BSC V2.0
Rack Description
There are six shelves (backplane)in a BSC rack. They are:
( 1 ) Control layer(BCTL) ;
( 2 ) T-net and clock layer(BNET) ;
( 3 ) A interface and TC layer(BATC) ;
( 4 ) Abis interface layer(BBIU) ;
( 5 ) Sub-multiplexing layer(BSMU) ;
( 6 ) GPRS layer(PCU) ;
Control layer(1)
• Active/Standby MP
• SMEM
• COMM
• MONI
• PEPD

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
P S C C C C C C C C C C C C P P
M
O M M M O O O O O O O O O O O O E O
O
W E P M M M M M M M M M M M M P W
P N
B M M M M M M M M M M M M M D B
Control layer(2)
Ethernet

Control layer backplane bus 1


MP0
Active/standby switching

SMEM

Control layer backplane bus 2


MP1

Ethernet t COMM COMM PEPD MONI I

OMC -R

Infrared smoke sensor

umidity sensor
Temperature/h
4 HWwires 4 HW wires 8 RS485 buses
Basic Structure of MP
Control layer bus
AT bus controller
Control layer backplane bus
CPU subsystem

Shared m em ory
m anager Shared m em o ry b u s
PCI b u s
E thernet controller T wo 10/100M E thernet
interfaces
MP active/
Active/standby switchover
standby control
signal
IDE interface
Other service
functions
Hard
disk Power m odule -4 8 V
Main Function of MP
• 1. Communicate with external interface units assisted
by COMM boards;
• 2. Control connection of the switching network
assisted by COMM boards;
• 3. Processes the Ethernet interface and enables
communication between foreground and background;
• 4. Control active/standby MP switchover;
• 5. Control the active/standby switchover of function
units working in the active/standby mode
SMEM

1 2
MP0 bus

Data buffer Data buffer

Dual interfaces

RAM EPLD
2M
RAM

MP1 bus

Data buffer Data buffer


Functions of COMM Boards and Types
Functions:

– Co-processors of MP
– Fulfils data link functioning of control channel
Types:
HDLC : MP-PP communication within BSC
HDLC : MP-MP communication within and between
BSCs
LAPD : BSC-BTS communication at Abis interface
No.7 : BSC-MSC communication at A interface
COMM Structure Diagram
Communication Channels of COMM

BTS
BTS BIPP T Net TCPP AIPP MSC
MSC

Backplane Bus
LAPD
LAPD MPMP
MPMP MPPP
MPPP MPMP No.7
MPMP No.7
Communication Mode of COMM(1)

64Kb/s
PP COMM
64Kb/s

64Kb/s
PP COMM
64Kb/s
Communication Mode of COMM(2)

5 1 2 K b /s
MP M PM P M PM P MP

5 1 2 K b /s
MP M PM P M PM P MP
Communication Mode of COMM(3)

2 5 6K b /s
MP COMM B O SN
2 5 6K b /s

2 5 6K b /s
MP COMM B O SN
2 5 6K b /s
MONI

select control
RS-

EPLD chip
M em ory
485

transceivers
( )
8
M P0
Buffer D ual interfaces
RAM CPU M ulti-serial-port RS-
M P1 386 controller 232
D ual interfaces

transceivers
Buffer
RAM

( )
2
Parity
check
PEPD

D ual Iso la tio n T e m p e ra tu re /


M P0 in te r fa c e s a m p lific a tiohnu m id ity s e n s o r
B u ffe r R A M
CPU
M P1 386
D ual
B u ffe r
in te r fa c e s In fr a re d s m o k e s e n
RAM Iso la tio n
T-NET Buildup
• DSN (BOSN)
• DSNI
• SYCK
• CKI
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

P S S D D D D D D D D D D P
C D D
O Y Y S S S S S S S S S S O
K S S
W C C N N N N N N N N N N W
I N N
B K K I I I I I I I I I I B
Schematic Block Diagram of T-net

16MHZ
Clock processing circuit SYCK board
8KHZ
4M 8K 16M 8K
COM
M0
Hub HW0

Bus interface Drive isolation


EPLD

Timeslot switching
COM
M1 HW1
Chip select

(
32 HW2
control

circuit
K× K)
HDLC protocol circuit

……
control 32 64

Alarm HW62
Shared memory HW63

FE frame alignment
Active/standby
CPU
switching
Control Mode of T-net(1)

256kb/s
MP CO M M Bosn
256kb/s

256kb/s
MP CO M M Bosn
256kb/s
Control Mode of T-net(2)

DSNI (PP level) DSNI (MP level)


59 ×8M 59 ×8M
Externalinterface
unitorR M M
m odule

BOSN digital switching


network

32
K×K

32
4 ×8M 16*2 MHWs
COM M (SCM )

2MHW

Communication Communication
board board
(H D LC) (H DLC )

SCMmainprocessunit

MP0 MP1
Connection Between T-network HWs and DSNI
BOSN DSNI (MP) DSNI (PP)

/
HW0, 1 The first DSNI board

/
HW2, 3 The second DSNI
board
/
HW4~19 The third and the
fourth DSNI boards
/
HW20~35 The fifth and the sixth
DSNI boards
/
HW36~51 The seventh and the
eighth DSNI boards
/
HW52~62 The ninth and the
tenth DSNI boards
DSNI(MP Level)
8MHZ Clock 4M
SYCKboard frequency- 4M, 8K(16 channels) COMMboard
8KHZ division 8K
allocation 8M, 8K(4 channels)

8M 8K
8× 2M
2× 8M Code rate change
HW0
8× 2M
Code rate change HW1

Difference drive

…………
Isolation circuit of
single end drive

8M 8K
2× 8M
8× 2M
2× 8M Code rate change HW14
8× 2M HW15
Code rate change

Active/standby
switching

Slot recognition
CPU
5

RS485
Monitoring board
External Physical Connection of DSNI Board (MP-level)

CBLHW0 ( TS0~TS15 ) Cable 0#


CBLHW1 ( TS0~TS15 )

……
DSNI
HW1 0
CBLHW14 ( TS0~TS15 )
HW2 Cable 7#
CBLHW15 ( TS0~TS15 )

BOSN
CBLHW0 ( TS0~TS15 ) Cable 8#
CBLHW1(TS0~TS15)
HW3
HW4
……
DSNI
1
CBLHW14 ( TS0~TS15 )
Cable 15#
CBLHW15 ( TS0~TS15 )
DSNI(PP Level)
16 × 8M

Difference drive
HW0
HW1
Single end drive


16 × 8M
HW14
HW15

Active/standby
switching
Slot recognition
CPU
5

RS485 Monitoring board

8MHZ
16 M
SYCK board Clock frequency- External
8KHZ division allocation 16M,8K interface
8K
unit
Working Mode of DSNI(PP level) Board (1)

16
A c tiv e T -n e tw o rk A c tiv e D S N I
16
16 E x te rn a l in te r fa c e
16 u n it
S ta n d b y T -n e tw o rk S ta n d b y D S N I
16
Working Mode of DSNI(PP level)
Board(2)
• 1) If no standby DSNI interface board is available,
DSNI will not switched over in case of
active/standby switchover of the T-network.
• 2) If standby DSNI interface board is available,
DSNI will automatically switch over together with
active/standby switchover of the T-network.
• 3) If DSNI board is plugged out, it will perform
active/standby switch over automatically, while no
switchover occurs in the T-network.
Jumper Configurations for
MP and PP level DSNI

Jumper connection MP-level PP-level


board type

X3 1 and 2 connected 2 and 3 connected

X4A, X4B 1 and 2 connected 2 and 3 connected


BBIU

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
P B B C C B B P
T T T T T T T T T T T T
O I I O O I I O
I I I I I I I I I I I I
W P P M M P P W
C C C C C C C C C C C C
B P P I I P P B
Position of BIU
Cascaded BIPP
Abis

BIU
TIC 1
BIPP 2 COMI BIPP 1
2× 8M 2× 8M 8M
TIC n
2× 8M
2× 8M
DSNI n<=6

MPMP LAPD

S
MP M MP
E
M
RMU
Block Diagram of BIPP
Cascade BIPP 8MHZ
Clock processing circuit T-network
TIC, COMI 8KHZ

drive isolation
Difference
4× 8M T-network
Cascade BIPP
Switching circuit
(4KX4K)
Drive 9× 8M COMI(2)
TIC (6)
Single
Multiplexing/ Opposite board (1)
polarity
demultiplexing

HDLC protocol processing

485 bus Active/standby


CPU switching
Block Diagram of TIC

To BIPP E I
Isolation interface
drive circuit 0

E I
interface
circuit 1

E I
interface
circuit 2
Isolation
receiving E I
From BIPP interface
circuit 3
EI interface unit

CPU
8M,8K,2M
8K square wave
Clock processing unit
485 8M and 8K clocks
Alarm indication
BIPP
TCU&AIU(BATC)

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
P T T A A P
D D D D D D D D T T T T T T T T
O C C I I O
R R R R R R R R I I I I I I I I
W P P P P W
T T T T T T T T C C C C C C C C
B P P P P B
Block Structure of TCU&AIU
BOSN

DSNI

2× 8M
TCU AIU
4× E1
(E)DRT 1× 8M TIC
1 1
TCPP AIPP


1× 8M (E)DRT 1× 8M TIC
m m

m<=8
A
Block Structure of DRT
8MHz Clock receiving 8MHz
T-network or FSMU processing circuit To AIPP
8KHz 8KHz

1× 8M 1× 8M
Difference drive Difference drive
T-network or FSMU AIPP
8M(16kb/s ) 8M(64kb/s )

HDLC protocol
controller

Switching circuit

Communicate with MP Traffic channels


concentration circuit

Traffic channels

Message channel
Level translation isolation circuit
Level translation
CPU

isolation circuit

8M(64kb/s ) 8M(16kb/s )

HPI Digital signal 8M


processing circuit
8K
8M(16kb/s ) 8M(64kb/s )

EPLD
Level translation circuit

1× 8M 1× 8M
Difference drive Difference drive
DSNI or SMT2 AIPP
SMU(1)

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
P S S F F P
C T T T T T T T T
O Y Y S S O
K I I I I I I I I
W C C P P W
I C C C C C C C C
B K K P P B

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
P N N P
T T T T T T T T
O S S O
I I I I I I I I
W P P W
C C C C C C C C
B P P B
SMU(2)

SYCK
4× E1 Far BIPP
TIC TIC Or TCPP
8M 1 1
1
2× 8M
TIC TIC
2 2
n× 8M
NSPP FSPP
T-NET …… Far BIPP
8M
Or TCPP
TIC TIC n/2
n n

n<=8
Physical Position of SMU

BIU TCU

BIU/Far SMU T-NET SMU TCU/Far

BIU TCU
Power P

-4 8V 1 I so la tin g d io d e
power module

- 4 8V o u tp u t
Primary

I so la tin g d io d e R a c k b u sb a r
-4 8V 2

PO W ER P
Power B(1)

1 2 3 4 5 6 7 8 9 10 11 1 2 13 1 4 15 16 1 7 1 8 1 9 20 21 22 2 3 2 42 5 2

P P
O O
O th e r circu it c on nec tors
W W
B B
Power B(3)
Name Index

Maximum input <8A


surging current

DC output ripple <60mv

high-frequency <100mv
noise

System ≥75%
conversion
efficiency
Device <50°C
temperature rise

Overvoltage Fuses withstand current


protection <8A.

When the output voltage exceeds the nominal


value by ± 20%, an alarm will be given.
Synchronization
• Synchronization is in master-slave mode.
• There are multiple synchronization references,
such as BITS synchronization, cesium-atomic
clock frequency scale synchronization, and digital
trunk timing extraction synchronization, each with
4-channel clock input interface and additional
property of multiple backups.
• Realized by CKI and SYCK
SYCK
• SYCK applies phase lock circuits in “loose
coupling mode” and works in the following
four modes:
• 1) Fast capture mode.
• 2) Tracking mode.
• 3) Hold mode.
• 4) Free Oscillating mode.
Clock Circuit
• SYCK outputs 20-channel 8MHZ and its
frame header clock signal O8k, and 10-
channel 16MHz and its frame header clock
signal H8k, which will be sent to each
subsystem as the timely source of
synchronization clock references for the
whole system.
Diagram of SYCK Timing
Clock Synchronization without SMU
A interface clock signal

BCTL (SCU )

S
Y
C
K

Ordinary BSC rack BSCcenter rack Ordinary BSCrack

Abis interface Clock flow direction


Clock Synchronization with SMU
A interface clock signal

S
Y BCTL (SCU ) S
C Y
K S C
Abis interface
Y K
C
K

Remote RMM rack BSC center rack Remote TC rack

Clock flow direction


Abis interface SMB DRT DTI Ainterface
CKI
Supportin
Abis interface Trunk transmission body
Supportin SYCK SYCK SYCK SYCK
body
TIC #1 #1 #1
#1
BIPP FSPP TIC TIC NSPP DSNI BOSN DSNI NSPP TIC

BIPP FSPP NSPP DSNI DSNI NSPP


TIC TIC TIC
#6 TIC
Supportin #m1 #n1 BSMU #n2
body BOSN
BSMU BNET
COMI COMI Supportin
DSNI DSNI
Supportin body BSMU
BBIU body

MPMP MPMP LAPD PEPD MPMP MPMP MPPP MPPP MTP LAPD PEPD MON

BCTL

MP(RMM) MP(RMM)
Supportin BCTL MP(SCM) MP(SCM)
Supportin
body body

Trunk transmission
SYCK SYCK
#1
Ainterface #1 #1
TIC AIPP (E)DRT TCPP FSPP TIC
Description:
TIC #8 AIPP (E)DRT TCPP FSPP TIC
1 Color
#8
indicates thispart Supportin Supportin #n2
belongs toV1.X body body
BATC BSMU
2 Color
indicates thispart is
optiona Gb
interface
3 Enclosure withdotted lines PCU
indicates content of a shelf
4 Arrow
indicatesthis part isthe basisfor
the existence of this shelf

Supportin
POWB
5 Sign body = +Backplane
POWB

6 Inthe figure: m1,n1 ,n2 ≤ 8 ; m1 ≤ n1


ZXG10-BSC Software Structure

O&M RR DTAP

BSSMAP
B B
T S
S C
DAT
M M
ABA
SE MTP Layer 3
Abis
A
LAPD MTP Layer 2

OSS