Digital Fundamentals

Tenth Edition

Floyd

Chapter 7

Floyd, Digital Fundamentals, 10th ed

© 2008 Pearson Education © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved

Summary
Latches A latch is a temporary storage device that has two stable states (bistable). It is a basic form of memory.
The S-R (Set-Reset) latch is the most basic type. It can be constructed from NOR gates or NAND gates. With NOR gates, the latch responds to active-HIGH inputs; with NAND gates, it responds to active-LOW inputs.
R Q S Q

S

Q

R

Q

NOR Active-HIGH Latch
Floyd, Digital Fundamentals, 10th ed

NAND Active-LOW Latch

© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved

Summary
Latches The active-HIGH S-R latch is in a stable (latched) condition when both inputs are LOW.
Assume the latch is initially RESET (Q = 0) and the inputs are at their inactive level (0). To SET the latch (Q = 1), a momentary HIGH signal is applied to the S input while the R remains LOW. To RESET the latch (Q = 0), a momentary HIGH signal is applied to the R input while the S remains LOW.
0 R 0 1 Q

1 0
0 S 0 R 1 0

Latch initially RESET
Q

Q

0 1 0 S

Latch initially SET
Q

Floyd, Digital Fundamentals, 10th ed

© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved

Assume the latch is initially RESET (Q = 0) and the inputs are at their inactive level (1). All Rights Reserved . Upper Saddle River. Digital Fundamentals. Floyd. To RESET the latch a momentary LOW is applied to the R input while S is HIGH. Never apply an active set and reset at the same time (invalid). 10th ed 1 S 0 1 Q 1 0 1 R 1 S 1 0 Latch initially RESET Q Q Latch initially 0 1 SET 1R Q © 2009 Pearson Education. To SET the latch (Q = 1). a momentary LOW signal is applied to the S input while the R remains HIGH.Summary Latches The active-LOW S-R latch is in a stable (latched) condition when both inputs are HIGH. NJ 07458.

Digital Fundamentals. All Rights Reserved . It features four internal latches with two having two S inputs. S-R latches are frequently used for switch debounce circuits as shown: VCC (2) (3) (1) (6) (5) (11) (12) (10) (15) (14) Position 1 to 2 Position 2 to 1 1S1 1S2 1R 2S 2R 3S1 3S2 3R 4S 4R (4) 1Q (7) 2Q (9) 3Q 2 S R Q S R (13) 4Q 1 74LS279A Floyd. 10th ed © 2009 Pearson Education. NJ 07458. Upper Saddle River. It is available in several packages. the S line is pulsed low. To SET any of the latches.Summary Latches The active-LOW S-R latch is available as the 74LS279A IC.

Keep in mind that S and R are only active when EN is HIGH. Digital Fundamentals. Upper Saddle River. R Assume Q starts LOW. 10th ed © 2009 Pearson Education. Show the Q output with Q relation to the input signals. S R EN Q Floyd.Summary Latches A gated latch is a variation on the basic latch. All Rights Reserved . NJ 07458. called enable (EN) that must be HIGH in order for the latch to EN respond to the S and R inputs. S The gated latch has an additional Q input.

Upper Saddle River. NJ 07458. All Rights Reserved .Summary Latches The D latch is an variation of the S-R latch but combines the S and R inputs into a single D input as shown: D EN Q Q D EN Q Q A simple rule for the D latch is: Q follows D when the Enable is active. Floyd. 10th ed © 2009 Pearson Education. Digital Fundamentals.

All Rights Reserved . If EN is LOW. 10th ed © 2009 Pearson Education. Digital Fundamentals. Upper Saddle River.Summary Latches The truth table for the D latch summarizes its operation. NJ 07458. then there is no change in the output and it is latched. Inputs Outputs D 0 1 X EN 1 1 0 Q 0 1 Q0 Q 1 0 Q0 Comments RESET SET No change Floyd.

Summary Latches Determine the Q output for the D latch. D EN Q D EN Q Q Notice that the Enable is not active during these times. 10th ed © 2009 Pearson Education. given the inputs shown. All Rights Reserved . NJ 07458. so the output is latched. Upper Saddle River. Digital Fundamentals. Floyd.

NJ 07458.Summary Flip-flops A flip-flop differs from a latch in the manner it changes states. in which only the clock edge determines when a new bit is entered. All Rights Reserved . D C Q D C Q (a) Positive edge-triggered Q (b) Negative edge-triggered Q Dynamic input indicator Floyd. The active edge can be positive or negative. Digital Fundamentals. 10th ed © 2009 Pearson Education. Upper Saddle River. A flip-flop is a clocked device.

All Rights Reserved . The truth table for a negative-edge triggered D flip-flop is identical except for the direction of the arrow. Inputs D 1 0 CLK Outputs Q 1 0 Q 0 1 Comments SET RESET Inputs D 1 0 CLK Outputs Q 1 0 Q 0 1 Comments SET RESET (a) Positive-edge triggered (b) Negative-edge triggered Floyd. Digital Fundamentals. otherwise it is latched.Summary Flip-flops The truth table for a positive-edge triggered D flip-flop shows an up arrow to remind you that it is sensitive to its D input only on the rising edge of the clock. 10th ed © 2009 Pearson Education. NJ 07458. Upper Saddle River.

labeled J and K. All Rights Reserved . When both J and K = 1. it has two inputs. the output changes states (toggles) on the active clock edge (in this case.Summary Flip-flops The J-K flip-flop is more versatile than the D flip flop. Upper Saddle River. the rising edge). In addition to the clock input. NJ 07458. Digital Fundamentals. Inputs J K Outputs Q Q0 0 1 Q0 CLK Q Q0 1 0 Q0 Comments No change RESET SET Toggle 0 0 1 1 0 1 0 1 Floyd. 10th ed © 2009 Pearson Education.

Q Notice that the outputs change on the leading edge of the clock. All Rights Reserved . given the inputs shown. NJ 07458.Summary Flip-flops J CLK K Q Determine the Q output for the J-K flip-flop. Upper Saddle River. Digital Fundamentals. Set CLK J K Q Floyd. 10th ed Toggle Set Latch © 2009 Pearson Education.

D Q For example. CLK CLK Q D flip-flop hardwired for a toggle mode Floyd. All Rights Reserved . Q is HIGH and the flip-flop will toggle on the next clock edge. Because the flip-flop only changes on the active edge. the output will only change once for each clock pulse. if Q is LOW. This is useful in some counters as you will see in Chapter 8. Upper Saddle River. but you can hardwire a toggle mode by connecting Q back to D as shown. Digital Fundamentals.Summary Flip-flops A D-flip-flop does not have a toggle mode like the J-K flipflop. 10th ed © 2009 Pearson Education. NJ 07458.

Digital Fundamentals. Upper Saddle River. meaning they affect the output independent of the clock. 10th ed © 2009 Pearson Education. J CLK K Q Q CLR Floyd. All Rights Reserved . NJ 07458. A J-K flip flop with active LOW preset and CLR is shown. PRE Two such inputs are normally labeled preset (PRE) and clear (CLR).Summary Flip-flops Synchronous inputs are transferred in the triggering edge of the clock (for example the D or J-K inputs). Most flipflops have other inputs that are asynchronous. These inputs are usually active LOW.

given the inputs shown. Upper Saddle River.Summary Flip-flops J PRE Q CLK Determine the Q output for the J-K flip-flop. 10th ed © 2009 Pearson Education. Set CLK J K K Q CLR Toggle Set Reset Toggle Latch Set Reset PRE CLR Q Floyd. NJ 07458. All Rights Reserved . Digital Fundamentals.

Upper Saddle River. All Rights Reserved .Summary Flip-flop Characteristics Propagation delay time is specified for the rising and falling outputs. 10th ed © 2009 Pearson Education. Digital Fundamentals. Floyd. It is measured between the 50% level of the clock to the 50% level of the output transition. 50% point on triggering edge CLK CLK 50% point Q tPLH 50% point on LOW-toHIGH transition of Q Q tPHL 50% point on HIGH-toLOW transition of Q The typical propagation delay time for the 74AHC family (CMOS) is 4 ns. Even faster logic is available for specialized applications. NJ 07458.

Upper Saddle River. Again it is measured from the 50% levels. Digital Fundamentals. All Rights Reserved . PRE 50% point CLR 50% point Q tPHL 50% point Q tPLH 50% point Floyd. The 74AHC family has specified delay times under 5 ns. NJ 07458. 10th ed © 2009 Pearson Education.Summary Flip-flop Characteristics Another propagation delay time specification is the time required for an asynchronous input to cause a change in the output.

All Rights Reserved . D CLK Hold time. NJ 07458. Upper Saddle River. Digital Fundamentals. ts Hold time is the minimum time for the data to remain after the clock. tH Floyd. 10th ed © 2009 Pearson Education. D CLK Set-up time.Summary Flip-flop Characteristics Set-up time and hold time are times required before and after the clock transition that data must be present to be reliably clocked into the flip-flop. Setup time is the minimum time for the data to be present before the clock.

Summary Flip-flop Characteristics Other specifications include maximum clock frequency.6 ns. The unit is energy. A useful comparison between logic families is the speed-power product which uses two of the specifications discussed: the average propagation delay and the average power dissipation. Digital Fundamentals. All Rights Reserved . NJ 07458. The quiescent power dissipated is 1. The power dissipation is the product of the supply voltage and the average current required.1 mW. Upper Saddle River. the speed-power product is 5 pJ Floyd. and power dissipation. Therefore. 10th ed © 2009 Pearson Education. From Table 7-5. minimum pulse widths for various inputs. What is the speed-power product for 74AHC74A? Use the data from Table 7-5 to determine the answer. the average propagation delay is 4.

for data storage applications. Upper Saddle River. as frequency dividers. a group of flip-flops are connected to parallel data lines and clocked together.Summary Flip-flop Applications Principal flip-flop applications are for temporary data storage. All Rights Reserved . 10th ed © 2009 Pearson Education. and in counters (which are covered in detail in Chapter 8). D C Output lines Q0 R D C Q1 R D C Q2 R Parallel data input lines D Q3 C Clock Clear R Floyd. Digital Fundamentals. Typically. NJ 07458. Data is stored until the next clock pulse.

it is simple to use a flip-flop in the toggle mode or to chain a series of toggle flip flops to HIGH HIGH continue to divide by two. A side benefit of frequency division is that the output has an exact 50% duty cycle. Upper Saddle River. two flip-flops will divide fin by 4 (and so on). Waveforms: fout Floyd. One flip-flop will divide fin by 2. Digital Fundamentals. NJ 07458.Summary Flip-flop Applications For frequency division. 10th ed © 2009 Pearson Education. All Rights Reserved J QA CLK J QB CLK fout fin K K fin .

Upper Saddle River. 10th ed © 2009 Pearson Education. the length of time in the unstable state (tW) is determined by an external RC circuit. REXT CEXT CX RX/CX Q Trigger Q Trigger Q tW Floyd. When triggered. it goes to its unstable state for a predetermined length of time.Summary One-Shots The one-shot or monostable multivibrator is a device with only one stable state. Digital Fundamentals. +V then returns to its stable state. All Rights Reserved . For most one-shots. NJ 07458.

Digital Fundamentals. 10th ed © 2009 Pearson Education. If it occurs during the unstable state. All Rights Reserved .Summary One-Shots Nonretriggerable one-shots do not respond to any triggers that occur during the unstable state. Retriggerable one-shot: Trigger Retriggers Q tW Floyd. NJ 07458. even if it occurs in the unstable state. Upper Saddle River. Retriggerable one-shots respond to any trigger. the state is extended by an amount equal to the pulse width.

Summary One-Shots An application for a retriggerable one-shot is a power failure detection circuit. All Rights Reserved . and continue to retrigger the one shot. NJ 07458. In the event of a power failure. Triggers are derived from the ac power source. 10th ed © 2009 Pearson Education. Digital Fundamentals. Triggers derived from ac Missing trigger due to power failure Q Retriggers tW tW Retriggers tW Power failure indication Floyd. the one-shot is not triggered and an alarm can be initiated. Upper Saddle River.

The pulse width is determined by R1C1 and is approximately +V tW = 1. including as a one-shot. Digital Fundamentals.Summary The 555 timer The 555 timer can be configured in various ways. 10th ed © 2009 Pearson Education. Upper Saddle River.1R1C1. NJ 07458.1R1C1 C1 Floyd. All Rights Reserved . A basic one shot is shown. (6) (2) THRES OUT (5) TRIG CONT GND (1) tW = 1. CC (4) (8) R1 (7) RESET VCC (3) DISCH The trigger is a negative-going pulse.

Digital Fundamentals.Summary The 555 timer Determine the pulse width for the circuit shown.1R1C1 Floyd. NJ 07458.2 mF TRIG CONT GND (1) tW = 1.2 mF) = 24.2 ms +VCC +15 V R1 10 kW (4) (7) RESET (8) VCC (3) DISCH (6) (2) THRES OUT (5) C1 2.1R1C1 = 1.1(10 kW)(2. tW = 1. 10th ed © 2009 Pearson Education. All Rights Reserved . Upper Saddle River.

Digital Fundamentals. R2 C1 (6) (2) OUT TRIG CONT GND (1) Floyd.44  R1  2 R2  C1 R1 (7) (4) (8) RESET DISCH THRES VCC (3) (5) The frequency and duty cycle are set by these components. The output +V frequency is given by: CC f  1.Summary The 555 timer The 555 can be configured as a basic astable multivibrator with the circuit shown. 10th ed © 2009 Pearson Education. In this circuit C1 charges through R1 and R2 and discharges through only R2. NJ 07458. All Rights Reserved . Upper Saddle River.

All Rights Reserved .001 0. Digital Fundamentals.1 TRIG CONT GND (1) 1. NJ 07458.1 R2 C1 (6) (2) W OUT 0. 10th ed © 2009 Pearson Education.0k 10k 100k f (Hz) Floyd.Summary The 555 timer Given the components. you can read the frequency from the chart.01 0. you can use the chart to pick components for a desired frequency.0 10 100 1. Upper Saddle River. Alternatively. +VCC 100 10 1.0 R1 (7) 10 1 1M 0k 10 10 kW MW kW W (4) (8) C1 (mF) RESET DISCH THRES VCC (3) (5) 0.

Latches and flip-flops are bistable multivibrators. no-change. 10th ed © 2009 Pearson Education. All Rights Reserved . Floyd. D flip-flop A type of bistable multivibrator in which the output assumes the state of the D input on the triggering edge of a clock pulse. NJ 07458. J-K flip-flop A type of flip-flop that can operate in the SET. Clock A triggering input of a flip-flop. Digital Fundamentals. Bistable Having two stable states. Upper Saddle River. RESET. and toggle modes.Selected Key Terms Latch A bistable digital circuit used for storing a bit.

All Rights Reserved . Upper Saddle River. Digital Fundamentals. NJ 07458. Set-up time The time interval required for the input levels to be on a digital circuit. Floyd. Hold time The time interval required for the input levels to remain steady to a flip-flop after the triggering edge in order to reliably activate the device. 10th ed © 2009 Pearson Education. Timer A circuit that can be used as a one-shot or as an oscillator.Selected Key Terms Propagation The interval of time required after an input signal delay time has been applied for the resulting output signal to change.

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