Centre for Computer Technology

ICT123 Computer Architecture
Week 02
Computer System Architectures and Data Handling
Semester 2, 2006

Content at a Glance
Week 1 Review  Computer System and connectivity  Van Neumann architecture  Harvard Architecture  More advanced Architectures  Machine Operation: Instruction cycle  Machine organization and instruction sets

March 20, 2012

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

Computer Architecture

Abstract characterisations of physical computers that provide the structural, functional and performance specifications for a specific physical computer.
Formalisation of the requirements to a specification of constraints that can be feasibly and economically implemented in a physical machine.
Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

March 20, 2012

Computer Architecture vs. Organization

Computer architecture refers to the system attributes that have direct impact on the logical execution of operations, and which are visible to the programmer Computer organization refers to the physical operational units, their interconnections, and other details that realize the architectural specifications, and which are transparent to the programmer. (Stallings, 2003 p.4)
Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

March 20, 2012

Structure and Function
Computer Structure:
     

Computer Function: Data Movement Data Storage Data Processing Control mechanism Paths for data and control signals

Input/Output Main Memory CPU Control Unit System interconnection

    

March 20, 2012

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

The Human Hardware

March 20, 2012

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

Functional View of a Computer
Data Storage Facility
Data Movement Apparatus

Control Mechanism

Data Processing Facility

March 20, 2012

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

Basic Computer System
ALU Memory equipment

I/O

CU

CPU

March 20, 2012

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

Basic Computer System Connectivity
A computer consists of four functional units and their communication channels.  Each functional unit could itself be made up using a number of physical units.  How can we connect all these components into a single functional unit?

March 20, 2012

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

Basic Computer System
First Solution:
Memory ALU I/O

Mesh connectivity;
i.e. direct connection between all components

CU

1 unit 2 units 3 units 4 units 10 units -

no connection needed 1 connection path 3 connection paths 6 connection paths 45 connection paths

March 20, 2012

N units - ½*N*(N-1) connection paths Richard Salomon, Sudipto Mitra
Copyright Box Hill Institute

Basic Computer System
Connect all components using a system bus
CPU
CU ALU Memory I/O

2 units - 3 connection paths (only 1 path really) 3 units - 4 connection paths ( 2 physical connections) N units - logically (N + 1) connection paths - physically (N – 1) connections
March 20, 2012

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

Bus Interconnection Scheme

March 20, 2012

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

The CPU Structure
CPU
Computer
I/O System Bus Memory CPU

Registers

Arithmetic and Login Unit

Internal CPU Interconnection

Control Unit

March 20, 2012

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

Von Neumann Architecture

March 20, 2012

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

Von Neumann Architecture

The 3 key concepts in Von Neumann architecture are: 1. Data and instructions are stored in a single read/write memory 2. The contents of this memory are addressable by location, regardless of its Locn 410 Instrcn 1 contents Locn 414 Instrcn 2 3. Instructions are executed in a sequential manner, one Locn 416 Instrcn 3 after another; in a single March 20, 2012 Richard Salomon, Sudipto Mitra processing unit. Memory

Copyright Box Hill Institute

Most computers are based on the Von Neumann architecture concepts developed by John Von Neumann in the 1940s.

Simple CPU Operation
To perform a simple register-toregister addition, the control logic executes the following steps:
1.

2.

3. 4. 5.

Access the data from one CPU register and then latching the data into an ALU holding register. Access the data from another CPU register and then latching the data into the other ALU holding register. Instruct the ALU to add the two numbers together Latch the result into the ALU output register Write the result back to a CPU register

March 20, 2012

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

The Von Neumann bottleneck

In a typical instruction execution sequence we must: 1. access the instruction to determine what to do 2. get the data 3. perform the required operation (execute) 4. save the result in memory, if required The speed of a von Neumann computer is limited by the fact that instructions and data must be accessed sequentially via a single bus This is known as the Von Neumann bottleneck
Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

March 20, 2012

Harvard Architecture
Harvard architecture machines have separate program and data memories, with their own separate busses.  Thus Harvard machines are potentially faster, as we can access the next instruction while fetching the data for the current instruction

March 20, 2012

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

Program Memory Address Bus

Harvard Architecture

Data Memory Address Bus

Program Memory

CPU

Data Memory

March 20, 2012

Program Memory Data Bus

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

Data Memory Data Bus

Harvard Architecture
Get Get Instruction Data Execute Instruction
Execute Instruction

Get Get Instruction Data

Simultaneou s

March 20, 2012

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

More recent architectures support the use of:

More Advanced Architectures


more sophisticated memory structures that allow simultaneous access to multiple locations multiple functional units for simultaneous data processing control concurrent execution instructions (threading)
Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

March 20, 2012

Instruction Cycle
Each instruction has two distinct phases, namely; Instruction Fetch (IF) execute Instruction (EI)  The computer continues through this sequence one instruction after another

START
March 20, 2012

IF

EI

STOP

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

Instruction Cycle
 

Now lets take a closer look

To fetch the instruction we need to calculate its address in memory  We may also need to fetch the data to operate upon (operand)

March 20, 2012

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

Fetch Cycle
  

Program Counter (PC) holds address of next instruction to fetch Processor fetches instruction from memory location pointed to by PC Increment PC

Unless told otherwise

 

Instruction loaded into Instruction Register (IR) Processor interprets instruction and performs required actions
March 20, 2012

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

Execute Cycle

Processor-memory

data transfer between CPU and main memory Data transfer between CPU and I/O module Some arithmetic or logical operation on data Alteration of sequence of operations e.g. jump

Processor I/O

Data processing

Control
 

Combination of above
Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

March 20, 2012

Example of Program Execution

March 20, 2012

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

Instruction Cycle State Diagram

March 20, 2012

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

Interrupts

In the real world, all computers must allow system modules to interrupt the normal execution sequence, to allow for unusual situations and for tasks with higher priority than the current job Virtually all computers provide an interrupt mechanism to suspend the current task in favour of a higher priority task When the higher priority task is completed execution usually returns to the interrupted task
Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

March 20, 2012

Common Interrupts

Program

e.g. overflow, division by zero Generated by internal processor timer Used in pre-emptive multi-tasking from I/O controller e.g. memory parity error
Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

Timer
 

I/O

Hardware failure

March 20, 2012

Instruction cycle with Interrupts
Interrupts Enabled

Handle Interrupt Request (Switch task)
Check for Interrupts

Interrupts Disabled START

IF

EI

Interrupts Enabled STOP
March 20, 2012

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

Instruction Formats
Machine code instructions tell the CPU two things  What to do. This is called the operator and is typically MOVE, ADD, SUBTRACT, AND, OR, etc.  What to do it to. This/these are called the operands and can be CPU registers.

March 20, 2012

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

Machine organization and instruction sets

Computer architectures are closely related to what their instructions may be able to do, and may be categorised as:
Zero Address  One address  Two Address and  Three Address

architectures.
March 20, 2012

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

Machine organization and instruction sets

  

Zero address architectures support only zero address instructions One address architectures support zero address and one address instructions, and so on ... Most personal computers have two address architecture Instructions are usually categorised by function as: data transfer, arithmetic, logic, machine control instructions
March 20, 2012

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

Zero Address Architecture
also known as Stack Architecture
e.g. HP calculator, FPUs
r0

IN-OUT

r1
r2 ALU
March 20, 2012

r3
Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

Zero Address Instructions

Do not provide direct reference to the data within the instruction

The location of the data is predefined (implied) within the architecture
Instruction examples: Push, Pop (Pull), add, sub, or, and, xor
Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

March 20, 2012

Zero Address Architecture Example

Consider: x = (2 + 3) * 4 – 12/6 ; The above infix expression must be first converted to its equivalent postfix notation: 2,3,+,4,*,12,6,/,This can be done with the help of Dijkstra’s algorithm

March 20, 2012

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

push 2 push 3 add push 4 mul push 12 push 6 div sub pop

One Address Architecture
early micro-computers

I-O

Accumulator

ALU
March 20, 2012

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

One Address Instructions

Provide direct reference for one operand only

The other operand is in a predefined accumulator  Instruction examples: ld m3, st m4, sub m25

March 20, 2012

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

One Address Architecture Example

Consider: x = (2 + 3) * 4 – 12/6 ;

ld #2 add #3 mul #4 st m1 ld #12 div #6 st m2 ld m1 sub m2 st m3

March 20, 2012

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

Two Address Architecture
most CPUs
6502, 8486, HC11, 8051
Accumulator
Register File ALU
March 20, 2012

I-O

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

Two Address Instructions
Provide direct reference for two operands  Instruction examples: mov m7, r3 Format: add r4, r5 sub m25, acc instruction destination, source
 e.g. move to m7 from r3

add to r4 from r5
March 20, 2012

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

Two Address Architecture Example

Consider: x = (2 + 3) * 4 – 12/6 ;

div #6,#12 st m2,acc add #3,#2 mul acc,#4 sub m2 st m1

March 20, 2012

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

Three Address Architecture
e.g. PowerPC, e-server
Accumulator Register File ALU

I-O

March 20, 2012

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

Three Address Instructions
• Provide direct reference to two source operands and the destination

• Instruction examples: add m32, r4, r5 Format: sub m12, m25, r7 instr dest, source2, source1 mul m5, m37, m12
A-B sub acc b a subtract b from a a (div) b div acc b a Be is the divisor of a

March 20, 2012

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

Three Address Architecture Example

Consider: x = (2 + 3) * 4 – 12/6 ; 20 – 2

div m2,#6,#12 add acc,#3,#2 mul acc,#4 sub m1,2,20

March 20, 2012

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

Observation

The simpler the architecture:

the simpler the instruction set i.e. supports only simple, short and therefore fast instruction. requires a longer and more complex program

The wider the address architecture:
 

the shorter the program, but requires support for more complex instructions

March 20, 2012

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

References

 

Stallings William, 2003, Computer Organization & Architecture designing for performance, 7th edn, Pearson Education M Morris Mano, Computer System Architecture, 3rd edn, Prentice Hall Frank Duyker, Computer Systems Architecture, Box Hill TAFE
Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

March 20, 2012

Web References
 


http://en.wikipedia.org/wiki/Reverse_Polish_not ation http://www.spsu.edu/cs/faculty/bbrown/web_lec tures/postfix/ http://home.att.net/~srschmitt/reversepolish.ht ml http://users.ece.gatech.edu/mleach/revpol/

March 20, 2012

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

Sign up to vote on this title
UsefulNot useful