Submitted by: Name: Alankrita Singh Roll No: 08 Branch: Computer Science

Today's microprocessors sport a general-purpose design which has its own advantages and disadvantages.
 Advantage: One chip can run a range of programs.

That's why you don't need separate computers for different jobs, such as crunching spreadsheets or editing digital photos  Disadvantage: For any one application, much of the chip's circuitry isn't needed, and the presence of those "wasted" circuits slows things down.

Hardware (Application Specific Integrated Circuits) Chameleon computing Software-programmed processors Advantages: •very high performance and efficient Disadvantages: •not flexible (can’t be altered after fabrication) • expensive Advantages: •fills the gap between hardware and software •much higher performance than software •higher level of flexibility than ASIC’s Advantages: •software is very flexible to change Disadvantages: •performance can suffer if clock is not fast •fixed instruction set by hardware .

to describe the functionality of ASICs. such as Verilog or VHDL. .  Designers of digital ASICs use a hardware description language (HDL). a chip designed solely to run a cell phone is an ASIC. An application-specific integrated circuit (ASIC) is an integrated circuit (IC) customized for a particular use  For example.

.  FPGAs contain programmable logic components called "logic blocks". and a hierarchy of reconfigurable interconnects that allow the blocks to be wired together. A field-programmable gate array (FPGA) is an integrated circuit designed to be configured by the customer or designer after manufacturing.


 that means when a particular software is loaded the present hardware design is erased and a new hardware design is generated by making a particular number of connections active while making others idle.  Reconfigurable processor usually contains several parallel processing computational units known as functional blocks. . A chameleon processor is a reconfigurable microprocessor with erasable hardware that can rewire itself dynamically. the connections inside the functional blocks and the connections in between the functional blocks are changing.  While reconfiguring the chip.  This allows the chip to adapt effectively to the programming tasks demanded by the particular software they are interfacing with at any given time.

 Among .  Reconfigurable processors are currently available from Chameleon Systems. which allows customers to convert their algorithms to hardware configuration by themselves. those only Chameleon is providing a design environment.  It takes just 20 microseconds to reconfigure the entire processing array. Billions of Operations (BOPS). This will define the optimum hardware configuration for that particular software. and PACT (Parallel Array Computing Technology).

Four algorithms would divide the chip into four functional areas.  With Reconfigurable Technology. In a conventional ASIC or FPGA. multiple algorithms are implemented as separate hardware modules.  So finally the result is: much higher performance. lower cost and lower power consumption . many algorithms are loaded into the entire reconfigurable Fabric one at a time.


which are used to construct the circuit. Resulting configuration stream is downloaded into configuration memory through configuration inputs.  The most important parts are the logic circuits. which configure function blocks according to data in the configuration memory.  A new chip must inside determine the set of the function blocks (FB).  Thus. Machine design supposes that some pins are considered as the configuration inputs and another as data or control inputs and outputs. .  The various possible connections between functional blocks are encoded to bits known as Configuration bits. a new Reconfigurable machine is established. rules of their interconnections and ways of the input/output connections.


 32-bit RISC processor  64 bit memory controller  32 bit PCI controller  reconfigurable processing fabric (RPF)  high speed system bus  programmable I/O (160 pins)  DMA(Direct Mem Access) Subsystem  Configuration Subsystem .

16×24-bit Multipliers  Operating at 125Mhz. Each tile can be reconfigured at runtime  Tiles contain :  Datapath Units  Local Store Memories  16x24 multipliers  Control Logic Unit .000.  The CS2112 has 4 Slices with 3 Tiles in each. the basic unit of reconfiguration. they provide up to 3.  The fabric is divided into Slices.000 16-bit Million Multiply-Accumulates Per Second  24.32-bit Data path Units  24. It consists of  84. The Fabric provides unmatched algorithmic computation power to Chameleon Chip. 16-bit Million Operations Per Second.



 Each Programmable I/O bank (ie each slice) of 40 Programmable I/O pins delivers 0.5 GBytes/sec I/O bandwidth. These chips includes banks of Programmable I/O (PIO) pins which provide tremendous bandwidth. .

with eConfigurable Technology. . each Slice can be configured independently.eCONFIGURABLE™ TECHNOLOGY: eConfigurable™ Technology is instantaneous reconfiguration. Swapping the Background Plane into the Active Plane requires just one clock cycle. this operation does not interfere with active processing on the Fabric. This used for technology reconfigures fabric in one clock cycle and increases voice/data/video channels per chip. Loading the Background Plane from external memory requires just 3 µsec per Slice. As mentioned earlier.



C~SIDE Development Tools :  With this software development tool .  C~Side uses a combined C language and Verilog flow to map algorithms into the chip’s reconfigurable processing fabric (RPF). debugging and verifying RCP designs. .  The Chameleon Systems Integrated Development Environment (C~SIDE) is a complete toolkit for designing. Chameleon Systems are providing the ability for the customers to do the programming themselves thus keeping the secrecy of their algorithms.


configuration management and DMA services.  The eBIOS calls are automatically generated at compile time. .eBIOS (eConfigurable Basic I/O Services ):  It provides a interface between the Embedded Processor System and the Fabric.  eBIOS provides resource allocation. but can be edited for precise control of any function.

and field-programmable gate arrays (FPGAs). system architects continue to struggle with the requirement that communication systems deliver both performance and flexibility. .  Enter the reconfigurable processor. However. Today’s system architects have at their disposal an arsenal of highly integrated. an entirely new category of semiconductor solution that serves as a system-level platform for a broad range of applications. high-performance semiconductor technologies. application-specific standard products (ASSPs). such as application-specific integrated circuits (ASICs). digital signal processors (DSPs).

. Early and fast design  Reducing development cost  Can more quickly adapt to new requirements and standards  Increasing bandwidth  Reducing power  Reducing manufacturing cost.

 Inertia – Engineers slow to change  Inertia is the worst problem facing reconfigurable computing  RCP designs requires comprehensive set of tools  'Learning curve' for designers unfamiliar with reconfigurable logic .

 Software-Defined Radio (SDR) SDR concept is applied in Cell phone Technology .  High-Performance DSL (Digital Subscriber Line Technology) DSL technology brings high Bandwidth to homely users. bandwidth and reconfigurable nature. Base-station infrastructure will have to be adaptive enough to accommodate those requirements. Wireless Base stations The reconfigurable technology mainly focuses on base stations and their unpredictable combination of voice and data-traffic. With a fixed processor the channels must be able to support both simple voice calls and high-bandwidth data connections  Wireless Local Loop (WLL) Reconfigurable technology is widely applied in Wireless Local Loops also because of their high processing power.

xDSL concentrators. Its advantages are that it can create customized communications signal processors . DSP. multichannel voice compression. multiprotocol packet and cell processing protocols. base-stations. fixed wireless local loop. and it can more quickly adapt to new requirements and standards and it has lower development costs and reduce risk. software-defined radio. These new chips called chameleon chips are able to rewire themselves on the fly to create the exact hardware needed to run a piece of software at the outmost speed. highperformance embedded telecom and datacom applications. data-intensive has increased performance and channel count. voice compression.  Its applications are in. wireless .

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