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Unit - IV


Peripheral Devices:
The input-output subsystem of a computer provides an efficient mode of communication between the central system and the outside environment. Programs and data must be entered into computer memory for processing and results obtained from computations must be recorded or displayed for the user. The common input devices are keyboard, mouse and joystick. To use a computer efficiently, a large amount of programs and data must be prepared in advance and transmitted into a storage medium such as magnetic tapes or disks.

The information in the disk is then transferred into computer memory at a rapid rate.

Devices that are under the direct control of the computer are said to be connected on-line.
Input or output devices attached to the computer are also called peripherals. Among the most common peripherals keyboards, display units, and printers. are

Peripherals that provide auxiliary storage for the system are magnetic disks and tapes.

Input Output Interface:

Input - output interface provides a method for transferring information between internal storage and external I/O devices.

Peripherals connected to a computer need special communication links for interfacing them with the central processing unit.
The purpose of the communication link is to resolve the differences that exist between the central computer and each peripheral. The major differences are:

3. 4.

Peripherals manner of operation is different from the operation of the CPU and memory, The data transfer rate of peripherals is usually slower than the transfer rate of the CPU, Data codes and formats in peripherals differ from the word format in the CPU and memory. The operating modes of peripherals are different from each other.

To resolve these differences, computer systems include special hardware components between the CPU and peripherals to supervise and synchronize all input and output transfers. These components are called interface units. Because they interface between the processor bus and the peripheral device. In addition, each device may have its own controller that supervises the operations of the particular mechanism in the peripheral.

I/O Bus and Interface modules:

A typical communication link between the processor and several peripherals as shown in below figure.

The I/O bus consists of data lines, address lines, and control lines. The magnetic disk, printer, and terminal are employed in practically any general-purpose computer. Each peripheral device has associated with it an interface unit. Each interface decodes the address and control received from the I/O bus interprets them for the peripheral and provides signals for the peripheral controller. It also synchronizes the data flow and supervises the transfer between peripheral and processor. Each peripheral has its own controller that operates the particular electromechanical device.

To communicate with a particular device, the processor places a device address on the address lines. When the interface detects its own address, it activates the path between the bus lines and the device that it controls. All peripherals whose address does not correspond to the address in the bus are disabled by their interface. At the same time that the address is made available in the address lines, the processor provides a function code in the control lines. The interface selected responds to the function code and proceeds to execute it. The function code is referred to as an I/O command.

There are four types of commands that an interface may receive. They are classified as control, status, data output, and data input. A control command is issued to activate the peripheral and to inform it what to do. A status command is used to test various status conditions in the interface and the peripheral. A data output command causes the interface to respond by transferring data from the bus into one of its registers. The data input command is the case interface receives an item of data from the peripheral and places it in its buffer registers.

I/O versus Memory Bus:

In addition to communicating with I/O, the processor must communicate with the memory unit. Like the I/O bus, the memory bus contains data, address, and read/write control lines.

There are three ways that computer buses can be used to communicate with memory and I/O:
1. Use two separate buses, one for memory and the other for I/O. Use one common bus for both memory and I/O but have separate control lines for each. Use one common bus for memory and I/O with common control lines.


In the first method, the computer has independent sets of buses, one for memory and the other for I/O. This is done in computers that provide a separate I/O processor (lOP) in addition to central processing unit (CPU).

The memory communicates with both the CPU and the IOP through a memory bus.
The IOP communicates also with the input and output devices through a separate I/O bus. The I/O processor is sometimes called a data channel.

Isolated versus Memory-mapped I/O:

Many computers use one common bus to transfer information between memory or I/O and the CPU. The distinction between a memory transfer and I/O transfer is made through separate read and write lines.

The CPU specifies whether the address on the address lines is for a memory word or for an interface register by enabling one of two possible read or write lines. The I/O read and I/O write control lines are enabled during an I/O transfer.
The memory read and memory write control lines are enabled during a memory transfer.

This configuration isolates all I/O interface addresses from the addresses assign to memory and is referred to as the isolated I/O method for assigning addresses in a common bus. In the isolated I/O configuration, the CPU has distinct input and output instructions, and each of these instructions is associated with the address of an interface register. When the CPU fetches and decodes the operation code of an input or output instruction, it places the address associated with the instruction into the common address lines. At the same time, it enables the I/O read (for input) or I/O write (for output) control line. This informs the external components that are attached to the common bus that the address in the address lines is for an interface register and not for a memory word.

The isolated I/O method isolates memory and I/O addresses so memory address values are not affected by interface address assignment since each has its own address space.
The other alternative is to use the same address space for both memory and I/O.

This is the case in computers that employ only one set of read and write signals and do not distinguish between memory and I/O addresses. This configuration is referred to as memorymapped I/O.
The CPU can manipulate I/O data residing in interface registers with the same instructions that are used to manipulate memory words.

Asynchronous Data transfer:

The internal operations in a digital system are synchronized by means of clock pulses supplied by a common pulse generator.

Clock pulses are applied to all registers within a unit and all data transfers among internal registers occur simultaneously during the occurrence of a clock pulse. Two units, such as a CPU and an I/O interface, are designed independently of each other. the registers in the interface share a common clock with the CPU registers, the transfer between the two units is said to be synchronous.
In most cases, the internal timing in each unit is independent from the other in that each uses its own private clock for internal registers. In that case, the two units are said to be asynchronous to each other.

Asynchronous data transfer between two independent units requires that control signals be transmitted between the communicating units to indicate the time at which data is being transmitted. One way of achieving this is by means of a strobe pulse supplied by one of the units to indicate to the other unit when the transfer has to occur. Another method commonly used is to accompany each data item being transferred with a control signal that indicates the presence of data in the bus. The unit receiving the data item responds with another control signal to acknowledge receipt of the data. This type of agreement between two independent units is referred to as handshaking.

Strobe Control:
The strobe control method of asynchronous data transfer employs a single control line to time each transfer. The strobe may be activated by either the source or the destination unit.

The data bus carries the binary information from source unit to the destination unit. Typically, the bus has multiple lines to transfer an entire byte or word.

The strobe is a single line that informs the destination unit when a valid data word is available in the bus.


1. The source unit first places the data on the data bus. After a brief delay, 2. The source activates the strobe pulse. 3. The information on the data bus and the strobe signal remain in the active state for a sufficient time. 4. Often, the destination unit uses the falling edge of the strobe pulse to transfer the contents of the data bus into one of its internal registers. 5. The source removes the data from the bus a brief period after it disables its strobe pulse.

Destination initiated Data transfer:

The above diagram shows the strobe control initiated the destination (i.e. destination is requesting for data from a source).

The destination unit activates the strobe pulse, informing the source to provide the data. The source unit responds by placing the requested binary information on the data bus. The data must be valid and remain in the bus long enough for the destination unit to accept it. The destination unit then disables the strobe after it receives the data. The source removes the data from the bus after a predetermined time interval. In many computer systems, the strobe pulse is actually controlled by the clock pulses in the CPU.

Hand shaking:
The disadvantage of the strobe method is that the source unit that initiates the transfer has no way of knowing whether the destination unit has actually received the data item that was placed in the bus. Similarly, a destination unit that initiates the transfer has no way of knowing whether the source unit has actually placed the data on the bus. The handshake method solves this problem by introducing a second control signal that provides a reply to the unit that initiates the transfer.

The basic principle of the two-wire handshaking method of data transfer is as follows.

One control line is in the same direction as the data flow in the bus from the source to the destination. It is used by the source unit to inform the destination unit whether there are valid data in the bus.

The other control line is in the other direction from the destination to the source.
It is used by the destination unit to inform the source whether it can accept data. The sequence of control during the transfer depends on the unit that initiates the transfer.

Source initiated transfer:

1. Source initiates the transfer by placing data on the bus and enabling its data valid signal. 2. The data accepted signal is activated by the destination unit after it accepts the data from the bus. 3. The source unit then disables its data valid signal which invalidates the data on the bus.

4. Destination unit disables its data accepted signal.

5. The source does not send next data until destination disables accepted signal.


This scheme allows arbitrary delays from one state to the next and permits each unit to respond at its own data transfer rate.

Destination initiated data transfer:

The name of the signal generated by the destination unit has been changed to ready for data to reflect its new meaning. The source unit does not place the data until it receives the ready for data signal fro the destination unit. From there on, same procedure follows as in the case source initiation. The handshaking scheme provides a high degree of flexibility and reliability. If one unit is faulty, the data transfer is not completed. Such an error can be detected by means of timeout mechanism. Which produces an alarm if data transfer is not completed within a predetermined time.

Asynchronous Serial Transfer:

The transfer of data between two units may be done in parallel or serial.
In parallel data transmission, each bit of the message has its own path and the total message is transmitted at the same time. This means that an n-bit message must be transmitted through n separate conductor paths.

In serial data transmission, each bit in the message is sent in sequence one at a time.
This method requires the use of one pair of conductors or one conductor and a common ground.

Serial transmission asynchronous. can be synchronous or

In synchronous transmission, the two units share a common clock frequency and bits are transmitted continuously at the rate dictated by the clock pulses.

In asynchronous transmission, binary information is sent only when it is available and the line remains idle when there is no information to be transmitted. A serial asynchronous data transmission technique used in many interactive terminals employs special bits that are inserted at both ends of the character code.

With this technique, each character consists of three parts: a start bit, the character bits, and stop bits. The convention is that the transmitter rests at the 1-state when no characters are transmitted. The first bit, called the start bit, is always a 0 and is used to indicate the beginning of a character. The last bit called the stop bit is always a 1.

A transmitted character can be detected by the receiver from knowledge of the transmission rules: 1. When a character is not being sent, the line is kept in the 1-state. 2. The initiation of a character transmission is detected from the start bit, which is always 0. 3. The character bits always follow the start bit. 4. After the last bit of the character is transmitted, a stop bit is detected.

A clock in the receiver examines the line at proper bit times. The receiver knows the transfer rate of the bits and the number of character bits to accept.

As an illustration, consider the serial transmission of a terminal whose transfer rate is 10 characters per second.
Each transmitted character consists of a start bit, eight information bits, and two stop bits, for a total of 11 bits. Ten characters per second means that each character takes 0.1 s for transfer. See there are 11 bits to be transmitted, it follows that the bit time is 9.09 ms. The baud rate is defined as the rate at which serial information is transmitted.

The terminal has a keyboard and a printer. Every time a key is depressed, the terminal sends 11 bits serially along a wire. To print a character in the printer, an 11-bit message must be received along another wire. The terminal interface consists of a transmitter and a receiver. The transmitter accepts an 8-bit character from the computer and proceeds to send a serial 11bit message into the printer line. The receiver accepts a serial 11-bit message from the keyboard line and forwards the 8-bit character code into the computer.

Integrated circuits are available which are specifically designed to provide the interface between computer and similar interactive terminals. Such a circuit is called an asynchronous communication interface or a universal asynchronous receiver- transmitter (UART).

Asynchronous communication Interface:

The block diagram of an asynchronous communication interface is shown in Fig. 11-8. It functions as both a transmitter and a receiver. The interface is initialized for a particular mode of transfer by means of a control byte that is loaded into its control register. The transmitter register accepts a data byte from the CPU through the data bus. This byte is transferred to a shift register for serial transmission. The receiver portion receives serial information into another shift register, and when a complete data byte is accumulated, it is transferred to the receiver register.

The CPU can select the receiver register to read the byte through the data bus. The bits in the status register are used for input and output flags and for recording certain errors that may occur during the transmission. The CPU can read the status register to check the status of the flag bits and to determine if any errors have occurred. The chip select and the read and write control lines communicate with the CPU. The chip select (CS) input is used to select the interface through the address bus. The register select (RS) is associated with the read (RD) and write (WR) controls. The register selected is a function of the RS value and the RD and WR status, as listed in the table.

Function Table:

Two bits in the status register are used as flags. One bit used to indicate whether the transmitter register is empty and another bit is used to indicate whether receiver register is full.

Operation of transmitter:
The CPU reads the status register and checks the flag to see if the transmitter register is empty. If it is empty, the CPU transfers a character to the transmitter register and the interface clears the flag to mark the register full. The first bit in the transmitter shift register is set to 0 to generate a start bit. The character is transferred in parallel from the transmitter register to the shift register and the appropriate number of stop bits are appended into the shift register. The transmitter register is then marked empty. The character can now be transmitted one bit at a time by shifting the data in the shift register at the specified baud rate.

Operation of receiver:
The receiver data input is in the 1-state when the line is idle. The receiver control monitors the receive-data line for a 0 signal to detect the occurrence of a start bit.

Once a start bit has been detected, the incoming bits of the character are shifted into the shift register at the prescribed baud rate.
After receiving the data bits, the interface checks for the parity and stop bits. The character without the start and stop bits is then transferred in parallel from the shift register to the receiver register. The flag in the status register is set to indicate that the receiver register is full.

Possible Errors checked by the interface:

Three possible errors that the interface checks during transmission are parity error, framing error, and overrun error. Parity error occurs if the number of ls in the received data is not the correct parity.

A framing error occurs if the right number of stop bits is not detected at the end of the received character. An overrun error occurs if the CPU does not read the character from the receiver register before the next one becomes available in the shift register.

Modes of Transfer:
Binary information received from an external device is usually stored in memory for later processing. The CPU merely executes the I/O instructions and may accept the data temporarily, but the ultimate source or destination is the memory unit. Data transfer to and from peripherals may be handled in one of three possible modes: 1) Programmed I/O 2) Interrupt-initiated I/O 3) Direct Memory Access (DMA)

Programmed I/O:
Programmed I/O operations are the result of I/O instructions written in the computer program.

Each item transfer is initiated by an instruction, usually the transfer is to and from a CPU register and peripheral. Other instructions are needed to transfer the data to and from CPU and memory.
Transferring data under program control requires constant monitoring of the peripheral by the CPU. Once a data transfer is initiated, the CPU is required to monitor the interface to see when a transfer can again be made.

Interrupt initiated I/O has been adopted to avoid the CPU idle time by using interrupt facility and special commands. In Direct Memory Access (DMA), the interface transfer data into and out of the memory unit through the memory bus. Many computers combine the interface logic with the requirements for DMA into one unit and call it an I/O processor (IOP). IOP can handle many peripherals through a DMA and interface facility.

Example of Programmed I/O:

In the programmed I/O method, the I/o device does not have direct access to memory.

A transfer from an I/O device to memory requires the execution of several instructions by the CPU.
Instructions including input instructions (from device to CPU) and store instructions (from CPU to memory). The example of data transfer from an I/O device through an interface into the CPU is shown in coming diagram.

The device transfers bytes of data one at a time as they are available. The device puts data on I/O bus and enables data valid line. Once interface receives data byte it enables the Data accepted line. It uses the Handshaking approach. The flow chart is show in the below figure.

Read the status register. Check the flag bit, if equal to 1 step 3 else go to step 1. Read the data register.

Interrupt initiated I/O:

An alternative to the CPU constantly monitoring the flag is to let the interface inform the computer when it is ready to transfer the data. This mode of transfer uses interrupt facility. While the CPU is running the program, it does not check the flag, however when the flag is set the computer is momentarily interrupted from the proceeding with current program. The CPU deviates from what it is doing to take care of the input and output transfer. The way that the processor chooses the branch address of the service routine varies from one unit to another.

In principle, there are two methods for accomplishing this one is Vectored Interrupt and another is Non vectored interrupt. In a non-vectored interrupt, the source that interrupts supplies the branch address is assigned to a fixed location in memory.

In a vectored interrupt, the source that interrupts supplies the branch information to the computer called interrupt vector. In some computers the interrupt vector is the first address of the I/o service routine or it may be the address that points to a location in memory where the beginning address of the I/O service routine is stored.