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General-purpose microprocessor

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CPU for Computers No RAM, ROM, I/O on CPU chip itself Example:Intel‟s x86, Motorola‟s 680x0

CPU GeneralPurpose Microprocessor

Data Bus

Many chips on mother‟s board

RAM

ROM

I/O Port

Timer

Serial COM Port

Address Bus General-Purpose Microprocessor System

Microcontroller :
  

A smaller computer On-chip RAM, ROM, I/O ports... Example:Motorola‟s 6811, Intel‟s 8051, Zilog‟s Z8 and PIC 16X

CPU

RAM ROM

A single chip
I/O Port
Serial Timer COM Port Microcontroller

Microprocessor vs. Microcontroller
Microprocessor  CPU is stand-alone, RAM, ROM, I/O, timer are separate  designer can decide on the amount of ROM, RAM and I/O ports.  expansive  versatility  general-purpose Microcontroller • CPU, RAM, ROM, I/O and timer are all on a single chip • fix amount of on-chip ROM, RAM, I/O ports • for applications in which cost, power and space are critical • single-purpose

Embedded System Embedded system means the processor is embedded into that application. video game player  . there is only one application software that is typically burned into ROM.  Example:printer.  An embedded product uses a microprocessor or microcontroller to do one task only.  In an embedded system. keyboard.

packaging. C compilers. technical support wide availability and reliable sources of the microcontrollers. . 2. debuggers. emulator. size. the amount of ROM and RAM. power consumption • easy to upgrade • cost per unit availability of software development tools • assemblers.Three criteria in Choosing a Microcontroller 1. simulator. meeting the computing needs of the task efficiently and cost effectively • speed. 3. the number of I/O ports and timers.

External interrupts Interrupt Control On-chip ROM for program code Timer/Counter On-chip RAM Timer 1 Timer 0 Counter Inputs CPU Serial Port OSC Bus Control 4 I/O Ports P0 P1 P2 P3 TxD RxD Address/Data .

Comparison of the 8051 Family Members Feature ROM (program space in bytes) RAM (bytes) Timers I/O pins Serial port Interrupt sources 8051 4K 128 2 32 1 6 8052 8K 256 3 32 1 8 8031 0K 128 2 32 1 6 .

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5(AD5) P0.6 P1.2 P1.5(A13) P2.6(A14) P2.7 RST (RXD)P3.2(A10) P2.4 (T1)P3.5 P1.1 (INT0)P3.4(AD4) P0.7(AD7) EA/VPP ALE/PROG PSEN P2.0(AD0) P0.5 (WR)P3.1(A9) P2.2 (INT1)P3.4(A12) P2.3 (T0)P3.3(AD3) P0.7 XTAL2 XTAL1 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 8051 (8031) Vcc P0.3(A11) P2.7(A15) P2.4 P1.0(A8)  .1 P1.1(AD1) P0.2(AD2) P0.0 P1.0 (TXD)P3.3 P1.6(AD6) P0.PDIP/Cerdip P1.6 (RD)P3.

 The voltage source is +5V.  Way 1:using a quartz crystal oscillator   Way 2:using a TTL oscillator   .18):  These 2 pins provide external clock.Vcc(pin 40):  Vcc provides supply voltage to the chip.  GND(pin 20):ground  XTAL1 and XTAL2(pins 19.

 It is a power-on reset. the microcontroller will reset and all values in registers will be lost. RST(pin 9):reset  It is an input pin and is active high(normally low). ▪ The high pulse must be high at least 2 machine cycles. ▪ Upon applying a high pulse to RST. ▪ Reset values of some 8051 registers  .

 For 8051.  “/” means active low.  The /EA pin is connected to GND to indicate the code is stored externally.  /PSEN & ALE are used for external ROM./EA(pin 31):external access  There is no on-chip ROM in 8031 and 8032 .  /PSEN(pin 29):program store enable  This is an output pin and is connected to the OE pin of the ROM in 8031 based systems  . /EA pin is connected to Vcc.

 The ALE pin is used for de-multiplexing the address and data by connecting to the G pin of the 74LS373 latch. P2.  .  8051 port 0 provides both address and data.ALE(pin 30):address latch enable  It is an output pin and is active high.  All I/O pins are bi-directional.  I/O port pins  The four ports P0. P1.  Each port uses 8 pins. and P3.

  Using a quartz crystal oscillator We can observe the frequency on the XTAL2 pin. C2 XTAL2 30pF C1 XTAL1 30pF GND .

machine cycle = 1 / 921.6 kHz = 1. Solution: (a) 11.333 MHz.6 kHz.75 s  .085 s (b) 16 MHz / 12 = 1.Find the machine cycle for (a) XTAL = 11.333 MHz = 0.0592 MHz / 12 = 921.0592 MHz (b) XTAL = 16 MHz. machine cycle = 1 / 1.

Register PC ACC B PSW SP DPTR RAM are all zero. Reset Value 0000 0000 0000 0000 0007 0000  .

Vcc + 10 uF 30 pF 11.2 K 30 pF 18 X2 9 RST 31 EA/VPP X1 19  .0592 MHz 8.

Vcc 31 10 uF 30 pF EA/VPP X1 X2 RST 9 8.2 K  .

  .7)  Port 3(pins 10-17):P3(P3.X (X=0..X.7)  Port 1(pins 1-8) :P1(P1.0~P2.The 8051 has four I/O ports  Port 0 (pins 32-39):P0(P0.0~P3. ▪ Named P0.7)  Each port has 8 pins.0~P1.. P2. P1.0~P0..X..7)  Port 2(pins 21-28):P2(P2.X ▪ Ex:P0.1. P3.7).7 is the bit 7(MSB)of P0 ▪ These 8 bits form a byte.0 is the bit 0(LSB)of P0 ▪ Ex:P0.  Each port can be used as input or output (bi-direction).

Registers A B R0 R1 R2 R3 R4 R5 R6 Some 8051 16-bit Register PC PC DPTR DPH DPL R7 Some 8-bit Registers of the 8051 .

dest = source .A=„r‟ OR 72H .B=the content of F9‟th byte of RAM MOV DPTR.72H AL.72H ” the content of 72‟th byte of RAM will replace in Accumulator.3 MOV . #‟r‟ R4.#76H MOV P1.#‟r‟ A.72H A.MOV dest.#72H ≠ After instruction “MOV 8086 MOV MOV MOV MOV Note 2: MOV .#7634H MOV DPL.A Note 1: MOV A.A=72H .[BX] A.72H AL.mov A to port 1 MOV A. 8051 MOV MOV MOV AL.72H A.source MOV MOV MOV MOV A.#62H B.R4=62H .R3 ≡ A.#72H A.‟r‟ BX.0F9H .#34H MOV DPH.#72H A.

0F3H .ADD A. Source .A=A+[6] or A=A+R6 .A=A+SOURCE ADD ADD ADD ADD A.#6 A.A=A+[0F3H] .6 A.A=A+R6 .A=A+6 .R6 A.

bit 7 from port 3 =1 .A=0 . 20h Page 359.7 ACC.360 C P0.set high D5 of RAM loc.2 05 CLR instruction is as same as SETB i.bit 2 from ACCUMULATOR =1 Bit Addressable .e: CLR C .SETB CLR SETB SETB SETB SETB SETB Note: bit bit . bit=0 .CY=0 But following instruction is only for CLR: CLR A . CY=1 .0 P3.bit 0 from port 0 =1 . bit=1 .

CY=1 .source .R5 A.source .A=A+R5+1 .A=A+source+CY .CY=1 A.SUBB SETB C SUBB A.A=A-R5-1 ADC SETB C ADC A.R5 .A=A-source-CY .

.#55H .byte=byte-1 .1’s complement A.A DELAY L01  CALL NOP & RET & RETI All are like 8086 instructions. [40]=[40]-1 CPL Example: MOV L01: CPL MOV ACALL SJMP A .byte=byte+1 .A=01010101 B A P1.DEC INC INC DEC DEC byte byte R7 A 40H .

#08H RR – RL – RRC – RLC A EXAMPLE: RR A .ORL .XRL EXAMPLE: MOV R5.#89H ANL R5.ANL .

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abs OH PROGRAM Myfile.#12H HERE EDITOR PROGRAM Myfile.R5 A.obj LINKER PROGRAM Myfile.#0 A.hex .asm ASSEMBLER PROGRAM Myfile.lst Other obj file Myfile.#25H R7.#34H A.ORG MOV MOV MOV ADD ADD HERE: SJMP END 0H R5.

 ROM memory map in 8051 family 4k 0000H 0000H 8k 0000H 32k 0FFFH DS5000-32 8751 AT89C51 1FFFH 8752 AT89C52 7FFFH from Atmel Corporation from Dallas Semiconductor .

 RAM memory space allocation in the 8051 7FH Scratch pad RAM Available as a place to save byte-sized data 30H 2FH Bit-Addressable RAM 20H 1FH 18H 17H 10H 0FH 08H 07H 00H Register Bank 2 Register Bank 1 (Stack) Register Bank 0 Register Bank 3 Bit addressable space to save single-bit data .

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2 PSW.5 PSW.3 PSW.1 PSW.0 AC -RS1 RS0 OV -P Address 00H-07H 08H-0FH 10H-17H 18H-1FH .7 CY Auxiliary carry flag Available to the user for general purpose Register Bank selector bit 1 Register Bank selector bit 0 Overflow flag User define bit Parity flag Set/Reset odd/even parity RS1 0 0 1 1 RS0 0 1 0 1 Register Bank 0 1 2 3 PSW.6 PSW. PSW Register CY AC F0 RS1 RS0 OV -P Carry flag PSW.4 PSW.

Instructions that Affect Flag Bits: Note: X can be 0 or 1 .

#38H ADD A.#64H 9C +64 ---100 CY=1 AC=1 10011100 +01100100 -------------00000000 P=0 Example: MOV A.#93H 88 +93 ---11B CY=1 AC=0 10001000 +10010011 -------------00011011 P=0 Example: MOV A.#88H ADD A.#2FH 38 +2F ---67 CY=0 AC=1 00111000 +00101111 -------------01100111 P=1 .Example: MOV A.#9CH ADD A.

Immediate  Register  Direct  Register Indirect  Indexed  .

#65H A.#65H DPTR.Num DPTR.#data1 100H db “IRAN” .#65H Example : Num … MOV MOV … ORG data1: EQU 30 R0.MOV MOV MOV MOV MOV A.#‟A‟ R6.#2343H P1.

A A. Rn . R6 . Rn DPL...n=0. movement of data between Rn registers is not allowed. . A Rm.MOV ADD MOV Rn..7 MOV MOV DPTR.

R4 . . it is most often used to access RAM loc. ≡ MOV B.A  .A it is important to note that when using direct addressing any instruction which refers to an address between 00h and 7Fh is referring to Internal Memory. MOV R6. R2 . ≡ MOV A. R2 MOV 80H. 40H 56H. Any instruction which refers to an address between 80h and FFh is referring to the SFR control registers that control the 8051 microcontroller itself. ≡ MOV A. 2 . A A.#66H . #66H MOV 0F0H. 30 – 7FH. MOV MOV MOV MOV R0. ≡ MOV P1.Although the entire of 128 bytes of RAM can be accessed using direct addressing mode. 4 6. copy R2 to R6 .R2 is invalid ! SFR register and their address MOV 0E0H.

A.A INC R0 INC R1 DJNZ R2.@Ri @R1.37h MOV R1. ADD and SUBB insructions. counter  jump .10 L1: MOV A. register is used as a pointer to the data.L1 . the content of register R0 or R1 is sources or target in MOV. source pointer . move content of RAM loc.Where address is held by Ri into A ( i=0 or 1 ) MOV MOV In other word.B .@R0 MOV @R1. Solution: MOV R0. In this mode. Example: Write a program to copy a block of 10 bytes from RAM location sterting at 37h to RAM location starting at 59h. dest pointer .59h MOV R2.

Indirect addressing always refers to Internal RAM. it never refers to an SFR.  .  using this we can not write data to serial port by making use of its SFR address which is 99h.

 This mode is widely used in accessing data elements of look-up table entries located in the program (code) space ROM at the 8051 MOVC A. . The “C” means code.@A+DPTR A= content of address A +DPTR from ROM Note: Because the data elements are stored in the program (code ) space ROM of the 8051. it uses the instruction MOVC instead of MOV.

Example: Assuming that ROM space starting at 250h contains “Hello.@A+DPTR JZ L2 MOV @R0.0  END Notice the NULL character .------------------------------------ORG 250H MYDATA: DB “Hello”. Solution: ORG 0 MOV DPTR.#40H L1:CLR A MOVC A. write a program to transfer the bytes into RAM locations starting at 40h.A INC DPTR INC R0 SJMP L1 L2:SJMP L2 .0.#MYDATA MOV R0. .”. as end of string and how we use the JZ instruction to detect that.

---------------------------------------------------ORG 300H TAB1: DB 0.81  END .#0FFH MOV P1.49.9.16.P1 MOVC A.A L01: MOV A.1.64.Example: Write a program to get the x value from P1 and send x2 to P2. #TAB1 MOV A.4.A SJMP L01 .36. continuously .@A+DPTR MOV P2. Solution: ORG 0 MOV DPTR.25.

And sent Sum to LCD a) in hex b) in decimal Write a program to subtract P1 from P0 and send result to LCD  (Assume that “ACAL DISP” display A to LCD )  .Exercise:  Write a program to add n 16-bit number. Get n from port 1.

A = A/B. MUL MOV MOV MUL MUL MOV MOV MUL AB A.#65H AB AB A. B=5 .B=0EH.B|A = A*B .#25 B.A=2.#10 AB .#25H B. A=99H .25H*65H=0E99 . B = A mod B  .

7FH Scratch pad RAM 30H  2FH Bit-Addressable RAM 20H 1FH 18H 17H 10H 0FH 08H 07H 00H Register Bank 3 Register Bank 2 (Stack) Register Bank 1 Register Bank 0 . When 8051 powered up. The register used to access the stack is called SP (stack pointer) register. the SP register contains value 07. which means that it can take value 00 to FFH. The stack pointer in the 8051 is only 8 bits wide.

#25H R1.Example: MOV MOV MOV PUSH PUSH PUSH R6.#0F3H 6 1 4 0BH 0AH 09H 08H Start SP=07H 0BH 0AH 09H 08H 25 0BH 0AH 09H 08H 12 25 0BH 0AH 09H 08H F3 12 25 SP=08H SP=09H SP=08H .#12H R4.

A .#0. then add 3 to the accumulator ten time Solution: MOV MOV AGAIN: ADD DJNZ MOV A.AGAING .repeat until R2=0 (10 times) R5. DJNZ: Write a program to clear ACC.#10 A. R2.#03 R2.

 JZ JNZ Other conditional jumps : Jump if A=0 Jump if A/=0 Decrement and jump if A/=0 Jump if A/=byte Jump if byte/=#data Jump if CY=1 Jump if CY=0 DJNZ CJNE A.#data JC JNC JB JNB JBC Jump if bit=1 Jump if bit=0 Jump if bit=1 and clear bit .byte CJNE reg.

SJMP(short jump) In this 2-byte instruction. . The relative address range of 00-FFH is divided into forward and backward jumps. that is . It is a 3-byte instruction in which the first byte is the opcode. within -128 to +127 bytes of memory relative to the address of the current PC. The first byte is the opcode and the second byte is the relative address of the target location.SJMP and LJMP: LJMP(long jump) LJMP is an unconditional jump. and the second and third bytes represent the 16-bit address of the target location. The 20byte target address allows a jump to any memory location from 0000 to FFFFH.

else if R0<R1 then send 0FFh to port 2. . If R0>R1 then send 1 to port 2.R1.Exercise: Write a program that compare R0. else send 0 to port 2.

Another control transfer instruction is the CALL instruction. Therefore. the first byte is the opcode an the second and third bytes are used for the address of target subroutine. which is used to call a subroutine.  LCALL(long call) In this 3-byte instruction. . LCALL can be used to call subroutines located anywhere within the 64K byte address space of the 8051.

 ACALL (absolute call) ACALL is 2-byte instruction in contrast to LCALL. The only difference is that the target address for LCALL can be anywhere within the 64K byte address space of the 8051 while the target address of ACALL must be within a 2Kbyte range. the target address of the subroutine must be within 2K bytes address because only 11 bits of the 2 bytes are used for the address. which is 13 bytes. There is no difference between ACALL and LCALL in terms of saving the program counter on the stack or the function of the RET instruction. . Since ACALL is a 2-byte instruction.

.0 ~ P1.e.Port 1(pins 1-8)   Port 1 is denoted by P1. write CPU data to the external pin)  P1 as an input port (i. read pin data into CPU bus) .e.  P1..7  We use P1 as examples to show the operations on ports.  P1 as an output port (i.

Read latch TB2 Vcc Load(L1) Internal CPU bus Write to latch D Q P1.X pin M1 TB1 Read pin P0.x 8051 IC .X Clk Q P1.

 Each pin of I/O ports  Internal CPU bus:communicate with CPU  A D latch store the value of this pin ▪ D latch is controlled by “Write to latch” ▪ Write to latch=1:write data into the D latch  2 Tri-state buffer: ▪ TB1: controlled by “Read pin” ▪ Read pin=1:really read the data present at the pin ▪ TB2: controlled by “Read latch” ▪ Read latch=1:read value from internal latch  A transistor M1 gate ▪ Gate=0: open ▪ Gate=1: close .

Output Input Tri-state control (active high) L L H H Low H H Highimpedance (open-circuit)  .

X pin output 1 TB1 Read pin 8051 IC . output pin is 1.Read latch TB2 Vcc Load(L1) 2.X Clk Q P1. write a 1 to the pin Internal CPU bus Write to latch D Q Vcc 1 0 M1 P1.

write a 0 to the pin Internal CPU bus Write to latch D Q ground 0 1 M1 P1.X Clk Q P1.Read latch TB2 Vcc Load(L1) 2. output pin is 1.X pin output 0 TB1 Read pin 8051 IC .

 You can write to P1 directly. Send data to Port 1: MOV A. .A ACALL DELAY CPL A SJMP BACK BACK:  Let P1 toggle.#55H MOV P1.

A . PX ▪ JNB P2. P1 ← P1 AND A ▪ ORL P1. A . jump if P2.1 is not set ▪ JB P2.1. ▪ ANL P1. increase P1 ▪ Figure C-17 ▪ Table C-6 Read-Modify-Write Instruction (or Table 8-5) . TARGET . there are two possibilities:  Read the status of the input pin. P1 ← P1 OR A ▪ INC P1 .1. (from external pin value) ▪ MOV A. C-12  Read the internal latch of the output port. TARGET .1 is set ▪ Figures C-11. jump if P2. When reading ports.

X pin Write to latch Clk Q 0 M1 TB1 Read pin 3. MOV A. Read pin=1 Read latch=0 Write to latch=1 8051 IC . write a 1 to the pin MOV P1.X P1.#0FFH Internal CPU bus TB2 Vcc Load(L1) 1 1 2.Read latch 1.P1 external pin=High D Q P1.

X P1. Read pin=1 Read latch=0 Write to latch=1 8051 IC . write a 1 to the pin MOV P1.X pin Write to latch Clk Q 0 M1 TB1 Read pin 3.P1 external pin=Low D Q P1. MOV A.Read latch 1.#0FFH Internal CPU bus TB2 Vcc Load(L1) 1 0 2.

#0FFH P1.A=11111111B . P2 and P3 have similar methods.A BACK .send data to P2 BACK:  To be an input port. MOV MOV MOV MOV SJMP A.get data from P0 . the port must be programmed by writing 1 to all the bit.A A.P1 P2. In order to make P1 an input. . P1.make P1 an input port . P0.

TARGET JB P1.3.Y.Y JNB P2.. JB PX.PX Examples MOV A.TARGET MOV C.4 to CY . MOV C. Following are instructions for reading external pins of ports: Mnemonics MOV A.P2 Description Bring into A the data at P2 pins JNB PX.3 is high Copy status of pin P2...Y.1 is low Jump if pin P1.P2..1.4 Jump if pin P2.PX.

▪ D latch of P1. The read latch activates TB2 and bring the data from the Q latch into CPU.P1=11110101 1. . 3. ▪ This data is ORed with bit 1 of register A. The latch is modified.0) has value 1.#55H . The result is written to the external pin. 4.0=0 2. ▪ Read P1.0 has value 1. ▪ External pin (pin 1: P1. Get 1.P1=01010101 ORL P1. Exclusive-or the Port 1: MOV P1.#0F0H . CPU performs an operation.

X pin Vcc D Q P1. write result to latch Read pin=0 Read latch=0 Write to latch=1 Load(L1) 0 1 4.X 0 M1 Clk Q TB1 Read pin 8051 IC .X=0 initially) Read latch TB2 2.X=1 P1.X OR 1 0 Internal CPU bus 1 Write to latch 3. P1.1. CPU compute P1. Read pin=0 Read latch=1 Write to latch=0 (Assume P1.

Read-modify-write Instructions  Table C-6  This features combines 3 actions in a single instruction: 1. CPU reads the latch of the port 2. CPU perform the operation 3. Modifying the latch 4. Writing to the pin  Note that 8 pins of P1 work independently.

Exclusive-or the Port 1: MOV P1,#55H ;P1=01010101 AGAIN: XOR P1,#0FFH ;complement ACALL DELAY SJMP AGAIN  Note that the XOR of 55H and FFH gives AAH.  XOR of AAH and FFH gives 55H.  The instruction read the data in the latch (not from the pin).  The instruction result will put into the latch and the pin.

Mnemonics
ANL ORL XRL JBC PX.Y, TARGET CPL INC DEC DJNZ PX, TARGET

Example
ANL P1,A ORL P1,A XRL P1,A JBC P1.1, TARGET CPL P1.2 INC P1 DEC P1 DJNZ P1,TARGET

MOV PX.Y,C
CLR PX.Y SETB PX.Y

MOV P1.2,C
CLR P1.3 SETB P1.4

▪ Why we need to set the pin first?  Read the value come from the latch(not from the external pin).  How to write the data to a pin? How to read the data from the pin?  Read the value present at the external pin. ▪ Why the instruction is called read-modify write? .

and P3 have internal pull-up resisters.X and P0.   However. for a programmer.P1.X. P2.  Compare the figures of P1.  All the ports upon RESET are configured as output. P1.  . P2 and P3. and P3 are not open drain. it is the same to program P0.  P1. P2.  P0 has no internal pull-up resistors and does not connects to Vcc inside the 8051.  P0 is open drain.

Read latch TB2 Internal CPU bus Write to latch D Q P1.X Clk Q P0.x 8051 IC .X pin M1 TB1 Read pin P1.

 When P0 is used for simple data I/O we must connect it to external pull-up resistors.  With external pull-up resistors connected upon reset.  P0 is an open drain. port 0 is configured as an output port.  Each pin of P0 must be connected externally to a 10K ohm pull-up resistor.  Open drain is a term used for MOS chips in the same way that open collector is used for TTL chips. .

1 P0.7 Port 0 .4 8951 P0.2 8751 P0.6 P0.5 P0.0 DS5000 P0.Vcc 10 K P0.3 P0.

When connecting an 8051/8031 to an external memory.  .  8031 is capable of accessing 64K bytes of external memory. P2 provides address A8-A15.  When P0 is used for address/data multiplexing. it is connected to the 74LS373 to latch the address. P0 provides data lines D0-D7.  Also.  There is no need for external pull-up resistors as shown in Chapter 14.  16-bit address:P0 provides both address A0-A7. the 8051 uses ports to send addresses and read instructions.

7 D7 A8 A15 8051 ROM .0 P2.PSEN ALE P0.0 P0.7 G D 74LS373 OE OC A0 A7 D0 EA P2.

PSEN ALE P0.0 P0. Send address to ROM 2. 74373 latches the address and send to OE ROM OC G 74LS373 A0 D A7 Address D0 EA P2.7 D7 A8 A12 8051 ROM .0 P2.7 1.

ROM send the instruction back A8 A12 8051 ROM .0 P0.7 D7 3.0 P2.7 2.PSEN ALE P0. 74373 latches the address and send to ROM G D 74LS373 OE OC A0 A7 Address D0 EA P2.

P0 provides address A0-A7.  When ALE=1. .  The reason is to allow P0 to multiplex address and data. P0 provides data D0-D7. The ALE pin is used for de-multiplexing the address and data by connecting to the G pin of the 74LS373 latch.  When ALE=0.

  Port 2 does not need any pull-up resistors since it already has pull-up resistors internally. P2 are used to provide address A8-A15. . In an 8031-based system.

/RD(Chapter 14)  . /INT1(Chapter 11)  Timer/counter:T0.  Serial communications signal:RxD. TxD(Chapter 10)  External interrupt:/INT0.Port 3 does not need any pull-up resistors since it already has pull-up resistors internally. T1(Chapter 9)  External memory accesses in 8031-based system:/WR.  Although port 3 is configured as an output port upon reset. this is not the way it is most commonly used.  Port 3 has the additional function of providing signals.

7 Function RxD TxD INT0 INT1 T0 T1 WR RD Pin 10 11 12 13 14 15 16 17  .5 P3.6 P3.P3 Bit P3.4 P3.0 P3.2 P3.1 P3.3 P3.

Timer 0 registers TL0 ( timer 0 low byte ) TH0 ( timer 0 high byte ) .

Timer 1 registers TL1 ( timer 1 low byte ) TH1 ( timer 1 high byte ) .

TMOD (timer mode) register .

Reset by code for low level INT.TF0/TF1: Timer0/1 overflow flag is set when the timer counter overflows. reset to stop the timer0/1 External interrupt 9/1 edge detected flag1 is set when a falling edge interrupt on the external port 0/1. reset(cleared) by hardware itself for falling edge transition-activated INT. reset by program TR0/TR1: IE0/IE1: Timer0/1 run control bit is set to start. External interrupt type (1: falling edge triggered. 0 low level triggered) IT0/IT1 .

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Mode 0 Programming0  Mode 0  works like mode 1  13-bit timer instead of 16bit  13-bit counter hold values 0000 to 1FFFH  when the timer reaches its maximum of 1FFFH. and TF is set . it rolls over to 0000.

Mode 1 programming  16-bit timer. can stop the timer with "CLR TR0" or "CLR TR1“ after the timer reaches its limit and rolls over. the registers TH and TL must be reloaded with the original value and TF must be reset to 0 . values of 0000 to FFFFH  TH and TL are loaded with a 16-bit initial value  timer started by "SETB TR0" for Timer 0 and "SETB TR1"      for Timer l timer count ups until it reaches its limit of FFFFH rolls over from FFFFH to 0000H sets TF (timer flag) when this timer flag is raised.

Steps to program in mode 1  Set timer mode 1 or 2  Set TL0 and TH0 (for mode 1 16 bit mode)  Set TH0 only (for mode 2 8 bit auto reload mode)  Run the timer  Monitor the timer flag bit .

5 bit. Timer 0 is used to generate the time delay .Create a square wave of 50% duty cycle (with equal portions high and low) on the P1.

0592 MHz (12MHz)  divide the desired time delay by 1.Finding values to be loaded into the timer  XTAL = 11.085ms (1ms) to get n  65536 – n = N  convert N to hex yyxx  set TL = xx and TH = yy .

Create a square wave of 50% duty cycle (with equal portions high and low) on the P1.5 bit. Timer 0 is used to generate the time delay

Assuming XTAL = 11.0592 MHz, write a program to generate a square wave of 50 Hz frequency on pin P2.3.

     

T = 1/50 Hz = 20 ms 1/2 of it for the high and low portions of the pulse = 10 ms 10 ms / 1.085 us = 9216 65536 - 9216 = 56320 in decimal = DC00H TL = 00 and TH = DCH The calculation for 12MHz crystal uses the same steps

"SETB TR0" or "SETB TR1“ starts to count up by incrementing the TL register counts up until it reaches its limit of FFH when it rolls over from FFH to 00. allows values of 00 to FFH TH is loaded with the 8-bit value a copy is given to TL timer is started by . clear TF mode 2 is an auto-reload mode . it sets high TF TL is reloaded automatically with the value in TH To repeat.Mode 2 programming  Mode 2 programming           8-bit timer.

select mode 2 load the TH start timer monitor the timer flag (TF) with "JNB” get out of the loop when TF=1 clear TF go back to Step 4 since mode 2 is auto-reload .Steps to program in mode 2 • • • • • • • load TMOD.

0 and (b) the smallest frequency achievable in this program. .Assuming that XTAL = 11. and the TH value to do that.0592 MHz. find (a) the frequency of the square wave generated on pin P1.

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8051 Interrupts .

Polling A single microcontroller can serve several devices.    The program which is associated with the interrupt is called the interrupt service routine (ISR) or interrupt handler. There are two ways to do that:  interrupts  polling. . Interrupts vs. An interrupt is an external or internal event that interrupts the microcontroller to inform it that a device needs its service.

Jumps to a fixed location in memory depend on type of interrupt Starts to execute the interrupt service routine until RETI (return from interrupt) Upon executing the RETI the microcontroller returns to the place where it was interrupted. Get pop PC from stack   .Steps in executing an interrupt   Finish current instruction and saves the PC on stack.

ADC. another serial port (UART) . etc)  Enhanced version has 22 sources  More timers. buffer empty. more external interrupts. Original 8051 has 6 sources of interrupts       Reset Timer 0 overflow Timer 1 overflow External Interrupt 0 External Interrupt 1 Serial Port events (buffer full. programmable counter array.

Each interrupt has a specific place in code memory where program execution (interrupt service routine) begins. External Interrupt 0: 0003h Timer 0 overflow: 000Bh External Interrupt 1: 0013h Timer 1 overflow: 001Bh Serial : 0023h Timer 2 overflow(8052+) 002bh Note: that there are only 8 memory locations between vectors. .

ISRs and Main Program in 8051 SJMP ljmp ORG ljmp ORG ljmp ORG ljmp ORG ljmp ORG main: … END main ORG 03H int0sr 0BH t0sr 13H int1sr 1BH t1sr 23H serialsr 30H .

Interrupt Enable (IE) register All interrupt are disabled after reset We can enable and disable them bye IE .

Enable . #10010110B .Enable .Enable .7 SETB ET0 SETB IE.0 SETB EX1 SETB IE.Enable .Enable .3 SETB EX0 SETB IE.1 SETB ET1 SETB IE.2 SETB ES SETB IE.4 by mov instruction Recommended in the first of program .Enabling and disabling an interrupt by bit operation Recommended in the middle of program SETB EA SETB IE.Enable All Timer0 ovrf Timer1 ovrf INT0 INT1 Serial port MOV IE.

0 .Timer 0. mode 2 .Start timer .Return from ISR to Main program .Jump above interrupt .#-50 SETB TR0 MOV IE. A 10khz square wave with 50% duty cycle ORG LJMP 0 MAIN 000BH P1.Enable timer 0 interrupt .Timer 0 interrupt vector .Toggle port bit .Main Program entry point .#82H SJMP $ END .#02H MOV TH0.50 us delay .Do nothing just wait ORG T0ISR:CPL RETI ORG 0030H MAIN: MOV TMOD.Reset entry poit .

6.7 143s 71s 2ms P1. Write a program using interrupts to simultaneously create 7 kHz and 500 Hz square waves on P1.6 1ms .7 and P1. 8051 P1.

Solution
ORG LJMP ORG LJMP ORG LJMP ORG MOV MOV SETB SETB MOV MOV SJMP CPL RETI CLR MOV MOV SETB CPL RETI END 0 MAIN 000BH T0ISR 001BH T1ISR 0030H TMOD,#12H TH0,#-71 TR0 TF1 IE,#8AH IE,#8AH $ P1.7 TR1 TH1,#HIGH(-1000) TL1,#LOW(-1000) TR1 P1.6

8051 P1.7

143s 71s

MAIN:

2ms

P1.6

1ms

T0ISR: T1ISR:

Notice that
 There is no need for a “CLR TFx” instruction in

timer ISR  8051 clears the TF internally upon jumping to ISR

Notice that
 We must reload timer in mode 1  There is no need on mode 2 (timer auto reload)

 

By low nibble of Timer control register TCON IE0 (IE1): External interrupt 0(1) edge flag.
 set by CPU when external interrupt edge (H-to-L) is detected.
 Does not affected by H-to-L while ISR is executed(no int on int)  Cleared by CPU when RETI executed.  does not latch low-level triggered interrupt

IT0 (IT1): interrupt 0 (1) type control bit.
 Set/cleared by software  IT=1 edge trigger  IT=0 low-level trigger

(MSB) TF1 TR1 Timer 1

TF0 TR0 Timer0

IE1

IT1 IE0 for Interrupt

(LSB) IT0

3) 0 12 IT1 IE1 (TCON.3) 0013 Edge-triggered .2) 0 12 IT0 0003 IE0 (TCON.External Interrupts Level-triggered (default) INT0 (Pin 3.3) Edge-triggered Level-triggered (default) INT0 (Pin 3.

ORG 0000H LJMP MAIN .interrupt service routine (ISR) .1 MOV R0.for hardware external interrupt INT1 .200 WAIT: DJNZ R0.WAIT CLR P1.1 RETI . .#10000100B WAIT2: SJMP WAIT2 END . ORG 0013H SETB P1. ORG 30H MAIN: SETB IT1 .main program for initialization ..on negative edge of INT1 MOV IE.

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7 Reti Org 0013h setb p1.7 Jb p3.7 Skip: Sjmp $ end .Org 0000h Ljmp main x0isr: Org 0003h clr p1.7 Reti x1isr: Org 0030h Main: mov ie.#85h Setb it0 Setb it1 Setb p1.skip Clr p1.2.

Timer interrupt0 (TF0) 3. External interrupt 0 (INT0) 2. Timer interrupt1 (TF1) 5. . Serial communication (RI+TI)  Priority can also be set to “high” or “low” by IP reg. All interrupts have a power on default priority order. External interrupt 1 (INT1) 4.   What if two interrupt sources interrupt at the same time? The interrupt with the highest PRIORITY gets serviced first. 1.

5: timer 2 interrupt priority bit(8052 only) IP.--- --- PT2 PS PT1 PX1 PT0 PX0 IP.2: external interrupt 1 priority bit IP.3: timer 1 interrupt priority bit IP.4: serial port interrupt priority bit IP.6: reserved IP.1: timer 0 interrupt priority bit IP.7: reserved IP.0: external interrupt 0 priority bit .

Int1 Int0 Timer0 Timer1 Serial Int1 Timer1 Int0 Timer0 Serial  MOV IP . 3. 2. 5. #00001100B gives priority order 1. 2. 4. 5. .-- --- PT2 PS PT1 PX1 PT0 PX0 MOV IP .2 gives priority order 1. 3. 4. #00000100B or SETB IP.

--- --- PT2 PS PT1 PX1 PT0 PX0    A high-priority interrupt can interrupt a low-priority interrupy All interrupt are latched internally Low-priority interrupt wait until 8051 has finished servicing the high-priority interrupt .