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CHAPTER- 2

ARM Processors
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INTRODUCTION
Originally Acorn RISC Machines,but now called as Advanced RISC Machines. Development started in 1985. Over 1 billion ARM processors were sold by 2001. ARM7TDMI was most successful ARM core.

ARM -- Advanced Risc Machines was established by


Acron, Apple & VLSI in 1990. ARM cores are used in mobile phones, handheld organizers(PDA),portable consumer devices.

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Version 1 The first ARM processor, developed at Acorn Computers Limited 1983-1985 26-bit address, no multiply or coprocessor support Version 2 Sold in volume in the Acorn Archimedes and A3000 products 26-bit addressing, including 32-bit result multiply and coprocessor Version 2a Coprocessor 15 as the system control coprocessor to manage cache Version 3 First ARM processor designed by ARM Limited (1990) ARM6 (macro cell) ARM60 (stand-alone processor) ARM600 (an integrated CPU with on-chip cache, MMU, write buffer) ARM610 (used in Apple Newton) 32-bit addressing, separate CPSR and SPSRs Add the undefined and abort modes to allow coprocessor emulation and virtual memory support in supervisor mode Version 3M Introduce the signed and unsigned multiply and multiplyaccumulate instructions that generate the full 64-bit result
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Version 4 Add the signed, unsigned half-word and signed byte load and store instructions Reserve some of SWI space for architecturally defined operation System mode is introduced Version 4T 16-bit Thumb compressed form of the instruction set is introduced Version 5T Introduced recently, a superset of version 4T adding the BLX, CLZ and BRK instructions Version 5TE Add the signal processing instruction set extension Version 6 Media processing extensions (SIMD) 2x faster MPEG4 encode/decode 2x faster audio DSP

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FEATURES
32 bit RISC*processor. High Code density.( Less memory) Hardware Debug Technology. Load store architecture. Variable cycle execution for certain instructions. Inline barrel shifter.

Thumb 16 bit instruction set.


Conditional execution : An instruction is only executed when a specific condition has been satisfied.

Enhanced Instructions: DSP


Orthogonal instruction Set Large 16 x 32 register file.
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Fixed op code width of 32 bits to ease decoding and pipelining. Powerful indexed addressing modes. Simple, but fast, 2-priority-level interrupt subsystem with switched register banks. Speed 1MHZ - 1.25 GHz

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T: Thumb D: On-chip debug support M: Enhanced multiplier I: Embedded ICE hardware T2: Thumb-2 S: Synthesizable code E: Enhanced DSP instruction set J: JAVA support, Jazelle Z: Should be TrustZone? F: Floating point unit H: Handshake, clockless design for synchronous or asynchronous design 4/24/2012 Dr.B.V.V.S.Kumar

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The ARM has seven basic operating modes: User : unprivileged mode under which most tasks run FIQ IRQ : entered when a high priority (fast) interrupt is raised : entered when a low priority (normal) interrupt is raised

Supervisor : entered on reset and when a Software Interrupt instruction is executed Abort : used to handle memory access violations

Undef
System
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: used to handle undefined instructions


: privileged mode using the same registers as user mode
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ARM : Register Set


Current Visible Registers
Abort Mode
r0 r1 r2 r3 r4 r5 r6

Banked out Registers


User FIQ
r8 r9 r10 r11 r12 r13 (sp) r14 (lr)

IRQ

SVC

Undef

r7 r8 r9 r10 r11 r12 r13 (sp) r14 (lr) r15 (pc)


cpsr spsr 4/24/2012

r13 (sp) r14 (lr)

r13 (sp) r14 (lr)

r13 (sp) r14 (lr)

r13 (sp) r14 (lr)

spsr Dr.B.V.V.S.Kumar

spsr

spsr

spsr

USER
r0 r1 r2 r3 r4 r5 r6 r7

FIQ
User mode r0-r7, r15, and cpsr

IRQ

SVC

UNDEF

ABORT

r8 r9 r10 r11 r12 r13 (sp) r14 (lr) r15 (pc)


cpsr

User mode r0-r12, r15, and cpsr

User mode r0-r12, r15, and cpsr

User mode r0-r12, r15, and cpsr

User mode r0-r12, r15, and cpsr

Thumb state Low registers

r9 r10 r11 r12 r13 (sp) r14 (lr)

r13 (sp) r14 (lr)

r13 (sp) r14 (lr)

r13 (sp) r14 (lr)

r13 (sp) r14 (lr)

Thumb state High registers

spsr

spsr

spsr

spsr

spsr

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ARM has 37 registers all of which are 32-bits long. 1 dedicated program counter 1 dedicated current program status register 5 dedicated saved program status registers 30 general purpose registers The current processor mode governs which of several banks is accessible. Each mode can access a particular set of r0-r12 registers a particular r13 (the stack pointer, sp) and r14 (the link register, lr) the program counter, r15 (pc) the current program status register, cpsr Privileged modes (except System) can also access a particular spsr (saved program status register)
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ARM ARCHITECTURE

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3- stage Pipeline

5- Stage Pipeline
FETCH DECODE FETCH EXEC DECODE MEMORY EXEC WRITE MEMORY WRITE

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Current Program Status Register (CPSR)

Condition code flags Interrupt Disable bits. N = Negative result from ALU I = 1: Disables the IRQ. Z = Zero result from ALU F = 1: Disables the FIQ. C = ALU operation Carried out V = ALU operation oVerflowed T Bit Sticky Overflow flag - Q flag Architecture xT only Architecture 5TE/J only T = 0: Processor in ARM state Indicates if saturation has occurred T = 1: Processor in Thumb state J bit Architecture 5TEJ only Mode bits J = 1: Processor in Jazelle state Specify the processor mode
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Instruction Set Design


ARM, Thumb and Jazelle

ARM instruction set 32-bit instructions,support load-store architecture,conditionally execution,use 3-address format Example : ADDS r0,r1,#1
Thumb instruction set 16-bit instructions, support load-store architecture, unconditionally execution (branch instructions), use 2-address format Example : ADD r1,#1 Jazelle instruction set 8-bit instructions, Javabyte code execution
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Instructions supported by the ARM Processors


ARM Instruction Set: standard 32-bit instruction set Thumb Instruction Set: 16-bit instruction set Jazelle Instruction Set: 8-bit instruction set

ARM Instruction Set supports six different types of instructions Data Processing Instructions Branch Instructions Load/Store Instructions Software Interrupt Instruction Program Status Register Instructions Coprocessor Instructionsoi
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Data Processing Instructions


used to manipulate data in general-purpose registers, employ a 3-address format, support barrel shifter. Arithmetic Instructions: ADD, ADC, SUB, SBC, RSB, RSC Move Instructions: MOV, MVN Bit-Wise Logical Instructions: AND, EOR, ORR, BIC Comparison Instructions: TST, TEQ, CMP, CMN Multiply Instructions: MUL, MLA
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Data Processing Instructions


Move Instructions

MOV {<cond>}{S} Rd,N Move 32 bit value in register If S suffix on data processing instruction,then it updates flags in the cpsr. Ex. MOV r7,r5 MOV r6,#immediate
MNV : Move the NOT of the 32 bit value into a register.

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DPI contd. Barrel Shifter Barrel Shifter Operations LSL = Logical Shift left LSR = Logical Shift right ASR = Arithmetic right shift ROR = Rotate right RRX = Rotate right extended MOV r0,r2,LSL #1 MOVr0,r3,LSL r2 MOVSr0,r1,ROR #4

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DPIcontd. Arithmetic Instructions ADD{S} Rd,Rn,N (Rd= Rn+N) ADD r0,r3,r4 (r0= r3+r4) ADC

RSB: Reverse subtract of two 32 bit values ( Rd = N-Rn)


RSC : Reverse subtract with carry SBC: Subtract with carry SUB: Subtract4/12/2006 Y.H.Dandawate 26 Comparison Instructions CMP {<cond>}Rn,N ( no need of S) CMN: Compare negated

TEQ: Test for equality of two 32 bit values


TST: Test bits of a 32 bit value ( AND)4/12/2006 Y.H.Dandawate 28 UMULL: Unsigned multiply long
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DPIcontd.

Arithmetic with Barrel Shifter (Write examples) Logical Instructions AND{S} Rd,Rn,N : Logical bitwise AND ORR : Logical bit wise OR EOR: Logical bitwise Exclusive OR BIC:Logical bit clear (AND NOT)

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Branch Instructions

B{<cond>} label : Branch BLlabel : branch with link pc=label lr= address of next instruction after the BL BX: Branch Exchange pc=Rm & 0xfffffffe, T = Rm &1 BLX : Branch exchange with link same as above , lr is used like BL

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Load-Store Instructions

Single register transfer LDR: load word into register (32) STR: Save word from register

LDRB: Load byte into a register (8)


STRB : Save byte from register LDRH: Load halfword into a register(16)

STRH: Save halfword


LDRSB: load signed byte into register LDRSH: load signed halfwordDr.B.V.V.S.Kumar into register 4/24/2012

DPIcontd.

Multiply Instructions MUL{S} Rd,Rm,Rs (Rd = Rm*Rs) MLA : Multiply and Accumulate

MLA Rd,Rm,Rs,Rn ( Rd=(Rm*Rs)+Rn) SMLAL: Signed Multiply accumulate long [Rdhi,Rdlo]= [Rdhi,Rdlo]+(Rm*Rs)

SMULL : Signed Multiply Long [Rdhi,Rdlo]=(Rm*Rs)


UMLAL: Unsigned multiply accumulate long
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ARM 920T

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ARM 1020E

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Basic format: ADD r0,r1,r2


ARM data instructions Basic format: ADD r0,r1,r2 Computes r1+r2, stores in r0. Immediate operand: (8-bit constant can be scaled by 2k) ADD r0,r1,#2 Computes r1+2, stores in r0 Set condition flags based on operation: ADDS r0,r1,r2

Recently-added assembler translation:


ADD r1,r2 = ADD r1,r1,r2 (but not MUL) set status flags
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ARM arithmetic instructions ADD, ADC : add (w. carry) [Rd] <= Op1 + Op2 + C SUB, SBC : subtract (w. carry) [Rd] <= Op1 Op2 + (C 1) RSB, RSC : reverse subtract (w. carry)

[Rd] <= OP2 Op1 + (C 1) MUL: multiply (32-bit product no immediate for Op2)
[Rd] <= Op1 x Op2 MLA : multiply and accumulate (32-bit result) MLA Rd,Rm,Rs,Rn : [Rd] <= (Rm x Rs) + Rn

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ARM logical instructions AND, ORR, EOR: bit-wise logical ops


BIC : bit clear [Rd] <= Op1 ^ Op2 LSL, LSR : logical shift left/right (combine with data ops) ADD r1,r2,r3, LSL #4 : [r1] <= r2 + (r3x16) Vacated bits filled with 0s

ASL, ASR : arithmetic shift left/right (maintain sign)


ROR : rotate right RRX : rotate right extended with C from CPSR 33-bit shift:

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ARM comparison instructions CMP : compare : Op1 Op2 CMN : negated compare : Op1 + Op2 TST : bit-wise AND : Op1 ^ Op2 TEQ : bit-wise XOR : Op1 xor Op2 These instructions only set the NZCV bits of CPSR no other result is saved. (Set Status is implied)
ARM move instructions MOV, MVN : move (negated) MOV r0, r1 ; sets r0 to r1 MOVN r0, r1 ; sets r0 to r1 MOV r0, #55 ; sets r0 to 55 Can use shift modifier to scale a value:

MOV r0,r1,LSL #6 ; [r0] <= r1 x 64 Recently-added pseudo-Op:


LSL rd,rn,shift = MOV rd,rn,LSL shift
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ARM load/store instructions Load operand from memory into target register LDR load 32 bits LDRH load halfword (16 bit unsigned #) & zero-extend to 32 bits LDRSH load signed halfword & sign-extend to 32 bits LDRB load byte (8 bit unsigned #) & zero-extend to 32 bits LDRSB load signed byte & sign-extend to 32 bits
Store operand from register to memory STR store 32-bit word STRH store 16-bit halfword (right-most16 bits of register) STRB : store 8-bit byte (right-most 8 bits of register)

ARM load/store addressing Addressing modes: base address + offset register indirect : LDR r0,[r1] with second register : LDR r0,[r1,-r2] with constant : LDR r0,[r1,#4] pre-indexed: LDR r0,[r1,#4]! post-indexed: LDR r0,[r1],#8
Immediate #operand = 12 bits (2s complement)

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ARM load/store examples ldr r1,[r2] ; address = (r2) ldr r1,[r2,#5] ; address = (r2)+5 ldr r1,[r2,#-5] ; address = (r2)-5 ldr r1,[r2,r3] ; address = (r2)+(r3) ldr r1,[r2,-r3] ; address = (r2)-(r3) ldr r1,[r2,r3,SHL #2] ; address=(r2)+(r3 x 4) Base register r2 is not altered in these instructions
ldr r1,[r2,#4]! ; use address = (r2)+4 ; r2<=(r2)+4 (pre-index) ldr r1,[r2,r3]! ; use address = (r2)+(r3) ; r2<=(r2)+(r3) (pre-index) ldr r1,[r2],#4 ; use address = (r2) ; r2<=(r2)+4 (post-index) ldr r1,[r2],[r3] ; use address = (r2) ; r2<=(r2)+(r3) (post-index)

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Additional addressing modes Base-plus-offset addressing:


LDR r0,[r1,#16] Loads from location [r1+16] Auto-indexing increments base register: LDR r0,[r1,#16]! Loads from location [r1+16], then sets r1 = r1 + 16

Post-indexing fetches, then does offset:


LDR r0,[r1],#16 Loads r0 from [r1], then sets r1 = r1 + 16

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