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INTERRUPT CONTROLLER FOR FPGA BASED MULTIPLE PROCESSOR

Click to edit Master subtitle style by Manoj Naresh Avinash

4/29/12

What is a Interrupt Controller?

The Interrupt Controller is a device commonly found in computer systems (both single-processor and multiprocessors) It deals with interrupts generated by the peripherals and the processors. It handles the interrupt priorities, and delegates the execution to a processor
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What is our Interrupt controller about? • This interrupt controller is for MPSoCs(Multiprocessors System-onChip) type of systems which are based on FPGA technology. 4/29/12 .

our Interrupt Controller distributes the workload of the interrupt handling among the available processors. Ø This feature decreases the interrupt management latency. Ø 4/29/12 .Our design allows a peripheral to interrupt any of the processors of the system. In detail.

Ø 4/29/12 .The Interrupt Controller allows to delegate specific processors to handle interrupts generated by certain peripherals (booking). Ø It supports interrupt broadcasting and allows inter-processor interrupts.

High performance computers. 4/29/12 . Complex embedded systems. Devices using peripheral sharing.Applications Ø Ø Ø Ø Reactive systems.

OPB Interface.INTERRUPT CONTROLLER ARCHITECTURE It is composed of two main components. Controller logic(Int core) 4/29/12 . 2. 1.

4/29/12 Interrupt controller architecture .

It interfaces the core with the main bus of the system.Interface Ø The interface is based on the On-chip Peripheral Bus (OPB)specification to allow memory mapped access from the processors. The interface sends the following signals for controller logic. Ø Ø 4/29/12 .

Ø Ø Ø Ø Ø Proc id: the identification of the processor accessing the controller.Ø Reg Addr: the register address where the processor wants to write to or to read from. Data in: the data to write. 4/29/12 . Data out: the data to read. Valid rd: read operation from the register specified by Reg Addr. Valid wr: write operation towards the register specified by Reg Addr.

3. Edge interrupt detection. 4/29/12 • . Register block. Irq generator. 1. It consists of 3 main parts.Controller logic • Implements the core logic of a computer. 2.

• – Interrupt Pending Register(IPR) stores the interrupts that are both 4/29/12 active and enabled. deciding which interrupts can be handled and managing of interrupt acknowledge signals. The various registers are Ø – Interrupt Status Register (ISR) stores the active interrupts. .Register block Ø It allows handling of interrupt priorities.

– Set Interrupt Enable (SIE) is a support for writing into IER. – Clear Interrupt Enable (CIE) is a 4/29/12 support for deleting from IER. . – Interrupt Acknowledge Register (IAR) is a support for disabling interrupts that receive the corresponding acknowledgment signal.– Interrupt Enable Register (IER) keeps track of which interrupts are allowed to be handled.

– Device Processor Waiting (DPW) is a support to store which interrupts have been booked. 4/29/12 . – Broadcast (BRO) is a support to store which interrupts have to be handled in broadcast way. – Master Enable Register (MER) is used for enabling our Interrupt Controller to manage interrupts.– Interrupt Vector Register (IVR) contains the identification of the next interrupt that must be served.

Edge Interrupt Detection Ø It detects interrupts coming from the IPs of the system and activates the logic which communicates pending requests to the connected processors. 4/29/12 .

Irq Generator Ø It contains the generation logic of the interrupt signals toward processors.Broadcast Interrupt Generator generates signals in case of interrupts that need to be propagated to all processors. . Ø 1. 2.Standard Interrupt Generator 4/29/12 handles all the other kinds of interrupt. It is composed of two main subblocks.

4/29/12 Irq generator .

The interrupts are detected by the Edge Interrupt Detection module. ü Interrupt management for these two cores has been previously enabled by writing on the IER register.Working Consider two application specific cores connected to the Interrupt Controller generate interrupts in the same time interval. ü 4/29/12 .

The first processor which detects the interrupt request chooses the active interrupt with the highest priority and sends the related acknowledgment. ü ü ü 4/29/12 . Writing on ISR also influences the content of the IPR register. The Interrupt Controller waits for acknowledgment.ü The Edge Interrupt Detection Module stores the arrival of the interrupts in ISR register. IRQ Generation raises two outputs toward two free processors (not handling other interrupts).

ü ü 4/29/12 .ü The second processor which detects the interrupt request chooses the second active interrupt and sends the related acknowledgment. The second processor starts executing the handler associated to the selected interrupt. From now on. the two processors will concurrently handle the two generated interrupts.

AND INTER-PROCESSOR COMMUNICATION: Booking: • Interrupt Controller allows to delegate specific processors to handle interrupts generated by certain peripherals. 4/29/12 • .BOOKING. This is accomplished by calling the Book Peripheral primitive. and specifying which is the peripheral to book. BROADCASTING.

When interrupt is generated. The addresses of the selected peripheral are registered by writing the BRO register. • • • .Broadcast • This interrupt is distributed by the interrupt controller to all processors.disables the normal flow. Broadcast interrupt having high 4/29/12 priority served first . it enables the broadcast logic.

Conclusions Ø This design efficiently distributes multiple interrupts on a multiprocessor. it supports several features useful in a multiprocessor system. exploiting CPU-level parallelism. Ø 4/29/12 . In addition. like booking. broadcasting and inter-processor interrupt.

Question??? 4/29/12 .