Preetha Sreekumar

Manipal Dubai

Semiconductor Manufacturing Processes
• • • • • • • • • • Design Wafer Preparation Front-end Processes Photolithography Etch Cleaning Thin Films Ion Implantation Planarization Test and Assembly
Wafer Preparation Design

Thin Films

Front-End Processes

Photolithography

Ion Implantation

Etch

Cleaning

Planarization

Test & Assembly

Preetha Sreekumar

Manipal Dubai

Design
• • • • • Establish Design Rules Circuit Element Design Interconnect Routing Device Simulation Pattern Preparation

The first operation is the design of the chip. When tens of millions of transistors are to be built on a square of silicon about the size of a child’s fingernail, the placing and interconnections of the transistors must be meticulously worked out. Each transistor must be designed for its intended function, and groups of transistors are combined to create circuit elements such as inverters, adders and decoders. The designer must also take into account the intended purpose of the chip. A processor chip carries out instructions in a computer, and a memory chip stores data. The two types of chips differ somewhat in structure. Because of the complexity of today’s chips, the design work is done by computer, although engineers often print out an enlarged diagram of a chip’s structure to examine it in detail.
Preetha Sreekumar Manipal Dubai

Wafer Preparation • • • • Polysilicon Refining Crystal Pulling Wafer Slicing & Polishing Epitaxial Silicon Deposition Wafer Preparation Design Thin Films Front-End Processes Photolithography Ion Implantation Etch Cleaning Planarization Test & Assembly Preetha Sreekumar Manipal Dubai .

Wafer Preparation • The base material for building an integrated circuit is a silicon crystal. is the principal ingredient of beach sand. the second most abundant element on the earth after oxygen. Silicon. Silicon boules are sliced into wafers and polished. the silicon must be refined and purified. The refined silicon is melted. A layer of epitaxial silicon (epi) is then deposited onto the polished silicon wafers. then crystallized to form boules. trace amounts of impurities are added. Silicon is a natural semiconductor. • To make wafers from sand. which means that it can be altered to be either an insulator or conductor. Preetha Sreekumar Manipal Dubai .

Polysilicon Refining • Chemical Reactions • Silicon Refining: SiO2 + 2 C  Si + 2 CO • Silicon Purification: Si + 3 HCl  HSiCl3 + H2 • Silicon Deposition: HSiCl3 + H2  Si + 3 HCl Preetha Sreekumar Manipal Dubai .

called polysilicon. also known as polysilicon. • Because polycrystalline silicon. • The polycrystalline silicon is refined by dissolving the tantalum wicks in hydrofluoric acid and fused to produce polysilicon ingots.Polysilicon Refining • To make a silicon wafer. randomly oriented crystals of pure silicon. has randomly oriented crystals. • Raw silicon is reacted with hydrochloric acid to form trichlorsilane or TCS. raw silicon is refined from quartz rock by reacting it with carbon to form small. it does not have the electrical characteristics necessary to fabricate semiconductor devices. TCS is mixed with hydrogen gas in a reaction furnace to form polycrystalline silicon which is allowed to grow on the surface of heated tantalum wicks. Polysilicon must first be transformed into single crystal silicon using a process called Crystal Pulling. Preetha Sreekumar Manipal Dubai .

Crystal Pulling • Process Conditions • Flow Rate: 20 to 50 liters/min • • • Time: 18 to 24 hours Temperature: >1.300 degrees C Pressure: 20 Torr Quartz Tube Rotating Chuck Seed Crystal Growing Crystal (boule) RF or Resistance Heating Coils Molten Silicon (Melt) Crucible Preetha Sreekumar M anipal Dubai .

The melt is cooled to a precise temperature. allow proper crystal orientation.Silicon Crystal Growing • The most commonly used technique for silicon crystal growing is the Czochralski process where a silicon seed is slowly drawn from a crucible of molten silicon to produce a cylindrical ingot 100 to 300 mm in diameter and up to a meter in length. • Most ingots produced today are 200mm (8") in diameter. The surface tension between the seed and the molten silicon causes a small amount of the liquid to rise with the seed and cool into a single crystalline ingot with the same orientation as the seed. and prevent defects. The ingot diameter is determined by controlling temperature and extraction speed. the process takes place in an inert gas atmosphere at a pressure of 20 Torr. phosphorous or antimony and melted at a temperature greater than 1300° C in a quartz crucible surrounded by an inert gas atmosphere of high-purity argon. Crushed. To minimize contamination of the silicon. but silicon suppliers are switching to ingots that are 300mm (12") in diameter. • Crystal pullers are installed on large concrete foundations (sometimes as large as an 8 foot cube) to control vibration. then a “seed” of single crystal silicon is placed into the melt and slowly rotated as it is “pulled” out. high-purity polycrystalline silicon is doped with elements like arsenic. Preetha Sreekumar Manipal Dubai . boron.

Wafer Slicing & Polishing silicon wafer p+ silicon substrate Preetha Sreekumar Manipal Dubai .

Wafer Slicing • After characterization.Wafer Slicing & Polishing Ingot Characterization • Single crystal silicon ingots are characterized by the orientation of their silicon crystals. wafer manufacturers slice the ingot into individual wafers with a precision thin-bladed saw designed to minimize waste (called “kerf”) but rigid enough to cut flatly. 300 mm wafers may be polished on both sides to improve photolithography resolution. However. Preetha Sreekumar Manipal Dubai . Before the ingot is cut into wafers. Wafer Polishing • Wafers are typically polished to a high degree of flatness on one side. the orientation of the crystal is marked by grinding a “flat” or “notch” along the silicon ingot.

Pressure: 100 Torr to Atmospheric Quartz Lamps Wafers Exhaust Sorenson 12 .Epitaxial Silicon Deposition silicon wafer p.100 degrees C.silicon epi layer p+ silicon substrate Susceptor Gas Input Lamp Module Chemical Reactions Silicon Deposition: HSiCl3 + H2  Si + 3 HCl Process Conditions Flow Rates: 5 to 50 liters/min Temperature: 900 to 1.

Si on Si Heteroepitaxy . efficient operation Epitaxial growth Preetha Sreekumar Manipal Dubai .Growth of a layer of the same material as the substrate eg.Growth of a layer of a different material than the substrate eg.Epitaxial Growth is the deposition of a layer on a substrate which matches the crystalline order of the substrate Homoepitaxy . GaAs on Si Epitaxial growth is useful for applications that place stringent demands on a deposited layer: • High purity • Low defect density • Abrupt interfaces • Controlled doping profiles • High repeatability and uniformity • Safe.

in the reactor and finding new chemistries to increase the deposition rate. Starting at 0. The epitaxial deposition uses a chlorinated silane reacting with hydrogen at temperatures of 900 to 1100° C. Preetha Sreekumar Manipal Dubai . The technology is moving from batch to single wafer processing in order to provide better process control and to achieve lower cost of ownership. Among the challenges in the technology is lowering the deposition temperature to below 900° C for defect reduction. This will roughly double the percentage of wafers processed with epitaxy. This will require reducing contaminants. such as moisture or oxygen. • In the future more wafers will have an epitaxy layer to improve silicon performance. • EPI layers are important for assuring device isolation and avoiding junction leakage in CMOS devices.18 m. DRAM manufacturers are likely to use epitaxy.Epitaxial Silicon Deposition • Silicon manufacturers use a process called epitaxial silicon growth to grow a layer of single crystal silicon from vapor onto a single crystal silicon substrate at high temperatures.

General Scheme Epitaxial Growth .

amorphous and poly silicon are thermally deposited from silane. Thermal Oxidation The thermal oxidation of silicon uses oxygen in high temperature furnaces at atmospheric pressures. often referred to as FEOL. polysilicon deposition and annealing operations are included in the front-end of the line processes. reduce particulate contamination. Preetha Sreekumar Manipal Dubai . leading to better consistency in etch and conductance. describes the processes used to fabricate device structures from the starting silicon material through the construction of complete transistor structures.Front end Processes Front-End Processes The Front-End of the line. Polysilicon Deposition Performed in Low Pressure (LP) CVD reactors. Furnace temperatures are in excess of 1. Thermal oxidation. The technology has migrated from horizontal furnaces to vertical furnaces to provide improved film uniformity.100° C and the process can take as log as 24 hours for thick oxides. silicon nitride deposition. Silicon Nitride Deposition Silicon nitride is deposited in LPCVD furnaces similar to those used for polysilicon deposition. and improve grain structure uniformity.

Front-End Processes • Thermal Oxidation • Silicon dioxide alloyed with phosphorus pentoxide ("Pglass") can be used to smooth out uneven surfaces • Silicon Nitride Deposition • Low Pressure Chemical Vapor Deposition (LPCVD) Silicon nitride is often used as an insulator and chemical barrier in manufacturing ICs • Polysilicon Deposition • Low Pressure Chemical Vapor Deposition (LPCVD) used for improved film uniformity • Annealing .

300 sccm Temperature: 600 degrees C.silicon epi layer p+ silicon substrate Chemical Reactions Thermal Oxidation: Si + O2  SiO2 Nitride Deposition: 3 SiH4 + 4 NH3  Si3N4 + 12 H2 Polysilicon Deposition: SiH4  Si + 2 H2 Process Conditions (Silicon Nitride LPCVD) Flow Rates: 10 . Pressure: 100 mTorr Oxidation Polysilicon Nitride Annealing Ar H2 N2 N2 H2 O SiH4 * Cl2 AsH3 H2 B 2 H6 HCl * PH3 O2 * Dichloroethene * 18 NH3 * H2SiCl2 * N2 SiH4 * SiCl4 Ar He H2 N2 3 Zone Temperature Control Gas Inlet * High proportion of the total product use Sorenson .Front-End Processes silicon dioxide (oxide) Vertical LPCVD Furnace Exhaust Via Vacuum Pumps and Scrubber Quartz Tube p.

• Photo-litho-graphy: latin: light-stone-writing Steps involved • Spin on the photoresist to the surface of the wafer Produces a thin uniform layer of photoresist on the wafer surface. lithography is a type of printing technology that is based on the chemical repellence of oil and water. • Expose to UV light • Wash with developer solution Preetha Sreekumar Manipal Dubai .Photolithography • Historically.

There are two types of photoresist: positive and negative   Preetha Sreekumar Manipal Dubai . It contains a light-sensitive substance whose properties allow image transfer onto a printed circuit board.Photoresist  Photoresist is an organic polymer which changes its chemical structure when exposed to ultraviolet light.

Preetha Sreekumar Manipal Dubai .Photoresist Coating Process Photoresist or resist is a photo-sensitive material applied to the wafer in a liquid state in small quantities. There are many specialty chemicals used in the photolithography process including materials that promote adhesion of the photoresist to the silicon surface. Photoresists must also have very low metal content. Most semiconductor processes today use a positive resist where exposed portions are removed leaving a “positive” image of the mask pattern on the surface of the wafer. inhibit corrosion. The wafer is spun at 3000 rpm which spreads the “puddle” into a uniform layer typically around 2 µm thick. Photoresists are specially formulated to tradeoff sensitivity to short-wavelength light and chemical erosion resistance during etch processes. materials that remove the bead of photoresist that forms at the edge of the wafer during spin application and materials that enhance the photosensitivity of the resist. or thin the photoresist.

and thus be more difficult to dissolve  Developer removes the unexposed resist This is like a photographic negative of the pattern   .Photolithography  Exposure to UV light makes it more soluble in the developer Exposed resist is washed away by developer so that the unexposed substrate remains Results in an exact copy of the original design   Exposure to UV light causes the resist to polymerize.

proximity. and projection Preetha Sreekumar Manipal Dubai .Mask Alignment and Exposure    Photomask is a square glass plate with a patterned emulsion of metal film on one side After alignment. the photoresist is exposed to UV light Three primary exposure methods: contact.

Exposure Methods Preetha Sreekumar Manipal Dubai .

A stepper exposes a photoresist coated wafer to single wavelength UV light passing through a reticle which contains the image of a single device layer. Semiconductor device manufacturers expose wafers using a tool called a stepper. The term “stepper” comes from the “step-and-repeat” action of moving the wafer on its x and y axes to align the reticle with each individual device position. UV light is used because modern semiconductor device features are so small that the actual wavelength of the exposing light is a limiting factor.Exposure Processes The image of the chip is projected through a mask and exposes a photo-active emulsion. A typical stepper will print a single process layer on about 12 wafers per hour. Steppers are extremely high-precision devices and can cost upwards of $5 million each and are very sensitive to vibration and temperature variation. Preetha Sreekumar Manipal Dubai .

• A process in which energetic. • Goal : to introduce a desired atomic species. ion implantation changes the electrical characteristics of precise areas within an existing layer on the wafer. (Today also up to several MeV) • Primarily used to add dopant ions into the surface of silicon wafers. into the required depth. charged atoms or molecules are directly introduced into a substrate. with lateral selectivity. with a specified quantity (dose). . • Acceleration energies range between 10-200 KeV. Instead.Ion Implantation • Ion Implantation is different from other semiconductor processes because it does not create a new layer on the wafer.

Advantages of ion implantation .

-Their energy range spans 100eV to several MeV ( a few nm’s to several microns in depth range). Relative Beam Scan .Overview -Initially. -The implantation is always followed by a thermal activation (600-1100oC). -This approach was soon found to lack the flexibility and control required by CMOS processing. Ion implantation quickly gained popularity for the introduction of dopant atoms. 0-200keV Source Gas Plasma Analyzing Magnet Wafer -Modern ion implanters were originally developed from particle accelerator technology.Ion Implantation . doping was performed in a manner similar to thin film deposition via CVD.

.Equipment .II Schematic diagram of an ion implantation system.Ion implantation.

Changes chemical and electronic behaviour .Playing billiards with atoms and electrons… • Ion impact leads to cascades of recoil atoms and electrons • Atomic cascades act as a nanoblender changing crystal structure and mixing atoms • Electron cascades cause chemical changes (radiolysis) • Foreign ion comes to rest under surface of material – ion implantation doping.

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Etching Preetha Sreekumar Manipal Dubai .

A strong Radio Frequency or RF electromagnetic field is applied to the wafer. Preetha Sreekumar Manipal Dubai .The semiconductor industry typically employs a technique called plasma etching to precisely transfer micro-images printed in photoresist into semiconductor process films. The RF field tears the molecules of etch gas apart into chemically reactive ions. Plasma etching selectively removes portions of semiconductor layers to leave microstructures on a device. This is done by placing wafers into a vacuum chamber which is filled with an etch gas. The process must precisely eliminate the material left exposed by the photoresist pattern and avoid undercutting the sides of the remaining circuit elements. The charged ions are accelerated toward the wafer surface by the electromagnetic field and form a microscopic chemical and physical “sandblasting” action which removes the exposed material.

Cluster Tool for Etching Cluster Tool Configuration Wafers Etch Chambers Transfer Chamber Loadlock RIE Chamber Gas Inlet Wafer RF Power Transfer Chamber Exhaust Preetha Sreekumar Manipal Dubai .

Cleaning Wafer Preparation Design • Critical Cleaning • Photoresist Strips • Pre-Deposition Cleans Thin Films Front-End Processes Photolithography Ion Implantation Etch Cleaning Planarization Test & Assembly .

are present). Experts in this field usually refer to this process as “wafer surface preparation” because wafers are not just cleaned but have their surfaces left in a precise chemical state that allows the next process step to be properly performed. which are sensitive to acid damage. Critical cleans are done for front-end processes and use strong acids (before metalization layers. everything starts with a clean. and pre-deposition cleans. Photoresist strips are also done with strong acids during the front-end processes but must be done with solvents after the metalization process steps. Preetha Sreekumar Manipal Dubai .Cleaning In semiconductor processes. The term “cleaning” is somewhat a misnomer. however these processes are shifting to dry cleaning technologies. photoresist strips. Predeposition cleans are also done with solvents. There are three major types of cleans used: Critical cleans.

Planarization • Oxide Planarization • Metal Planarization This process enables multiple layers of semiconductor metallization to be deposited. Preetha Sreekumar Manipal Dubai . allowing denser interconnection layers.

Metal Planarization Chemical Mechanical Polish (CMP) provides planarity for the tungsten plug used at the metallization level. the nature of the pad. and the mechanics of the tool are all critical to achieving global planarization over a 300 mm wafer. Advanced development is in the area of copper and aluminum planarization. The chemistry of the slurry. Preetha Sreekumar Manipal Dubai .Chemical Mechanical Planarization (CMP) Oxide Planarization Chemical Mechanical Polish (CMP) provides planarity for the oxide dielectric used at the metallization level.

Test and Assembly • Test & Assembly Test and assembly operation are performed out of the cleanroom wafer fab. Preetha Sreekumar Manipal Dubai . put into packages. chips are tested. In these operations. then retested.

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