Intel 8086 CPU: An Introduction

8086 Features
1. 2. 3. 4. • 16-bit Arithmetic Logic Unit 16-bit data bus 20-bit address bus - 220 = 1,048,576 = 1 meg 16 I/O lines so it can access 64K I/O ports The address refers to a byte in memory. In the 8086, bytes at even addresses come in on the low half of the data bus (bits 0-7) and bytes at odd addresses come in on the upper half of the data bus (bits 8-15). The 8086 can read a 16-bit word at an even address in one operation and at an odd address in two operations. The least significant byte of a word on an 8086 family microprocessor is at the lower address.

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8086 Architecture
• The 8086 has two parts, the Bus Interface Unit (BIU) and the Execution Unit (EU). • The BIU fetches instructions, reads and writes data, and computes the 20-bit address. • The EU decodes and executes the instructions using the 16-bit ALU. • The BIU contains the following registers:

• • • •

IP - the Instruction Pointer CS - the Code Segment Register DS - the Data Segment Register SS - the Stack Segment Register ES - the Extra Segment Register

The BIU fetches instructions using the CS and IP, written CS:IP, to construct the 20-bit address. Data is fetched using a segment register (usually the DS) and an effective address (EA) computed by the EU depending on the addressing mode.

8086 Programmer’s Model 16-bit Registers BIU registers (20 bit adder) ES CS SS DS IP AX BX CX DX AH BH CH DH AL BL CL DL Extra Segment Code Segment Stack Segment Data Segment Instruction Pointer Accumulator Base Register Count Register Data Register Stack Pointer Base Pointer Source Index Register Destination Index Register EU registers 16 bit arithmetic SP BP SI DI FLAGS .

The 8-bit registers are: » » » » AX --> AH. and DX registers can be considered as two 8bit registers.AL BX --> BH.the Count Register DX . as seen by their names.the Base Pointer SI .DL . BX.the Accumulator BX .8086 Architecture [2] • The EU contains the following 16-bit registers: » » » » » » » » AX .BL CX --> CH.the Source Index Register DI . the 8080 and 8085.the Base Register CX .the Data Register SP .the Destination Register • These are referred to as general-purpose registers. a High byte and a Low byte. CX. they often have a special-purpose use for some instructions. although. • The AX.CL DX --> DH.the Stack Pointer BP . This allows byte operations and compatibility with the previous generation of 8bit processors.

. 3.CF Carry Flag .for BCD arithmetic Bit 6 .Set if result has even parity Bit 4 . 12-15 are undefined.8086 Architecture [3] The EU also contains the Flag Register which is a collection of condition bits and control bits. 5.IF Interrupt Enable Flag Bit 10 .TF Single Step Trap Flag Bit 9 .DF String Instruction Direction Flag Bit 11 .SF Sign Flag = MSB of result Bit 8 . The condition bits are set or cleared by the execution of an instruction. • • • • • • • • • Bit 0 . The control bits are set by instructions to control some operation of the CPU.OF Overflow Flag • Bits 1.ZF Zero Flag .Set if result is zero Bit 7 .AF Auxiliary Flag .Set by carry out of MSB Bit 2 .PF Parity Flag .

8086 Block Diagram .

Segments Segment Starting address is segment register value shifted 4 place to the left. FFFFFH . CODE MEMORY Address 00000H STACK DATA EXTRA 64K Data Segment  CS:0 64K Code Segment Segment Registers Segments are < or = 64K. can overlap. start at an address that ends in 0H.

. Note that the Code segment is < 64K since FFFFFH is the highest address.8086 Memory Terminology Segment Registers DS: 0100H Memory Segments 00000H DATA 01000H 10FFFH B2000H C1FFFH ES: CF00H EXTRA CS: FF00H CODE FF000H FFFFFH CF000H DEFFFH SS: B200H STACK Segments are < or = 64K and can overlap.

Defines the segment name and specifies that the code that follows is in that segment. Give source module a name.Assembler Directives • • • • ASSUME SEGMENT ENDS ORG Tells the assembler what segments to use. • • • • • • END NAME EQU LABEL $ ALIGN End of source code. Current location count aligns the next segment at even address . End of segment Originate or Origin: sets the location counter. Equate or equivalence Assign current location count to a symbol.

most of the time we use 4CH function of DOS interrupt 21H. PROC. default 1024 bytes DATA  DB – Define Byte  DW – Define Word  DD – Define Double word  DQ – Define Quad word  DT – Define Ten bytes  DUP – used to declare an array of bytes CODE – indicates the beginning of code segment Ex: code [name]. • • • • .• STACK stack 100d (or) stack 64h . ENDM directives support modularity. EXIT – marks the end of CS. ENDP & MACRO.


A17/S4. A18/S5.A19/S6. A16/S3 Address/Status S4 S3 Function Extra segment access Stack segment access Code segment access Data segment access 0 0 1 1 0 1 0 1 .

S2 0 0 0 S1 0 0 1 S0 0 1 0 Characteristics Interrupt acknowledge Read I/O port Write I/O port 0 1 1 1 1 1 0 0 1 1 1 0 1 0 1 Halt Code access Read memory Write memory Passive State .

QS1 0 QS0 0 Characteristics No operation 0 1 1 1 0 1 First byte of opcode from queue Empty the queue Subsequent byte from queue .

D15 8286 DT/R DEN T OE 16 .8086 System Minimum mode PCLK +5V RES Clock generator AEN2 AEN1 F/C CLK READY RESET M/IO INTA RD WR MN/MX +5V Control Bus Wait-State Generator ALE STB OE A0 .A19 Address Bus 8086 CPU AD0-AD15 A16-A19 BHE 8282 Latch BHE D0 .

8284 Pin Diagram CSYNC PCLK AEN 1 1 2 3 4 5 6 7 8284 18 17 16 15 14 13 12 VCC X2 X1 TANK EFI RDY1 READY RDY2 AEN 2 F/ C OSC CLK GND 8 9 11 10 RES RESET .


Read Cycle timing Diagram for Minimum Mode .





8086 System Maximum Mode +5V CLK Clock generator MN/MX S0 S1 S2 Gnd S0 S1 S2 CLK MRDC MWTC AMWC IORC IOWC AIOWC INTA RESET DEN DT/R Wait-State Generator ALE 8086 CPU STB OE 8288 Bus Controller A0 .A19 Address Bus BHE RES READY AD0-AD15 A16-A19 8282 Latch T OE 8286 Transceiver DATA .

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