Presented By: Muhammad Israr Azem Muhammad Tahir Maryam Firdous Co_ordinators: Dr.Fadah Azim .

First Evolution Task .

FPGA Altera Kit .

Hardware is provided By DE2-115 board                     The following : USB Blaster (on board) for programming. both JTAG and Active Serial (AS) programming modes are supported 2MB SRAM Two 64MB SDRAM 8MB Flash memory SD Card socket 4 Push-buttons 18 Slide switches 18 Red user LEDs 9 Green user LEDs 50MHz oscillator for clock sources 24-bit CD-quality audio CODEC with line-in. line-out. VGA DAC (8-bit high-speed triple DACs) with VGA-out connector TV Decoder (NTSC/PAL/SECAM) and TV-in connector 2 Gigabit Ethernet PHY with RJ45 connectors USB Host/Slave Controller with USB type A and type B connectors RS-232 transceiver and 9-pin connector PS/2 mouse/keyboard connector IR Receiver 2 SMA connectors for external clock input/output .

The ADV7180 is an integrated video decoder that automatically detects and converts a standard analog base band television signals (NTSC. including DVD players.656 interface standard. tape-based sources. and security/surveillance cameras. The ADV7180 is compatible with a broad range of video devices.TV Decoder The DE2-115 board is equipped with an Analog Device ADV7180 TV decoder chip. broadcast sources. . and SECAM) into  4:2:2 component video data compatible with the 8-bit ITU-R BT. PAL.

Connections between FPGA and TV Decoder .

Implementing a TV Encoder  Although the DE2-115 board does not include a TV encoder chip. the ADV7123 (10-bit highspeed triple ADCs) can be used to implement a professional-quality TV encoder with the digital processing part implemented in the Cyclone IV E FPGA .

A TV Encoder that uses the Cyclone IV E FPGA and the ADV7123 .

TD_Data ITU_R656Dec oder YUV4:2:2 SDRAM frame buffer control MUX VGA DAC ADV7123 TV decoder ADV7180 TD_HS TD_VS RGB Locked Detector V Y U 4 2 2 VGA controller VGA_HS VGA_VS i t I2c_SCLK YUV4:2:2 to YUV4:4:4 I2c Ycbcr to RGB I2c_SDAT .

Block diagram of the TV box demonstration .

Introduction  Tv Decoder ADV7180  ITU_R 656 Decoder  I2c_V Config  YUV4:2:2_ to_ YUV4:4:4  Ycbcr _to _RGB  VGA Controller  LCD Display  Refrences  .


Convert analog signal into worldwide standers(NTS.PAL etc)  Convert worldwide standers into 4:2:2 video components  Output signals synchronous  Programmed by 2wires    serial Bidirectioal port .

.It describes how to embed video timing information in the 4:2:2 bit parallel sampling scheme of the Ycrcb color space definition.

Used for communication b/w FPGA core and tv decoder ADV7180  I2c clock  I2c SData  .



used to control the color .     Horizontal sync: digital signal.7 v). used for synchronisation of the video Red (R): analog signal (0-0. used to control the color Blue (B): analog signal (0-0.7 v).7 v). used for synchronisation of the video Vertical sync: digital signal. used to control the color Green (G): analog signal (0-0.

Video display on LCD by VGA DAC ADV7123. .

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