CADENCE CONFIDENTIAL 1 CADENCE DESIGN SYSTEMS, INC.

SESSION 1: MOS THEORY
•Review of PN Junction
•MOS Structure
•Accumulation, cutoff, Inversion
•MOS transistor
•Threshold Voltage


CADENCE CONFIDENTIAL 2
Review of PN Junction
• Drift current: electrons and holes move in an electric field
(+)
holes
E field
electrons
• Diffusion current: electrons and holes move from high
concentration to low concentration
Si Si Si Si
e-
conc.
(-)
CADENCE CONFIDENTIAL 3
Review (cont)
• PN junction built-in potential
E
C
E
Fn
E
Fp
E
V
qV
0
• Fermi levels line up
• Electrons traveling from
right to left have to cross
potential barrier of qV
0
E field
N P
- V
0
+
|
|
.
|

\
|
=
2
ln
i
D A
n
N N
q
kT
q
E E
V
in ip
÷
=
0
CADENCE CONFIDENTIAL 4
• When biased, electric field in depletion region changes
– Forward bias: reduces electric field
– Reverse bias: increases electric field
• Electric field is a result of uncovered charges. Therefore
depletion width must change
– Forward bias: less charges needed. Depletion width reduces
– Reverse bias: more charges needed. Depletion region increases.
Bias Effect on Depletion Width
CADENCE CONFIDENTIAL 5
0
) ( 2
V
N N
N N
q
W
d a
d a
d
+
=
c
Width of depletion region:
( ) V V
N N
N N
q
W
d a
d a
d
÷
+
=
0
) ( 2c
Width of depletion region with bias V:
Bias Effect on Depletion Width
CADENCE CONFIDENTIAL 6
• Forward bias: barrier lowered, diffusion current dominates
• Reverse bias: barrier raised, only current is small drift
current of minority carriers
• Diode only lets current flow in one direction
• Diode equation:
) 1 (
/
0
÷ =
kT qV
e I I
I
0
= generation current
Diode Equation
CADENCE CONFIDENTIAL 7
• Separated charges result in depletion region capacitance
• Similar to parallel-plate capacitor
E field
N P
a d
a d
j
N N
N N
V V
q A
C
+ ÷
=
0
2
2
c
) ( 2
0
V V
N N
N N
q A Q
a d
a d
j
÷
+
= c
Charge in depletion region: Capacitance:
Capacitance of P/N Junction
CADENCE CONFIDENTIAL 8
MOS structure
• MOS: Metal-oxide-semiconductor
– Gate: metal (or polysilicon)
– Oxide: silicon dioxide, grown on substrate
• MOS capacitor: two-terminal MOS structure
Si substrate
Oxide (SiO
2
)
Metal gate (Al)
Body or substrate terminal
Gate terminal
CADENCE CONFIDENTIAL 9
MOS Energy Band Diagram
• Work function (qu
M
, qu
S
): energy required to take
electron from Fermi level to free space
• Work function difference between Al and Si
• At equilibrium, Fermi levels must line up

qu
M

E
C

E
i

E
Fp

E
V

qu
S

E
0

E
Fm

oxide
bandgap
8ev
Oxide Metal p-type Si
q_
oxid
e

q_
S

CADENCE CONFIDENTIAL 10
MOS Energy Band Diagram
E
Fp
E
V
E
C
M O S (p-type)
• Bands must bend for Fermi levels to line up
• Part of voltage drop occurs across oxide, rest occurs
next to O-S interface
• Amount of bending is equal to work function
difference: qu
M
- qu
S

E
i
E
Fm
q|
F q|
S
|
F
= Fermi potential
(difference between E
F

and E
i
in bulk)

|
S
= surface potential
CADENCE CONFIDENTIAL 11
Flat-Band Voltage
• Flat-band voltage
– Built-in potential of MOS system
– Work function difference: V
FB
= u
m
- u
S

– Apply this voltage to ―flatten‖ energy bands
CADENCE CONFIDENTIAL 12
MOS capacitor operation
• Assume p-type substrate
• Three regions of operation
– Accumulation (V
G
< 0)
– Depletion (V
G
> 0 but small)
– Inversion (V
G
>> 0)
P-type Si substrate
V
B
= 0
V
G

CADENCE CONFIDENTIAL 13
Accumulation
• Negative voltage on gate: attracts holes in substrate
towards oxide
• Holes ―accumulate‖ on Si surface (surface is more
strongly p-type)
• Electrons pushed deeper into substrate
P-type Si substrate
V
G
< 0
V
B
= 0
E
Fp
E
V
E
C
E
i
E
Fm
qV
G
CADENCE CONFIDENTIAL 14
Depletion
• Positive voltage on gate: repels holes in substrate
– Holes leave negatively charged acceptor ions
• Depletion region forms: devoid of carriers
– Electric field directed from gate to substrate
• Bands bend downwards near surface
– Surface becomes less strongly p-type (E
F
close to E
i
)
P-type Si substrate
V
G
> 0
V
B
= 0
Depletion region
E
ox
E
Fp
E
V
E
C
E
i
E
Fm
qV
G
CADENCE CONFIDENTIAL 15
Depletion region depth
• Calculate thickness x
d
of depletion region
– Find charge dQ in small slice of depletion area




– Find change in surface potential to displace dQ by distance x
d

(Poisson equation):
x
d

dx
dQ
dx qN dQ
A
÷ =
Si
A
Si
dx
xqN d
dQ
x d
c
|
c
| ÷ = ÷ =
CADENCE CONFIDENTIAL 16
Depletion region depth (cont.)
– Integrate perpendicular to surface







– Result:
Si
d A
F S
x
Si
A
S
x qN
dx
x qN
d
d S
F
c
| |
c
|
|
|
2
2
2
0
= ÷
=
} }
A
F S Si
d
qN
x
| | c ÷
=
2
CADENCE CONFIDENTIAL 17
Depletion region charge
• Depletion region charge density
– Due only to fixed acceptor ions
– Charge per unit area
F S Si A
d A
qN Q
x qN Q
| | c ÷ ÷ =
÷ =
2
CADENCE CONFIDENTIAL 18
Inversion
• Increase voltage on gate, bands bend more
• Additional minority carriers (electrons) attracted from
substrate to surface
– Forms “inversion layer” of electrons
• Surface becomes n-type
P-type Si substrate
V
G
>> 0
V
B
= 0
E
Fp
E
V
E
C
E
i
E
Fm
qV
G
electrons
E
ox
CADENCE CONFIDENTIAL 19
• Definition of inversion
– Point at which density of electrons on surface equals
density of holes in bulk
– Surface potential is same as |
F
, but different sign
E
V
E
Fp
E
i
E
C
q|
F
q|
S
= -q|
F
Remember:

q|
F
= E
F
- E
i
Inversion
CADENCE CONFIDENTIAL 20
MOS transistor
• Add ―source‖ and ―drain‖ terminals to MOS capacitor
• Transistor types
– NMOS: p-type substrate, n
+
source/drain
– PMOS: n-type substrate, p
+
source/drain
source
drain
P-substrate
N
+
N
+
NMOS
source
drain
N-substrate
P
+
P
+
PMOS
CADENCE CONFIDENTIAL 21
MOS Transistor
• Important transistor physical characteristics
– Channel length L
– Channel width W
– Thickness of oxide t
ox
L
W
t
ox
CADENCE CONFIDENTIAL 22
MOS transistor operation
• Simple case: V
D
= V
S
= V
B
= 0
– Operates as MOS capacitor
• When V
GS
<V
T0
, depletion region forms
– No carriers in channel to connect S and D
source drain
P-substrate
V
B
= 0
V
g
< V
T0

V
d
=0 V
s
=0
depletion
region
CADENCE CONFIDENTIAL 23
MOS transistor operation
• When V
GS
> V
T0
, inversion layer forms
• Source and drain connected by conducting n-type layer
(for NMOS)
source drain
P-substrate
V
B
= 0
V
g
> V
T0

V
d
=0 V
s
=0
depletion
region
inversion
layer
CADENCE CONFIDENTIAL 24
MOS transistors Types and Symbols

D
S
G
D
S
G
G
S
D D
S
G
NMOS
Enhancement NMOS
PMOS
Depletion
Enhancement
B
NMOS with
Bulk Contact
CADENCE CONFIDENTIAL 25
Threshold voltage
• Threshold voltage (V
T0
): voltage between gate and source
required for inversion
– Transistor is ―off‖ when V
GS
< V
T0
• Components:
– Work function difference between gate and channel
(Flat-band voltage)
– Gate voltage to change surface potential
– Gate voltage to offset depletion charge
– Gate voltage to offset fixed charges in gate oxide and
silicon-dioxide interface
CADENCE CONFIDENTIAL 26
Threshold voltage (1)
• Work function difference u
GC
between gate and channel
– Represents built-in potential of MOS system
– For metal gate: u
GC
= |
F
(substrate) - |
M
(gate)
– For poly gate: u
GC
= |
F
(substrate) - |
F
(gate)
 + u =
GC T
V
0
CADENCE CONFIDENTIAL 27
Threshold voltage (2)
• First component accounts for built-in voltage drop
• Now apply additional gate voltage to achieve inversion:
change surface potential by -2|
F
 + ÷ u =
F GC T
V | 2
0
CADENCE CONFIDENTIAL 28
Threshold voltage (3)
• Offset depletion region charge, due to fixed acceptor ions
• Calculate charge at inversion (|
S
=-|
F
)
– From before:

– So:

– For non-zero substrate bias (V
SB
= 0):



Due to larger depletion region

F S Si A
qN Q | | c ÷ ÷ = 2
F Si A B
qN Q | c 2 2
0
÷ ÷ =
SB F Si A B
V qN Q + ÷ ÷ = | c 2 2
CADENCE CONFIDENTIAL 29
Threshold voltage (3, cont.)
• To offset this charge, need voltage -Q
B
/C
ox

• Cox = gate capacitance per unit area
– C
ox
=c
ox
/t
ox

– t
ox
= thickness of gate oxide


 + ÷ ÷ u =
ox
B
F GC T
C
Q
V | 2
0
CADENCE CONFIDENTIAL 30
Threshold voltage (4)
• Correct for non-ideal fixed charges
– Fixed positive charge density Q
ox
at boundary
between gate oxide and substrate
– Due to impurities, lattice imperfections at interface
– Correct with gate voltage = -Q
ox
/C
ox

• Final threshold voltage formula (for NMOS):
ox
ox
ox
B
F GC T
C
Q
C
Q
V ÷ ÷ ÷ u =
0
0
2|
CADENCE CONFIDENTIAL 31
Threshold voltage
• General form (non-zero substrate bias):


• Can also write as:

• Replacing second term:
ox
ox
ox
B
F GC T
C
Q
C
Q
V ÷ ÷ ÷ u = | 2
ox
B B
T T
C
Q Q
V V
0
0
÷
÷ =
( )
ox
Si A
F SB F T T
C
qN
V V V
c
¸
| | ¸
2
2 2
0
=
÷ + ÷ + =
Substrate-bias
coefficient
CADENCE CONFIDENTIAL 32
Threshold voltage, summary
• If V
SB
= 0 (no substrate bias):


• If V
SB
= 0 (non-zero substrate bias)


• Body effect (substrate-bias) coefficient:


• Threshold voltage increases as V
SB
increases!
ox
ox
ox
B
F GC T
C
Q
C
Q
V ÷ ÷ ÷ u =
0
0
2|
( )
F SB F T T
V V V | | ¸ 2 2
0
÷ + ÷ + =
ox
Si A
C
qN c
¸
2
=
CADENCE CONFIDENTIAL 33
NMOS PMOS
Substrate Fermi potential |
F
< 0 |
F
> 0
Depletion charge density Q
B
< 0 Q
B
> 0
Substrate bias coefficient ¸ > 0 ¸ < 0
Substrate bias voltage V
SB
> 0 V
SB
< 0
Threshold Voltage (NMOS vs. PMOS)
CADENCE CONFIDENTIAL 34
Body effect
• Body effect: Voltage V
SB
affects threshold voltage of
transistor
– Body normally connected to ground for NMOS, V
DD
for PMOS
– Raising source voltage increases V
T
of transistor
– Implications on circuit design

V
T0
A
B
V
x
If V
x
> 0,
V
SB
(A) > 0,
V
T
(A) > V
TO
CADENCE CONFIDENTIAL 35
Threshold voltage adjustment
• Threshold voltage can be changed by doping the channel
region with donor or acceptor ions
• For NMOS:
– V
T
increased by adding acceptor ions (p-type)
– V
T
decreased by adding donor ions (n-type)
– Opposite for PMOS
• Approximate change in V
T0
:
– Density of implanted ions = N
I
[cm
-2
]
– Assume all implanted impurities are ionized

ox
I
T
C
qN
V = A
0
CADENCE CONFIDENTIAL 36

• 5 Minutes Break
CADENCE CONFIDENTIAL 37 CADENCE DESIGN SYSTEMS, INC.





MOS EQUATIONS – Lecture 1
•Cut-off, Linear, Saturation
•Drain Current equations
•MOS Characteristics
•Oxide capacitance
•Junction Capacitance


CADENCE CONFIDENTIAL 38
MOS transistor characteristics
• Three regions of operation: overview
– Cutoff: V
GS
< V
T

No inversion layer formed, drain and source are
isolated by depleted channel. I
DS
~ 0
– Linear: V
GS
> V
T
, V
DS
< V
GS
-V
T

Inversion layer connects drain and source.
Current is almost linear with V
DS
(like a resistor)
– Saturation: V
GS
>V
T
, V
DS
>V
GS
-V
T

Channel is ―pinched-off‖. Current saturates.

CADENCE CONFIDENTIAL 39
Cutoff Region
• V
GS
< V
TN

• V
GS
> V
TP
• Depletion region – no inversion
• Current between drain and source is 0
– Actually there is leakage current
source drain
substrate
V
B

V
G

V
D
V
S

depletion
region
CADENCE CONFIDENTIAL 40
Linear mode
• When V
GS
>V
T
, an inversion layer forms between drain
and source
• Current I
DS
flows from drain to source (electrons travel
from source to drain)
• Depth of channel depends on V between gate and
channel
– Drain end narrower due to larger drain voltage
– Drain end depth reduces as V
DS
is increased
V
B
= 0
V
g
> V
T0

V
d
< V
GS
-V
T0

depletion
region (larger at
drain end)
Channel
(inversion layer)
source drain
P-substrate
V
B
= 0
V
g
> V
T0

V
d
< V
GS
-V
T0
V
s
=0
CADENCE CONFIDENTIAL 41
Linear I/V Equation
• Gradual Channel Approximation:
– Assume dominant electric field in y-direction
– Current is constant along channel
CADENCE CONFIDENTIAL 42
Linear I/V Equation
• Assume that V
GS
> V
T,
then the charge induced per unit
area in channel

( ) ) ( ) ( y V V V C y Q
T GS ox I
÷ ÷ =
• The resistance dR of length dy of channel

) ( y Q W
dy
dR
I n
µ
=
• Where W is width of channel and μ
n
mobility of
electron.

CADENCE CONFIDENTIAL 43
Linear I/V Equation
• For current I
D
, drop across this resistance will be

• For total length L on integration we have

dV V V V C W dy I
T GS ox
V
n
L
D
DS
) (
0 0
÷ ÷ =
} }
µ
dy
y Q W
I
dR I dV
I n
D
D
) ( µ
= =
CADENCE CONFIDENTIAL 44
Linear I/V Equation
• Final equation for I
D

( ) | |
2
2
1
DS DS T GS ox n D
V V V V
L
W
C I ÷ ÷ = µ
L
W
C k
ox n n n
µ | = =
Device transconductance:
ox n n
C k µ =
'
Process transconductance:
( ) | |
2
2
1
'
DS DS T GS n D
V V V V
L
W
k I ÷ ÷ =
CADENCE CONFIDENTIAL 45
Saturation mode
• When V
DS
= V
GS
- V
T
:
– No longer voltage drop of V
T
from gate to substrate at drain
– Channel is ―pinched off‖
• If V
DS
is further increased, no increase in current I
DS

– As V
DS
increased, pinch-off point moves closer to source
– High electric field in depleted region accelerates electrons towards
drain
source drain
V
B
= 0
V
g
> V
T0

V
d
> V
GS
-V
T0

V
s
=0
depletion
region
pinch-off point
CADENCE CONFIDENTIAL 46
Saturation I/V Equation
• As drain voltage increases, channel remains pinched off
– Channel voltage remains constant
– Current saturates
• To get saturation current, use linear equation with V
DS
=
V
GS
- V
T
( )
2
2
1
TN GS ox n D
V V
L
W
C I ÷ = µ
CADENCE CONFIDENTIAL 47
MOS I/V Characteristics
• I/V curve for ideal MOS device
• V
GS3
> V
GS2
>V
GS1
Drain voltage V
DS

D
r
a
i
n

c
u
r
r
e
n
t

I
D
S

V
GS1

V
GS2

V
GS3

Linear
Saturation
CADENCE CONFIDENTIAL 48
MOS I/V Characteristics
0.0 1.0 2.0 3.0 4.0 5.0
V
DS
(V)
1
2
I
D

(
m
A
)
0.0 1.0 2.0 3.0
V
GS
(V)
0.010
0.020
÷
\
I
D
V
T
Subthreshold
Current
Triode Saturation
V
GS
= 5V
V
GS
= 3V
V
GS
= 4V
V
GS
= 2V
V
GS
= 1V
(a) I
D
as a function of V
DS
(b) \I
D
as a function of V
GS
(for V
DS
= 5V)
.
S
q
u
a
r
e

D
e
p
e
n
d
e
n
c
e
V
DS
= V
GS
-V
T
NMOS Enhancement Transistor: W = 100 µm, L = 20 µm
CADENCE CONFIDENTIAL 49
MOSFET Capacitances

• Oxide Capacitance
– Gate to Source overlap
– Gate to Drain overlap
– Gate to Channel
• Junction Capacitance
– Source to Bulk junction
– Drain to Bulk junction
CADENCE CONFIDENTIAL 50
• Overlap capacitances
– gate electrode overlaps source and drain regions
– L
D
is overlap length on each side of channel
– L
eff
= L
drawn
– 2L
D
– Total overlap capacitance:
source drain
L
D
L
drawn
D ox GDO GSO O
WL C C C C 2 = + =
Oxide capacitances
CADENCE CONFIDENTIAL 51
• Channel capacitances
– Gate-to-source: C
gs
– Gate-to-drain: C
gd
– Gate-to-bulk: C
gb


• Cutoff:
– No channel connecting source and drain
– C
gs
= C
gd
= 0
– C
gb
= C
ox
WL
eff

– Total channel capacitance C
C
= C
ox
WL
eff
source drain
C
gb
C
gd
C
gs
Oxide capacitances

CADENCE CONFIDENTIAL 52
• Linear mode
– Channel spans from source to drain
– Capacitance split equally between S and D
eff ox GS
WL C C
2
1
=
eff ox GD
WL C C
2
1
=
– Total channel capacitance C
C
= C
ox
WL
eff


• Saturation mode
– Channel is pinched off:
eff ox GS
WL C C
3
2
= 0 =
GD
C
– Total channel capacitance C
C
= 2/3 C
ox
WL
eff


0 =
GB
C
0 =
GB
C
Oxide capacitances
CADENCE CONFIDENTIAL 53
C
g,total

(no overlap)

Oxide capacitances
CADENCE CONFIDENTIAL 54
Junction Capacitance
Reverse-biased P-N junctions!
Capacitance depends on reverse-bias voltage.
CADENCE CONFIDENTIAL 55
Junction Capacitance
a d
a d
j
N N
N N
V V
q A
C
+ ÷
=
0
2
2
c
For a P-N junction:
a d
a d Si
j
N N
N N
V
q
C
+
=
0
0
2
c
If V=0, Cap/area =
m
j
j
V
V
AC
C
|
|
.
|

\
|
÷
=
0
0
1
General form:
m = grading coefficient (0.5 for abrupt junctions)
(0.3 for graded junctions)
CADENCE CONFIDENTIAL 56
Junction Capacitance
• Junction with substrate
– Bottom area = W * L
S
(length of drain/source)
– Sidewall facing channel: area = W * X
j
– Total cap = C
j

• Junction with sidewalls
– ―Channel-stop implant‖
– Perimeter = 2L
S
+ W
– Area = P * X
j
– Total cap = C
jsw

• Total junction cap C = C
j
+ C
jsw
CADENCE CONFIDENTIAL 57 CADENCE DESIGN SYSTEMS, INC.





SESSION 2: STATIC INVERTERS –
Lecture 1
•Characteristics of Inverters
•Resistive Load Inverters
•VTC, Delay, Power Dissipation
•Pseudo-NMOS Inverters
•Depletion Load Inverters


CADENCE CONFIDENTIAL 58
MOS voltage levels
Case 1: NMOS discharges capacitor
• Initially: Vout = V
DD
(capacitor fully charged)
• V
GS
of NMOS = V
DD
• What is final Vout?
V
DD
G
D
S
C
load

Vout
time
V
out

V
DD

• NMOS remains on since V
GS
> V
T

• Final output voltage V
out
= 0V
CADENCE CONFIDENTIAL 59
Case 2: NMOS charges capacitor
• Initially: Vout = 0
• Initial V
GS
of NMOS = V
DD
• What is final Vout?
V
DD
G
D
S
C
load

Vout
time
V
out

V
DD

• NMOS remains on until V
GS
= V
T

• Final output voltage V
out
= V
DD
- V
T

V
DD
V
DD
-V
T

MOS voltage levels
CADENCE CONFIDENTIAL 60
MOS voltage levels
Repeat for PMOS:
• Case 1: PMOS discharging capacitor
Gnd
G
S
D
C
load

Vout
• PMOS on until V
GS
= V
T

• Vout = |V
T
|
• Case 2: PMOS charging capacitor
Gnd
G
S
D
C
load

Vout
• PMOS always on (V
GS
= -V
DD
)
• Vout = V
DD

V
DD
CADENCE CONFIDENTIAL 61
MOS voltage levels
• NMOS summary
– Transfers logic ‗0‘ completely (good for discharging a node)
– Does not transfer logic ‗1‘ completely (bad for charging a node)
• PMOS summary
– Transfers logic ‗1‘ completely
– Does not transfer logic ‗0‘ completely
• Result:
– NMOS used for pulldown, PMOS for pullup

CADENCE CONFIDENTIAL 62
• Inverter is simplest digital logic gate



• Many different circuit styles possible
– Resistive-load
– Pseudo-NMOS
– CMOS
• Important characteristics
– Speed (delay through the gate)
– Power consumption
– Robustness (tolerance to noise)
– Area and process cost
Inverter Operation
„0‟ „1‟
„1‟ „0‟
In Out
0 1
1 0
CADENCE CONFIDENTIAL 63
Inverter
Vin Vout
V
DD
V
DD
Vin
Vout
ideal
actual
Inverter model: VTC
Ideal digital inverter:
– When Vin=0, Vout=V
DD
– When Vin=V
DD
, Vout=0
– Sharp transition region
Voltage transfer curve (VTC):
plot of output voltage Vout vs. input voltage Vin
CADENCE CONFIDENTIAL 64
Actual inverter: V
OH
and V
OL

• V
OH
and V
OL
represent the ―high‖ and
―low‖ output voltages of the inverter
• V
OH
= output voltage when Vin = ‗0‘
• V
OL
= output voltage when Vin = ‗1‘
• Ideally,V
OH
= V
DD,
V
OL
= 0
• Difference (V
OH
-V
OL
) is the voltage
swing of the gate
– Full-swing logic swings from ground
to V
DD

V
DD
Vin
Vout
V
OH

V
OL

V
DD

CADENCE CONFIDENTIAL 65
Inverter switching threshold:
– Point where voltage transfer
curve intersects line Vout=Vin
– Represents the point at which
the inverter switches state
– Normally, V
TH
~ V
DD
/2
V
DD
Vin
Vout
V
OH

V
OL

Vout=Vin
V
TH

Inverter threshold
CADENCE CONFIDENTIAL 66
Noise Margins
• V
IL
and V
IH
measure effect of
input voltage on inverter
output
• V
IL
= largest input voltage
recognized as logic ‗0‘
• V
IH
= smallest input voltage
recognized as logic ‗1‘
• Defined as point on VTC where
slope = -1
V
DD
Vin
Vout
V
OH

V
OL

V
IL
V
IH

Slope = -1
CADENCE CONFIDENTIAL 67
Noise margin (cont)
V
OH

V
OL

V
IH

V
IL

“1”
“0”
NM
H

NM
L

• Noise margin is a measure of the
robustness of an inverter
– N
ML
= V
IL
- V
OL

– N
MH
= V
OH
- V
IH
• Models a chain of inverters. Example:
– First inverter output is V
OH

– Second inverter recognizes input > V
IH

as logic ‗1‘
– Difference V
OH
-V
IH
is ―safety zone‖ for
noise
Ideally, noise margin should be
as large as possible
interconnect
CADENCE CONFIDENTIAL 68
Noise margin (cont)
• Why are V
IL
, V
IH
defined as unity-gain point on VTC?
– Assume there is noise on input voltage V
in
( )
noise in out
V V f V + =
( )
noise
in
out
in out
V
dV
dV
V f V + =
– First-order approximation:
– If gain (dV
out
/dV
in
) > 1, noise will be amplified.
– If gain < 1, noise is filtered. Therefore V
IL
, V
IH

ensure that gain < 1
CADENCE CONFIDENTIAL 69
Inverter time response
• Propagation delay measured from 50% point of Vin to 50% point
of Vout
• t
phl
= t
1
- t
0
, t
plh
= t
3
- t
2
, t
p
= ½(t
phl
+t
plh
)
V
DD
Vss
V
DD
/2
V
DD
Vss
V
DD
/2
Vin
Vout
t
0
t
1
t
2
t
3

CADENCE CONFIDENTIAL 70
Rise and fall time
• Fall time: measured from 90% point to 10% point t
F
= t
1
- t
0

• Rise time: measured from 10% point to 90% point t
R
= t
3
- t
2

• Alternately, can define 20%-80% rise/fall time
V90%
V10%
t
0
t
1

t
2
t
3

t
F
t
R

CADENCE CONFIDENTIAL 71
Ring oscillator
• Ring oscillator circuit: standard method of comparing delay from
one process to another
• Odd-number n of inverters connected in chain: oscillates with
period T (usually n >> 5)
V
1
V
3
V
2
V
OH
T

V
50%
t
PHL2
t
PLH3
t
PHL1
t
PLH2
t
PHL3
t
PLH1
C
load
C
load

V
1
V
2
V
3
nf
t
nt T
f nt T
t t t t t t T
p
p
p
phl plh phl plh phl plh
2
1
,
2
1 1
, 2
3 3 2 2 1 1
= = = =
+ + + + + + = 
CADENCE CONFIDENTIAL 72
Resistive-load inverter
• Requires only NMOS transistor and
resistor
• When Vin = 0:
– NMOS is OFF (V
GS
= 0)
– No current through NMOS or resistor
– Vout ~ V
DD
• When Vin = V
DD
:
– NMOS is ON (V
GS
= V
DD
)
– NMOS on resistance << R
– Vout ~ 0

Vin
Vout
V
DD
Gnd
R
G
D
S
Remember: if body terminal
not shown, it is connected to
gnd for NMOS, V
DD
for
PMOS
CADENCE CONFIDENTIAL 73
Resistive-load inverter: V
OH

• Vin = 0: NMOS transistor off, no current
flows in circuit
• No voltage drop across R
• V
OH
= V
DD
Vin=0
Vout
V
DD
Gnd
R
CADENCE CONFIDENTIAL 74
• Vin = V
DD
: NMOS transistor on (linear
mode)

Vin=V
DD
Vout
V
DD
Gnd
R
I
load

I
D

| |
OL
L
W
OL OL T DD L
W OL DD
OL DD
D
OL DS
DD IN GS
DS DS T GS L
W
D
V
Rk
V V V V k
R
V V
R
V V
I
V V
V V V
V V V V k I
=
÷ ÷ =
÷
÷
=
=
= =
÷ ÷ =
'
2
2
1
'
2
2
1
'
1
] ) [(
) (
) (
) (
• Solve quadratic equation for V
OL,
Approx value is


(because I
D
= I
load
)
Resistive-load inverter: V
OL
CADENCE CONFIDENTIAL 75
• Note that the value of V
OL
depends on the size of the
NMOS device and on R
– Increase W to reduce V
OL

– Increase R to reduce V
OL
• Logic with this property is called ―ratioed logic‖
– Requires careful sizing for correct logic levels
• Ratioless logic: output levels do not depend on
transistor sizes
Resistive-load inverter: V
OL
cont
CADENCE CONFIDENTIAL 76
Resistive-load inverter: V
IL
• V
IL
= low unity gain point of VTC
– When V
in
= V
IL
, NMOS in saturation:
( )
( )
2
2
1
2
2
1
T in n DD out
T in n
out DD
V V Rk V V
V V k
R
V V
÷ ÷ =
÷ =
÷
– Take derivative of V
out
with respect to V
in
, set to -1
( )
T
n
IL in
T in n
in
out
V
Rk
V V
V V Rk
dV
dV
+ = =
÷ = ÷ ÷ =
1
1
increase V
IL
(and
NM
L
) by reducing k
n
CADENCE CONFIDENTIAL 77
• V
IH
= high unity gain point of VTC
– When V
in
= V
IH
, NMOS in linear region:
( ) | |
( )
2
2
1
2
2
1
out n out T in n out DD
out out T in n
out DD
RV k V V V R k V V
V V V V k
R
V V
÷ ÷ = ÷
÷ ÷ =
÷
– Take derivative of V
out
with respect to V
in
, set to -1
( )
( )
out n out n T in n
in
out
out n out n
in
out
T in n
in
out
RV k RV k V V R k
dV
dV
RV k RV k
dV
dV
V V R k
dV
dV
+ + ÷ ÷ =
÷ + ÷ = ÷
1
– Solve this equation simultaneously with (1) to get:
R k R k
V
V V
n n
DD
T IH
1
3
8
÷ + =
(1)
Resistive-load inverter: V
IH
CADENCE CONFIDENTIAL 78
Resistive-load inverter: V
TH

• Threshold of resistive-load inverter: V
TH
:
– Point on VTC where V
in
= V
out
:
– NMOS in saturation (ignoring l):
( )
( )
2
'
2
1
2
'
2
1
) (
T TH L
W TH DD
TH out in
T in L
W
D
V V k
R
V V
V V V
V V k I
÷ =
÷
= =
÷ =
– Solve this quadratic for V
TH

CADENCE CONFIDENTIAL 79
Resistive-load inverter: VTC
• Plot I
DS
of transistor and I
load
of resistor vs. V
out
• Since currents must be equal, intersection points define VTC
D
r
a
i
n

c
u
r
r
e
n
t

I
D
S

V
out
= V
DS

V
in
=2V
V
DD

V
in
=1V
V
in
=3V
V
in
=4V
V
o
u
t

V
in

1 2 3 4 0
V
DD

Resistor load line
(slope = 1/R)
R
V
DD
V
OL

CADENCE CONFIDENTIAL 80
Resistive-load inverter: VTC
• Changing value of R affects VTC curve
• larger R → reduces V
OL
and improves NM
L
but degrades NM
H
D
r
a
i
n

c
u
r
r
e
n
t

I
D
S

V
out
= V
DS

V
in
=2V
V
DD

V
in
=1V
V
in
=3V
V
in
=4V
V
o
u
t

V
in

1 2 3 4 0
V
DD

R
V
DD
R
large
R
small R
R
small R
large
R
CADENCE CONFIDENTIAL 81
Resistive-load inverter: power
• Static power consumption: depends on input voltage V
in
– P
0
= power when V
in
= ‗0‘
– P
1
= power when V
in
= ‗1‘
• Average power depends on input probability
– a = probability that V
in
= ‗1‘
– (1-a) = probability that V
in
= ‗0‘
– P
avg
= aP
1
+ (1-a)P
0
CADENCE CONFIDENTIAL 82
Resistive-load inverter: power
• Find P
0
and P
1
:
– V
in
= 0: NMOS transistor off. No current flows from V
DD
to Gnd
(except leakage). P
0
= 0
– V
in
= V
DD
: NMOS transistor on. Output voltage V
out
= V
OL
.
( )
( )
( )
R
V V V
P
R
V V V
P
IV P
R
V V
I
DD OL DD
avg
DD OL DD
OL DD
load
÷
=
÷
=
=
÷
=
o
1
,
Static power consumed
when V
in
= V
DD

CADENCE CONFIDENTIAL 83
Resistive-load inverter: delay
Output falling (V
in
= 1):
• Discharge C
load
through
NMOS
• Need large I
D
, small I
R

R
I
R

I
D
„1‟
C
load

R
I
R

„0‟
C
load

Output rising (V
in
= 0):
• Charge C
load
through resistor
• Need large I
R

CADENCE CONFIDENTIAL 84
Resistive-load inverter: delay
• Delay calculation: approximate method
– Use an average value of capacitor current I
C
– Find current at start of transition, and current at end of transition, and
use the average
( )
0 1
0
1
0
,
V V
I
C
t
dV
I
C
dt
dV
I
C
dt
dt
dV
C I
avg
d
V
V
avg
t
avg
avg
d
÷ =
=
= =
} }
For rise delay:
V
0
= 0, V
1
= V
DD
/2
For fall delay:
V
0
= V
DD
, V
1
= V
DD
/2
CADENCE CONFIDENTIAL 85
Resistive-load inverter: delay
• Inverter rise delay t
plh
:
– Beginning of transition:
R
V V
I V V
OL DD
C OL out
÷
= = ,
– End of transition:
R
V
I V V
DD
C DD out
2
,
2
1
= =
– Average current:
R
V V
I
OL DD
avg
4
2 3 ÷
=
– Delay:
( )
OL DD
OL DD
load
plh
avg
load
d
V V
V V
RC
t V V
I
C
t + ÷
÷
= ÷ =
2
1
0 1
2 3
4
,
V
in
V
out
CADENCE CONFIDENTIAL 86
Resistive-load inverter: delay
• Inverter fall delay t
phl
:
– Beginning of transition: V
out
=V
DD
(NMOS in saturation)
( )
2
2
1
0 T DD n C
V V k I ÷ =
– End of transition: V
out
=½V
CC
(NMOS in linear)
– Average current:
( )
1 0 2
1
C C avg
I I I + =
– Delay:
( ) ( )
DD
avg
load
phl
avg
load
d
V
I
C
t V V
I
C
t
2
1
0 1
, = ÷ =
( ) | | ( )
DD T DD n DD DD T DD n C
V V V k V V V V k I
2
1
2
4
1
2
4
1
2
1
1
÷ = ÷ ÷ =
CADENCE CONFIDENTIAL 87
Resistive-load inverter: problems
• Static power consumption
• Tradeoff between delay and power:
– For fast operation, need small resistor
– For low power, need large resistor
• V
OL
is larger than 0V
– Reduced noise margin
• Large area
– Hard to make large resistance values on chip
CADENCE CONFIDENTIAL 88
Pseudo-NMOS inverter
• Replace resistor with “always-on” PMOS
transistor
• Easier to implement in standard process
than large resistance value
• PMOS load transistor:
– On when V
GS
< V
T

V
GS
= -V
DD
: transistor always on
– Linear when V
DS
> V
GS
-V
T

V
out
-V
DD
> -V
DD
-V
T
→ V
out
> -V
T
– Saturated when V
DS
< V
GS
-V
T
→ V
out
-
V
DD
< -V
DD
-V
T
→ V
out
< -V
T
Vin
V
DD
Gnd
G
S
D
V
GS,P
= -V
DD
Remember:
V
T
(PMOS) < 0
Vout
CADENCE CONFIDENTIAL 89
Pseudo-NMOS inverter: V
OH

• V
OH
for pseudo-NMOS inverter:
– Vin = 0
– NMOS in cutoff: no drain current
• Result: V
OH
is V
DD
(as in resistive-load
inverter case)
V
DD
Gnd
Vout
CADENCE CONFIDENTIAL 90
Pseudo-NMOS inverter: V
OL

• Find V
OL
of pseudo-NMOS inverter:
– Vin = V
DD
: NMOS on in linear mode
( ) | |
2
2
1
OL OL Tn DD n Dn
V V V V k I ÷ ÷ =
– PMOS on in saturation mode (assume)
( )
2
2
1
Tp DD p Dp
V V k I ÷ ÷ =
(neglecting ì)
– Setting I
dn
= I
dp
:
( ) ( ) 0
2
2
1
2
2
1
= ÷ ÷ + ÷ ÷
Tp DD p OL Tn DD n OL n
V V k V V V k V k
• Key point: V
OL
is not zero
– Depends on thresholds, sizes of N and P transistors
CADENCE CONFIDENTIAL 91
Pseudo NMOS inverter: VTC
V
DS
= V
out

D
r
a
i
n

c
u
r
r
e
n
t

I
D
S

V
in
=2V
V
DD

V
in
=1V
V
in
=3V
V
in
=4V
-V
DS
= -(V
out
- V
DD
)
-
D
r
a
i
n

c
u
r
r
e
n
t

-
I
D
S

I/V curve for NMOS: I/V curve for PMOS:
V
GS
=-V
DD
• Plot of -I
DS
vs -V
DS
since
current is from source to drain
• Only one curve since V
GS
fixed
CADENCE CONFIDENTIAL 92
V
out
= V
DS

D
r
a
i
n

c
u
r
r
e
n
t

I
D
S

V
in
=2V
V
DD

V
in
=1V
V
in
=3V
V
in
=4V
V
o
u
t

V
in

1 2 3 4 0
V
DD

• Similar VTC to resistive-load inverter
• Sharper transition region, smaller area
Pseudo NMOS inverter: VTC
CADENCE CONFIDENTIAL 93
Depletion-load inverter
• Depletion-load inverter: uses depletion
NMOS transistor as load
– Depletion transistor has V
T
< 0
• Load is always on:
– V
GS
= 0 > V
T

• Body effect of depletion transistor is
significant (when Vout = V
OH
)
Vin
V
DD
Gnd
G
D
S
V
GS
= 0

Vout
CADENCE CONFIDENTIAL 94
Depletion-load inverter
• Static characteristics: V
OH
and V
OL

– V
OH
: NMOS driver is off. As long as body effect does not cause
V
T
(load) > 0, V
OH
= V
DD


– V
OL
: driver in linear mode, depletion load in saturation
( ) ( ) | |
2
2
1
2
2
1
OL OL Td DD nd Tl nl
V V V V k V k ÷ ÷ = ÷
(solve for V
OL
) → V
OL
is non-zero
Need to calculate using body-effect coefficient
CADENCE CONFIDENTIAL 95
CADENCE CONFIDENTIAL 96 CADENCE DESIGN SYSTEMS, INC.





CMOS INVERTER – Lecture 1
•Regions of Operation
•Noise margin
•Inverter capacitances
•Delay, Rise and Fall time


CADENCE CONFIDENTIAL 97
CMOS Inverter
• Complementary NMOS and PMOS
devices
• In steady-state, only one device is on (no
static power consumption)
• Vin=1: NMOS on, PMOS off
– Vout = V
OL
= 0
• Vin=0: PMOS on, NMOS off
– Vout = V
OH
= V
DD
• Ideal V
OL
and V
OH
!
• Ratioless logic
Vin Vout
V
DD
Gnd
CADENCE CONFIDENTIAL 98
CMOS Inverter: VTC
V
out
= V
DS

D
r
a
i
n

c
u
r
r
e
n
t

I
D
S

V
in
=2V
V
DD

V
in
=1V
V
in
=3V
V
in
=4V
V
o
u
t

V
in

1 2 3 4 0
V
DD

PMOS NMOS
• Output goes completely to V
DD
and Gnd
• Sharp transition region
CADENCE CONFIDENTIAL 99
CMOS inverter operation
• NMOS transistor:
– Cutoff if V
in
< V
TN
– Linear if V
out
< V
in
– V
TN
– Saturated if V
out
> V
in
– V
TN
• PMOS transistor
– Cutoff if (V
in
-V
DD
) < V
TP
→ V
in
< V
DD
+V
TP
– Linear if (V
out
-V
DD
)>V
in
-V
DD
-V
TP
→ V
out
>V
in
- V
TP
– Sat. if (V
out
-V
DD
)<V
in
-V
DD
-V
TP
→ V
out
< V
in
-V
TP
Vin Vout
V
DD
CADENCE CONFIDENTIAL 100
CMOS inverter VTC
P linear
N cutoff
P linear
N sat
P sat
N sat
P sat
N linear
P cutoff
N linear
CADENCE CONFIDENTIAL 101
CMOS inverter VTC
V
DD

V
DD

V
in

V
out

k
p
=k
n

k
p
=5k
n

k
p
=0.2k
n

• Increase W of PMOS
k
p
increases
VTC moves to right
• Increase W of NMOS
k
n
increases
VTC moves to left
• For V
TH
= V
DD
/2
k
n
= k
p

W
n
~ 2W
p

CADENCE CONFIDENTIAL 102
Effects of V
TH
adjustment
• Result from changing k
n
/k
p
ratio:
– Inverter threshold V
TH
= V
DD
/2
– Rise and fall delays unequal
– Noise margins not equal
• Reasons for changing inverter threshold
– Want a faster delay for one type of transition (rise/fall)
– Remove noise from input signal: increase one noise margin at
expense of the other
CADENCE CONFIDENTIAL 103
CMOS inverter: V
IL
• KCL:



• Differentiate and set dVout/dVin to –1





• Solve simultaneously with KCL to find V
IL

( ) ( ) | |
2
, , , 0 ,
2
, 0 ,
2
2 2
p DS p DS p T p GS
p
n T n GS
n
V V V V
k
V V
k
÷ ÷ = ÷
( ) ( )( ) ( ) | |
2
, 0
2
, 0
2
2 2
DD out DD out p T DD in
p
n T in
n
V V V V V V V
k
V V
k
÷ ÷ ÷ ÷ ÷ = ÷
( ) ( ) ( ) ( )
(
¸
(

¸

÷ ÷ ÷ + ÷ ÷ = ÷
in
out
DD out DD out
in
out
p T DD in p n T in n
dV
dV
V V V V
dV
dV
V V V k V V k
, 0 , 0
( ) ( )
DD p T IL out p n T IL n
V V V V k V V k ÷ + ÷ = ÷
, 0 , 0
2
R
n T R DD p T out
IL
k
V k V V V
V
+
+ ÷ +
=
1
2
, 0 , 0
p
n
R
k
k
k =
CADENCE CONFIDENTIAL 104
CMOS inverter: V
IH
• KCL:



• Differentiate and set dVout/dVin to –1





• Solve simultaneously with KCL to find V
IH

( ) | | ( )
2
, 0 ,
2
, , , 0 ,
2
2
2
p T p GS
p
n DS n DS n T n GS
n
V V
k
V V V V
k
÷ = ÷ ÷
( ) | | ( )
2
, 0
2
, 0
2
2
2
p T DD in
p
out out n T in
n
V V V
k
V V V V
k
÷ ÷ = ÷ ÷
( ) ( )
p T DD in p
in
out
out out
in
out
n T in n
V V V k
dV
dV
V V
dV
dV
V V k
, 0 , 0
÷ ÷ =
(
¸
(

¸

÷ + ÷
( ) ( )
p T DD IH p p T IH out n
V V V k V V V k
, 0 , 0
2 ÷ ÷ = + ÷
( )
R
n T out R p T DD
IH
k
V V k V V
V
+
+ + +
=
1
2
, 0 , 0
p
n
R
k
k
k =
CADENCE CONFIDENTIAL 105
CMOS inverter: V
TH
• KCL:



• Solve for V
TH
= V
in
= V
out

( ) ( )
2
, 0 ,
2
, 0 ,
2 2
p T p GS
p
n T n GS
n
V V
k
V V
k
÷ = ÷
( ) ( )
2
, 0
2
, 0
2 2
p T DD in
p
n T in
n
V V V
k
V V
k
÷ ÷ = ÷
( )
R
p T DD
R
n T
TH
k
V V
k
V
V
1
1
1
, 0 , 0
+
+ +
=
p
n
R
k
k
k =
CADENCE CONFIDENTIAL 106
CMOS inverter: Ideal V
TH




• Ideally, V
TH
= V
DD
/2
• Assuming V
T0,n
= V
T0,p
,
( )
R
p T DD
R
n T
TH
k
V V
k
V
V
1
1
1
, 0 , 0
+
+ +
=
p
n
R
k
k
k =
2
, 0
, 0
,
2
2
|
|
.
|

\
|
+
+
=
n T DD
p T DD
ideal R
V V
V V
k
1
,
=
ideal R
k
5 . 2 ~ =
|
.
|

\
|
|
.
|

\
|
p
n
n
p
L
W
L
W
µ
µ
CADENCE CONFIDENTIAL 107
• Assuming V
T0,n
= -V
T0,p
, and k
R
= 1,
( )
0
2 3
8
1
T DD IL
V V V + =
( )
0
2 5
8
1
T DD IH
V V V ÷ =
DD IH IL
V V V = +
IL OL IL L
V V V NM = ÷ =
IL IH DD IH OH H
V V V V V NM = ÷ = ÷ =
CMOS inverter: V
IL
and V
IH
for Ideal V
TH
CADENCE CONFIDENTIAL 108
Vin
V
DD
Gnd
Cgd,p
Cgs,p
Cdb,p
Csb,p
Cgd,n
Cgs,n Csb,n
Cdb,n
Cint Cg
f
Cap on node f:

• Junction cap
Cdb,p and Cdb,n
• Gate capacitance
Cgd,p and Cgd,n
• Interconnect cap
• Receiver gate cap

CMOS inverter: capacitances
CADENCE CONFIDENTIAL 109
• Junction capacitances C
db,p
and C
db,n
:
– Equation for junction cap



– Non-linear, depends on voltage across junction
– Use K
eq
factor to get equivalent capacitance for a voltage
transition
( )
m
d a
d a
j
m
j
j
N N
N N q
C
V
AC
V C
|
|
.
|

\
|
+
=
|
|
.
|

\
|
÷
=
0
0
0
0
1
2
,
1
|
c
|
jsw eqsw j eq db
C PK C AK C + =
CMOS inverter: capacitances
CADENCE CONFIDENTIAL 110
• Gate capacitances C
GD,p
and C
GD,n
:
– In steady state, what regions are transistors in?
– One is in cutoff: C
GD
= C
GS
= 0
– One is in saturation: C
GD
= 0
– Therefore, gate-to-drain capacitance is only due to overlap
capacitance:
D ox n gd p gd
WL C C C = =
, ,
However, also need to consider Miller effect ...
CMOS inverter: capacitances
CADENCE CONFIDENTIAL 111
• When input rises by AV, output falls by AV
– Effective voltage change across C
gd1
is 2AV
– Effective capacitance to ground is twice C
gd1

• Including Miller effect:
Vin
Vout
C
gd1

Vin
Vout
2C
gd1

D ox n gd p gd
WL C C C 2
, ,
= =
CMOS inverter: capacitances
CADENCE CONFIDENTIAL 112
• Interconnect capacitance
– Due to capacitance of metal and poly lines used to connect
transistors
– Complex; includes parallel-plate and fringing-field components
– For wide wires:
WL
t
C
ox
ox
c
=
int
t
ox
= thickness of field oxide
Sample capacitances for 1µm process:
poly: 0.058 fF/µm
2
M1: 0.031 fF/µm
2
M2: 0.015 fF/µm
2
M3: 0.010 fF/µm
2
CMOS inverter: capacitances
CADENCE CONFIDENTIAL 113
• Receiver gate capacitance
– Includes all capacitances of gate(s) connected to output node
– Unknown region of operation for receiver transistor: total gate cap
varies from (2/3)WLC
ox
to WLC
ox
– Ignore Miller effect since operation unknown
– Assume worst-case value, include overlap
ox D ox eff g
C WL C WL C 2 + =
Review: CMOS inverter capacitances
CADENCE CONFIDENTIAL 114
First-order inverter delay
• Assume: Current charging or discharging
capacitance C
load
is nearly constant I
avg

Vin Vout
C
load

( )
( )
SS DD
avg
load
PLH
DD DD
avg
load
PHL
V V
I
C
t
V V
I
C
t
÷ =
÷ =
2
1
2
1
CADENCE CONFIDENTIAL 115
Inverter delay, falling
• Assume PMOS fully off (I
D,p
= 0)
C
load

Vin
I
D.n

dt
dV
C I
dt
dV
C I
out
load n D
=
=
,
Need to determine I
D,n

CADENCE CONFIDENTIAL 116
Inverter delay, falling
• From t
0
to t
1
: NMOS in saturation
• From t
1
to t
2
: NMOS in linear region
• Find I
D
in each region
V
DD
V
DD
- Vtn
V
DD
/2
t
0
t
1
t
2

NMOS in saturation
NMOS in linear region
CADENCE CONFIDENTIAL 117
CMOS inverter delay
• Another approximate method:
– Again assume constant I
avg
– I
avg
= current I
1
at start of transition
– good approximation esp. for deep
submicron
( )
( )
2
2
TP DD p
DD load
PLH
Tn DD n
DD load
PHL
V V k
V C
t
V V k
V C
t
÷
=
÷
=
V
1
=V
DD
V
2
=½V
DD
t
1
t
2

I
1

I
avg
= I
1
CADENCE CONFIDENTIAL 118
Inverter delay, falling t
1
-t
0

• Assumption: Input fast enough to go through transition before output
voltage changes
• Vout drops from V
DD
to V
DD
-V
TN
(NMOS saturated)
2
, 0
, 0
0 1
2
, 0
2
, 0
2
, 0
) (
2
) (
2
2 / ) ( 2 / ) (
, 0
1
0
n T OH n
n T L
V V
V
out
n T OH n
L
t
t
n T OH n n T in n DS
V V k
V C
t t
dV
V V k
C
dt
V V k V V k I
n T OH
OH
÷
= ÷
÷
÷
=
÷ = ÷ =
} }
÷
CADENCE CONFIDENTIAL 119
Inverter delay, falling t
2
-t
1

• V
out
drops from (V
OH
-V
T0,n
) to V
DD
/2
• NMOS in linear region
| |
| |
(
¸
(

¸

+
+ ÷ ÷
÷
= ÷
÷ ÷
÷ = ÷
÷ ÷ =
}
+
÷
2 / ) (
2 / ) ( ) ( 2
ln
) (
) (
) (
, 0
, 0
1 2
2 / ) (
2
2
1
, 0
1 2
2
2
1
, 0
, 0
OL OH
OL OH n T OH
n T OH n
L
V V
V V
out out n T OH n
out
L
out out n T OH n DS
V V
V V V V
V V k
C
t t
V V V V k
dV
C t t
V V V V k I
OL OH
n T OH
CADENCE CONFIDENTIAL 120
Inverter delay, falling
• Total fall delay = (t
1
-t
0
) + (t
2
-t
1
)
(
¸
(

¸

|
|
.
|

\
|
÷
+
÷
+
÷ ÷
= 1
) ( 4
ln
2
) (
, 0
, 0
, 0
, 0 OL OH
n T OH
n T OH
n T
n T OH n
L
PHL
V V
V V
V V
V
V V k
C
t
CADENCE CONFIDENTIAL 121
Inverter delay, rising
• Similar calculation as for falling delay
• Separate into regions where PMOS is in linear, saturation
(
(
¸
(

¸

|
|
.
|

\
|
÷
+
÷ ÷
+
÷ ÷ ÷ ÷
= 1
) ( 4
ln
2
) (
, 0
, 0
, 0
, 0 OL OH
p T OL OH
p T OL OH
p T
p T OL OH p
L
PLH
V V
V V V
V V V
V
V V V k
C
t
CADENCE CONFIDENTIAL 122
Inverter rise, fall time
• Exact method: separate into regions
– t
1

– V
out
drops from 0.9V
DD
to V
DD
-V
T
(NMOS in saturation)
– V
out
rises from 0.1V
DD
to V
T
(PMOS in saturation)
– t
2

– V
out
drops from V
DD
-V
T
to 0.1V
DD
(NMOS in linear region)
– V
out
rises from V
T
to 0.9 V
DD
(PMOS in linear region)
– t
f,r
= t
1
+ t
2


CADENCE CONFIDENTIAL 123
Inverter rise, fall time
• Average current method:
– Find current at start and end of transition
– Find average and use
avg
rise f all
I
V CA
=
,
t
CADENCE CONFIDENTIAL 124
How to improve delay?
• Minimize load capacitances
– Small interconnect capacitance
– Small Cg of next stage
• Raise supply voltage
• Increase transistor gain factor
– increase transistor drive current for charging/discharging output
capacitance
CADENCE CONFIDENTIAL 125
CMOS inverter delay
• Review of exact method
– Break transition into regions of operation
– Example: t
phl
(output falling):
VDD
VDD - Vtn
VDD/2
t
0
t
1
t
2

NMOS in saturation
NMOS in linear region
CADENCE CONFIDENTIAL 126
CMOS inverter delay
• What if input has finite rise/fall time?
– Both transistors are ON for some amount of time
– Capacitor charge/discharge current is reduced
2
2
2
) ( ) (
|
.
|

\
|
+ =
r
phl phl
t
step t actual t
2
2
2
) ( ) (
|
|
.
|

\
|
+ =
f
plh plh
t
step t actual t
Empirical equations:
t
rise
(ns)
t
p
H
L
(
n
s
)

CADENCE CONFIDENTIAL 127 CADENCE DESIGN SYSTEMS, INC.





SESSION 3: CMOS LOGIC STRUCTURES
Lecture 1
•MOS a Switch
•Static CMOS
•NAND,NOR
•Transistor sizing
•Complex Gate
•Design techniques
CADENCE CONFIDENTIAL 128
Switch-level model
• Model transistors as switches and
resistances
• Resistance R
on
= average resistance for a
transition
• For NMOS t
phl
:
R
n

R
P

A
A
( )
(
(
¸
(

¸

|
|
.
|

\
|
+
|
|
.
|

\
|
=
= + = =
= =
DD out DD out
V V
D
DS
V V
D
DS
on
DD out NMOS DD out NMOS on
I
V
I
V
R
V V R V V R R
2
1
2
1
2
1
2
1
) ( ) (
C
L

CADENCE CONFIDENTIAL 129
Switch-level model
Delay estimation using switch-level model (for general
RC circuit):
R
n

C
L

| |
|
|
.
|

\
|
= ÷ =
= = ÷
= ÷ =
= ÷ =
}
0
1
0 1
0 1
ln ) ln( ) ln(


1
0
V
V
RC V V RC t
dV
V
RC
t t t
dV
V
RC
dt
R
V
I
dV
I
C
dt
dt
dV
C I
p
V
V
p
CADENCE CONFIDENTIAL 130
Switch-level model
Delay estimation using switch-level model (for
general RC circuit):
R
n

C
L

| |
|
|
.
|

\
|
= ÷ =
= = ÷
= ÷ =
= ÷ =
}
0
1
0 1
0 1
ln ) ln( ) ln(


1
0
V
V
RC V V RC t
dV
V
RC
t t t
dV
V
RC
dt
R
V
I
dV
I
C
dt
dt
dV
C I
p
V
V
p
CADENCE CONFIDENTIAL 131
Switch-level model
• For fall delay t
phl
, V
0
=V
DD
, V
1
=V
DD
/2
L p plh
L n phl
p
DD
DD
p
C R t
C R t
RC t
V
V
RC
V
V
RC t
69 . 0
69 . 0
) 5 . 0 ln(
ln ln
2
1
0
1
=
=
=
|
|
.
|

\
|
=
|
|
.
|

\
|
=
Standard RC-delay
equations
CADENCE CONFIDENTIAL 132
Static CMOS
• Complementary pullup network
(PUN) and pulldown network
(PDN)
• Only one network is on at a time
• PUN: PMOS devices
– Why?
• PDN: NMOS devices
– Why?
• PUN and PDN are dual
networks
• Output is always connected to
V
DD
or Gnd
V
DD
V
SS
PUN
PDN
In1
In2
In3
F = G
In
1
In
2
In
3
PUN and PDN are Dual Networks
PMOS Only
NMOS Only
CADENCE CONFIDENTIAL 133
Dual Networks
B
A
F
• Dual networks:
• parallel connection in PDN = series
connection in PUN, vice-versa

• If CMOS gate implements logic
function F:
– PUN implements function F
– PDN implements function G = F‘
Example: NAND gate
parallel
series
CADENCE CONFIDENTIAL 134
NAND gate
• NAND function: F = A•B

• PUN function: F = A • B = A + B
– ―Or‖ function (+) → parallel connection
– Inverted inputs A, B → PMOS transistors

• PDN function: G = F = A • B
– ―And‖ function (•) → series connection
– Non-inverted inputs → NMOS transistors
CADENCE CONFIDENTIAL 135
NOR gate
• NOR gate operation: F = A+B
• PDN: G = F = A+B
• PUN: F = A+B = A•B
A
B
A
B
CADENCE CONFIDENTIAL 136
CMOS gate design
• Designing a CMOS gate:
– Find pulldown NMOS network from logic function or by inspection
– Find pullup PMOS network
– By inspection
– Using logic function
– Using dual network approach
– Size transistors using equivalent inverter
– Find worst-case pullup and pulldown paths
– Size to meet rise/fall or threshold requirements

CADENCE CONFIDENTIAL 137
Graph-based dual network
• Draw network for PUN or PDN
– Circuit nodes are vertexes
– Transistors are edges

A
B
F
gnd
A B
F
CADENCE CONFIDENTIAL 138
• To derive dual network:
– Create new node in each enclosed region of graph
– Draw new edge intersecting each original edge
– Edge is controlled by inverted input

A
B
A B A
B
F
Graph-based dual network
CADENCE CONFIDENTIAL 139
Analysis of CMOS gates
• Represent ―on‖ transistors as resistors
1
1
1
R
W
W
W
R
R
• Transistors in series → resistances in series
• Effective resistance = 2R
• Effective width = ½ W
CADENCE CONFIDENTIAL 140
• Represent ―on‖ transistors as resistors
• Transistors in parallel → resistances in parallel
• Effective resistance = ½ R
• Effective width = 2W
0
0
0
R
W
W W
R R
Analysis of CMOS gates
CADENCE CONFIDENTIAL 141
Equivalent Inverter
• CMOS gates: many paths to V
DD
and Gnd
– Multiple values for V
TH
, V
IL
, V
OL
, etc
– Different delays for each input combination
• Equivalent inverter
– Represent each gate as an inverter with appropriate device width
– Include only transistors which are on or switching
– Calculate V
TH
, delays, etc using inverter equations
CADENCE CONFIDENTIAL 142
• V
TH
of the equivalent inverter is used (assumes all inputs
are tied together)
– For specific input patterns, V
TH
will be different
• For V
IL
and V
IH
, only the worst case is interesting since
circuits must be designed for worst-case noise margin
• For delays, both the maximum and minimum must be
accounted for in race analysis

Static CMOS Logic Characteristics
CADENCE CONFIDENTIAL 143
Equivalent Inverter: V
TH
• Example: NAND gate threshold V
TH

Three possibilities:
– A & B switch together
– A switches alone
– B switches alone

• What is equivalent inverter for each case?
CADENCE CONFIDENTIAL 144
Equivalent inverter: delay
• Represent complex gate as inverter for delay estimation
• Use worse-case delays
• Example: NAND gate
– Worse-case (slowest) pull-up: only 1 PMOS ―on‖
– Pull-down: both NMOS ―on‖
W
N
W
N
W
P
W
P
W
P
½ W
N
CADENCE CONFIDENTIAL 145
Example: NOR gate
• Find threshold voltage V
TH
when both
inputs switch simultaneously
• Two methods:
– Transistor equations
– Equivalent inverter
A
B
A
B
F
W
N
W
P
W
P
W
N
CADENCE CONFIDENTIAL 146
Example: complex gate
Design CMOS gate for this truth table:
A B C F
0 0 0 1
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 0
F = A•(B+C)
CADENCE CONFIDENTIAL 147
Example: complex gate
Completed gate:
C B
A
C
B
A
F
W
P
W
P
W
P
W
N
W
N
W
N
• What is worse-case pull up delay?


• What is worse-case pull down delay?



• Effective inverter for delay calculation:
½ W
P
½ W
N
CADENCE CONFIDENTIAL 148
Transistor Sizing
• Sizing for switching threshold
– All inputs switch together

• Sizing for delay
– Find worst-case input combination

• Find equivalent inverter, use inverter analysis to set device
sizes

CADENCE CONFIDENTIAL 149
V
DD
A
B
A
B
C
D
C D
t
p
a
1
FI a
2
FI
2
a
3
FO + + =
Fan-Out: Number of Gates Connected
2 Gate Capacitances per Fan-Out
FanIn: Quadratic Term due to:
1. Resistance Increasing
2. Capacitance Increasing
(t
pHL
)
Influence of Fan-In and Fan-Out
CADENCE CONFIDENTIAL 150
1 3 5 7 9
fan-in
0.0
1.0
2.0
3.0
4.0
t
p

(
n
s
e
c
)
t
pHL
t
p
t
pLH
linear
quadratic
AVOID LARGE FAN-IN GATES! (Typically not more than FI < 4)
t
p
as a function of Fan-In
CADENCE CONFIDENTIAL 151
• Transistor Sizing:
As long as Fan-out Capacitance dominates
• Progressive Sizing:
C
L
In
1
In
N
In
3
In
2
Out
C
1
C
2
C
3
M1 > M2 > M3 > MN
M1
M2
M3
MN
Distributed RC-line
Can Reduce Delay with more than 30%!
Complex Gate - Design Techniques
CADENCE CONFIDENTIAL 152
In
1
In
3
In
2
C
1
C
2
C
L
M1
M2
M3
In
3
In
1
In
2
C
3
C
2
C
L
M3
M2
M1
(a) (b)
• Transistor Ordering
critical path
critical path
Complex Gate - Design Techniques(2)
CADENCE CONFIDENTIAL 153
• Improved Logic Design
Complex Gate - Design Techniques(3)
CADENCE CONFIDENTIAL 154
• Buffering: Isolate Fan-in from Fan-out
C
L
C
L
Complex Gate - Design Techniques(4)
CADENCE CONFIDENTIAL 155
CMOS design guidelines
• Transistor sizing
– Size for worst-case delay, threshold, etc
– Tapering: transistors near power supply are larger than transistors
near output
• Transistor ordering
– Critical signal is latest-arriving signal to gate
– Put critical signals closest to output
– Stack nodes are discharged by early signals
– Reduced body effect on top transistor
CADENCE CONFIDENTIAL 156
CMOS design guidelines
• Limit fan-in of gate
– Fan-in: number of gate inputs
– Affects size of transistor stacks
– Normally fan-in limit is 3-4
• Convert large multi-input gates into smaller chain of gates
• Limit fanout of gate
– fanout: number of gates connected to output
– Capacitive load: affects gate delay
• NANDs are better than NORs
CADENCE CONFIDENTIAL 157
• 5 minute break
CADENCE CONFIDENTIAL 158 CADENCE DESIGN SYSTEMS, INC.





PASS LOGIC and D Latch – Lecture 1
Transmission gate
MUX
Tristate Inverter
D Latch, MS register
CADENCE CONFIDENTIAL 159
CMOS disadvantages
• For N-input CMOS gate, 2N transistors required
– Each input connects to an NMOS and PMOS transistor
– Large input capacitance: limits fanout
• Large fan-in gates: always have long transistor stack in PUN or
PDN
– Limits pullup or pulldown delay
– Requires very large transistors
• Single-stage gates are inverting
CADENCE CONFIDENTIAL 160
Pseudo-NMOS logic
• Pseudo-NMOS: replace PMOS PUN with single ―always-on‖ PMOS
device
• Same problems as pseudo-NMOS inverter:
– V
OL
larger than 0
– static power when PDN is on
• Advantages
– Replace large PMOS stacks with single device
– Reduces overall gate size, input capacitance
– Especially useful for wide-NOR structures
CADENCE CONFIDENTIAL 161
Transmission Gate Logic
• NMOS and PMOS connected in parallel
• Allows full rail transition – ratioless logic
• Equivalent resistance relatively constant during transition
• Complementary signals required for gates
• Some gates can be efficiently implemented using transmission
gate logic
= =
CADENCE CONFIDENTIAL 162
Equivalent Resistance
• For a rising transition at the output (step input)
– NMOS sat, PMOS sat until output reaches |V
TP
|
– NMOS sat, PMOS lin until output reaches V
DD
-V
TN

– NMOS off, PMOS lin for the final V
DD
– V
TN
to V
DD
voltage swing
V
in
V
out
V
DD
0V

CADENCE CONFIDENTIAL 163
• NMOS sat:


• PMOS sat:
( )
( )
2
2
1
,
tn out DD n
out DD
n eq
V V V k
V V
R
÷ ÷
÷
=
( )
( )
2
2
1
,
tp DD p
out DD
p eq
V V k
V V
R
÷ ÷
÷
=
Equivalent Resistance – Region 1
CADENCE CONFIDENTIAL 164
• NMOS sat:


• PMOS lin:
( )
( )( ) ( ) ( )
( ) ( ) | |
out DD TP DD p
out DD out DD TP DD p
out DD
p eq
V V V V k
V V V V V V k
V V
R
÷ ÷ ÷
=
÷ ÷ ÷ ÷
÷
=
2
2
2
2
2
,
( )
( )
2
2
1
,
tn out DD n
out DD
n eq
V V V k
V V
R
÷ ÷
÷
=
Equivalent Resistance – Region 2
CADENCE CONFIDENTIAL 165
• NMOS off:


• PMOS lin:
· =
n eq
R
,
( ) ( ) | |
out DD TP DD p
p eq
V V V V k
R
÷ ÷ ÷
=
2
2
,
Equivalent Resistance – Region 3
CADENCE CONFIDENTIAL 166
Equivalent resistance
• Equivalent resistance R
eq
is
parallel combinaton of R
eq,n

and R
eq,p

• R
eq
is relatively constant
V
DD
V
Tp
V
cc
-V
Tn
R
eq,p
R
eq,n
R
eq
R

V
out
CADENCE CONFIDENTIAL 167
Resistance Approximations
• To estimate equivalent resistance:
– Assume both transistors in linear region
– Ignore body effect
– Assume voltage difference is small
( )
tn DD n
n eq
V V k
R
÷
~
1
,
( )
tp DD p
p eq
V V k
R
÷
~
1
,
( ) ( )
tp DD p tn DD n
eq
V V k V V k
R
÷ + ÷
~
1
CADENCE CONFIDENTIAL 168
Transmission Gate Logic
• Useful for multiplexers (select between multiple inputs) and XORs
• Transmission gate implements logic function F = A if S
– If S is 0, output is floating, which should be avoided
– Always make sure one path is conducting from input to output
• Two transmission gates can implement
AS + BS‘
– TGate 1: A if S
– TGate 2: B if S‘

CADENCE CONFIDENTIAL 169
A
M2
M1
B
S
S
S
F
VDD
GND
V
DD

In
1
In
2
S S
S
S
Pass-Transistor Based Multiplexer
CADENCE CONFIDENTIAL 170
A
B
F
B
A
B
B
M1
M2
M3/M4
Transmission Gate XOR
CADENCE CONFIDENTIAL 171
• Can implement Boolean formulas as networks of switches.
• Can build switches from MOS transistors—transmission gates.
• Transmission gates do not amplify but have smaller layouts.
Switch logic

CADENCE CONFIDENTIAL 172
complementary
n-type
Types of switches

CADENCE CONFIDENTIAL 173
n-type switch has source-drain voltage drop when conducting:
– conducts logic 0 perfectly;
– introduces threshold drop into logic 1.
V
DD
V
DD
V
DD
- V
t
Behavior of n-type switch
CADENCE CONFIDENTIAL 174
n-type switch driving static logic
Switch under-drives static gate, but gate restores logic levels.
V
DD
V
DD
V
DD
- V
t


CADENCE CONFIDENTIAL 175
n-type switch driving switch logic
Voltage drop causes next stage to be turned on weakly.
V
DD V
DD
- V
t
V
DD
V
DD
-2 V
t
CADENCE CONFIDENTIAL 176
Behavior of complementary switch
• Complementary switch products full-supply voltages for
both logic 0 and logic 1:
– n-type transistor conducts logic 0;
– p-type transistor conducts logic 1.
CADENCE CONFIDENTIAL 177
NMOS in SERIES PARALLEL
• Switch controlled by the gate input
• NMOS switch closes when the gate input is High






• Remember - NMOS transistors pass a strong 0 but a weak 1








CADENCE CONFIDENTIAL 178
PMOS in SERIES PARALLEL
• Switch controlled by the gate input
• PMOS switch closes when the gate input is low







• Remember - PMOS transistors pass a strong 1 but a weak 0








CADENCE CONFIDENTIAL 179
Pass Transistor Logic






• Primary inputs drive source/drain terminals as well as gate terminals
• N transistors instead of 2N
• No static power consumption
• Ratioless
• Bidirectional (versus undirectional)

CADENCE CONFIDENTIAL 180
NMOS Only Switch






• VC does not pull up to V
DD
, but V
DD
– V
Tn
• Threshold voltage drop causes static power consumption (M2 may
be weakly conducting forming a path from V
DD
to GND)
CADENCE CONFIDENTIAL 181
NMOS Only Switch







• VC does not pull up to V
DD
, but V
DD
– V
Tn
• Threshold voltage drop causes static power consumption (M2 may
be weakly conducting forming a path from V
DD
to GND)
• Body effect - VSB at x - when pulling high (B is tied to GND and S
charged up close to VDD). So the voltage drop is even worse
CADENCE CONFIDENTIAL 182
Cascaded Pass Transistors








• Pass transistor gates should not be cascaded as on the left
CADENCE CONFIDENTIAL 183
Tristate Inverter
– Tri-state inverters : 0 1 Z
A F
en
en
tri-state
inverter
When en=0, F is
“floating”
CADENCE CONFIDENTIAL 184
Memory elements
• Stores a value as controlled by clock.
• May have load signal, etc.
• In CMOS, memory is created by:
– capacitance (dynamic);
– feedback (static).
CADENCE CONFIDENTIAL 185
Variations in memory elements
• Form of required clock signal.
• How behavior of data input around clock affects the stored
value.
• When the stored value is presented to the output.
• Whether there is ever a combinational path from input to
output.
CADENCE CONFIDENTIAL 186
Memory element terminology
• Latch: transparent when internal memory is being set from
input.
• Flip-flop: not transparent—reading input and changing output
are separate events.
CADENCE CONFIDENTIAL 187
Clock terminology
• Clock edge: rising or falling transition.
• Duty cycle: fraction of clock period for which clock is active
(e.g., for active-low clock, fraction of time clock is 0).
CADENCE CONFIDENTIAL 188
Memory element parameters
• Setup time: time before clock during which data input must be
stable.
• Hold time: time after clock event for which data input must
remain stable.
clock
data
CADENCE CONFIDENTIAL 189
Dynamic latch
Stores charge on inverter gate capacitance:
CADENCE CONFIDENTIAL 190
Latch characteristics
• Uses complementary transmission gate to ensure that storage
node is always strongly driven.
• Latch is transparent when transmission gate is closed.
• Storage capacitance comes primarily from inverter gate
capacitance.
CADENCE CONFIDENTIAL 191
Latch operation
• | = 0: transmission gate is off, inverter output is determined
by storage node.
• | = 1: transmission gate is on, inverter output follows D input.

• Setup and hold times determined by transmission gate—must
ensure that value stored on transmission gate is solid.
CADENCE CONFIDENTIAL 192
Stored charge leakage
• Stored charge leaks away due to reverse-bias leakage
current.
• Stored value is good for about 1 ms.
• Value must be rewritten to be valid.
• If not loaded every cycle, must ensure that latch is loaded
often enough to keep data valid.
CADENCE CONFIDENTIAL 193
Non-dynamic latches
• Must use feedback to restore value.
• Some latches are static on one phase (pseudo-static)—load
on one phase, activate feedback on other phase.
CADENCE CONFIDENTIAL 194
Re-circulating latch
Static on one phase:
LD‟
LD
|
2

|
2
CADENCE CONFIDENTIAL 195
Clocked inverter
symbol
circuit
|‟
|
CADENCE CONFIDENTIAL 196
Clocked inverter operation
| = 0: both clocked transistors are off, output is floating.
| = 1: both clocked inverters are on, acts as an inverter to drive
output.
CADENCE CONFIDENTIAL 197
Clocked inverter latch
CADENCE CONFIDENTIAL 198
Clocked inverter latch operation
• Not transparent—use multiple storage elements to isolate
output from input.
• Major varieties:
• master-slave;
• edge-triggered.
| = 0: i1 is off, i2-i3 form feedback circuit.
| = 1: i2 is off, breaking feedback; i1 is on, driving i3 and output.
• Latch is transparent when | = 1.
CADENCE CONFIDENTIAL 199
Flip-flops
• Not transparent—use multiple storage elements to isolate
output from input.
• Major varieties:
– master-slave;
– edge-triggered.
CADENCE CONFIDENTIAL 200
Master-slave flip-flop
|
D Q
master slave
CADENCE CONFIDENTIAL 201
Master-slave operation
• ø = 0: master latch is disabled; slave latch is enabled, but
master latch output is stable, so output does not change.
• ø = 1: master latch is enabled, loading value from input; slave
latch is disabled, maintaining old output value.
CADENCE CONFIDENTIAL 202
Signal skew
• Machine data signals must obey setup and hold times—
avoid signal skew.
• If delays along different paths vary significantly, outputs
may not be valid even though inputs are.
CADENCE CONFIDENTIAL 203
Signal skew example
• Invalid latch input: signals are not aligned:
D Q
a
b
x
time
a
b
x
stable
5
10
stable
stable
circuit
timing diagram
CADENCE CONFIDENTIAL 204
Clock skew
Clock must arrive at all memory elements in time to load data.
CADENCE CONFIDENTIAL 205 CADENCE DESIGN SYSTEMS, INC.





SESSION 4: POWER DISSIPATION–
Lecture
•Static and Dynamic Power Dissipation
•Short Circuit Dissipation
•Impact of Rise/Fall Times on Short-Circuit Currents.
• Buffer Design Issues
CADENCE CONFIDENTIAL 206
CMOS inverter power
• Power has three components
– Static power: when input isn‘t switching
– Dynamic capacitive power: due to charging and discharging of
load capacitance
– Dynamic short-circuit power: direct current from V
DD
to Gnd when
both transistors are on
CADENCE CONFIDENTIAL 207
static power
• Static power consumption:
– Static current: in CMOS there is no static current as long as V
in
< V
TN

or V
in
> V
DD
+V
TP
– Leakage current: determined by ―off‖ transistor
– Influenced by transistor width, supply voltage, transistor threshold
voltages
V
DD
Vss
I
leak,n
V
DD
V
DD
I
leak,p
Vss
V
DD
CADENCE CONFIDENTIAL 208
Dynamic capacitive power
Energy for one
complete cycle
(charge and
discharge) f V C P
V C E
dV V C
dt
dt
dV
C V
dt V t i E
DD L dyn
DD L vdd
V
out DD L
out
L DD
DD vcc vdd
DD
2
2
0
0
0


) (
=
=
=
=
=
}
}
}
·
·
CADENCE CONFIDENTIAL 209
Dynamic capacitive power
• Formula for dynamic power:

• Observations
– Does not (directly) depend on device sizes
– Does not depend on switching delay
– Applies to general CMOS gate in which:
– Switched capacitances are lumped into CL
– Output swings from Gnd to V
DD
– Input signal approximated as step function
– Gate switches with frequency f
f V C P
DD L dyn
2
=
CADENCE CONFIDENTIAL 210
Dynamic short-circuit power
• Short-circuit current flows from V
DD
to Gnd when both transistors
are on
• Plot on VTC curve:

V
DD

V
DD

V
in

V
out

I
D

I
max

I
max
: depends on
saturation current
of devices
CADENCE CONFIDENTIAL 211
Dynamic short-circuit power
• Approximate short-circuit current as a triangular wave
• Energy per cycle:
f I V
t t
P
I V
t t t I
V
t I
V E
DD
f r
sc
DD
f r f
DD
r
DD sc
max
max
max
max
2
2 2 2
+
=
+
= + =
I
max
CADENCE CONFIDENTIAL 212
Inverter power consumption
• Total power consumption
leak DD
f r
DD DD L tot
stat sc dyn tot
I V f
t t
I V f V C P
P P P P
+
|
|
.
|

\
|
+
+ =
+ + =
2
max
2
• Energy-delay product:
– Multiply energy x delay: EDP = E*D
– Often the goal of a design is to minimize EDP
CADENCE CONFIDENTIAL 213
Power reduction
• Reducing dynamic capacitive power:
– Lower the voltage!
– Quadratic effect on dynamic power
– Reduce capacitance
– Short interconnect lengths
– Drive small gate load (small gates, small fan-out)
– Reduce frequency
– Lower clock frequency -> use more parallelism
– Lower signal activity
CADENCE CONFIDENTIAL 214
Power reduction
• Reducing short-circuit current:
– Fast rise/fall times on input signal
– Reduce input capacitance
– Insert small buffers to ―clean up‖ slow input signals before sending
to large gate
• Reducing leakage current:
– Small transistors (leakage proportional to width)
– Lower voltage
CADENCE CONFIDENTIAL 215
Inverter design
• Consider chain of minimum-sized inverters:
C
load
C
load
C
load
C
load

W
p
, W
n
W
p
, W
n
W
p
, W
n
W
p
, W
n

• Now double the size of each inverter:
2C
load
2C
load
2C
load
2C
load

2W
p
, 2W
n
2W
p
, 2W
n
2W
p
, 2W
n
2W
p
, 2W
n

Delay of single
inverter is t
p0
What is new
inverter delay?

CADENCE CONFIDENTIAL 216
Inverter chain delay
• Neglecting interconnect capacitance:
– Both delay and load capacitance scale linearly with inverter
size
– Increasing inverter size also increases capacitance -> delay
remains constant


• Including interconnect
capacitance
– Interconnect cap remains
constant
– Increasing inverter size
reduces delay


size
d
e
l
a
y

CADENCE CONFIDENTIAL 217
Inverter as a buffer
• Consider minimum-size inverter driving load C
load
:
C
load

W
p
,W
n

C
g

• Delay of inverter:
– Gate cap of min-size inverter = C
g

– Delay of min-size inverter driving another min-size inverter =
t
p0

0
,
p p g load
xt t xC C = =
CADENCE CONFIDENTIAL 218
Inverter as buffer
• Example:
– Assume t
p0
= 1ns
W
p
,W
n

20W
p
,20W
n

Inverter delay = 20ns!
• Reduce delay by inserting extra buffer
– What is the optimum ratio u?
C
load

W
p
,W
n

C
g

uW
p
,uW
n

W
p
,W
n

W
p
,W
n

Inverter delay = 1ns
CADENCE CONFIDENTIAL 219
Inverter as buffer
• Total delay = delay of first inverter + delay of buffer:
– First inverter has u-times larger load:
delay = ut
p0
– Second inverter has x/u-times larger load:
delay = (x/u)t
p0
– Total delay:
0 0 0 p p p p
t
u
x
u t
u
x
ut t
|
.
|

\
|
+ = + =
C
load

W
p
,W
n

C
g

uW
p
,uW
n

CADENCE CONFIDENTIAL 220
Inverter as buffer
• Find factor u which minimizes t
p
: take derivative of t
p
wrt u and
set to 0
x t t
x u
u
x
t
u
x
t
u
t
t
u
x
ut t
p opt p
opt
p p
p
p p p
0 ,
2
0
2
0
0 0
2
, 1
0
=
= =
= ÷ =
c
c
+ =
CADENCE CONFIDENTIAL 221
Inverter as buffer
• When should a single-inverter buffer be used?
– Only if combined delay of both inverters is faster than unbuffered
case
4
2
2
0 0
>
>
<
x
x x
xt x t
p p
x t t
p p 0
2 =
0 p p
xt t = unbuffered:
buffered:
single-inverter buffer is
faster if load is > 4X larger
CADENCE CONFIDENTIAL 222
Superbuffer design
• Large fixed load capacitance driven by chain of ―n‖
inverters
• Stage ratio = u
– First inverter is minimum size
– Each inverter is ―u‖ times bigger than previous one
• What is optimum ―u‖ and ―n‖ ?
C
load

1 u u
2
u
3

C
g

CADENCE CONFIDENTIAL 223
Superbuffer design
• t
p0
= average delay of one inverter driving another one of same size
• Delay of each stage = delay of inverter driving another inverter ―u‖
times bigger = ut
p0
• Total delay = n u t
p0
• Ratio of load cap to gate cap:
) ln(
) ln(
), ln( ) ln(
,
u
x
n u n x
u x
C
C
x
C u C
n
g
load
g
n
load
= =
= =
=


number of buffers
required
CADENCE CONFIDENTIAL 224
Superbuffer design
• Total delay:
0
) ln(
) ln(
p
t
u
u
x delay Total =
• Optimum stage delay u =
e ~ 2.7
• Including interconnect, u
ranges from 3-5
CADENCE CONFIDENTIAL 225
Buffer example
• A minimum-sized inverter (size 1)
needs to drive a fan-out of 4 size 20
inverters

• Find the delay for the (a) non-
buffered, (b) single buffer, and (c)
super-buffer case
C
g

1
20
20
20
20
t
p0
= 0.5 ns
CADENCE CONFIDENTIAL 226 CADENCE DESIGN SYSTEMS, INC.





SESSION 5: DYNAMIC LOGIC Lecture 1
•Pre charge evaluate
•Charge sharing, leakage
•Domino Logic
•C
2
MOS logic
CADENCE CONFIDENTIAL 227
M
p
M
e
V
DD
PDN
|
In
1
In
2
In
3
Out
M
e
M
p
V
DD
PUN
|
In
1
In
2
In
3
|
|
Out
C
L
C
L
|
p network
|
n network
2 phase operation:
• Evaluation
• Precharge
Dynamic Logic
CADENCE CONFIDENTIAL 228
M
p
M
e
V
DD
|
Out
|
A
B
C
• N + 1 Transistors
• Ratioless
• No Static Power Consumption
• Noise Margins small (NM
L
)
• Requires Clock
Example
CADENCE CONFIDENTIAL 229
0.00e+00 2.00e-09 4.00e-09 6.00e-09
t (nsec)
0.0
2.0
4.0
6.0
V
o
u
t

(
V
o
l
t
)
|
V
out
PRECHARGE
EVALUATION
Transient Response
CADENCE CONFIDENTIAL 230
In
1

In
2

In
3

In
4

Out
V
DD

GND
|
Dynamic 4 Input NAND Gate
CADENCE CONFIDENTIAL 231
Charge Sharing
• Output is floating after clk = ‗1‘ if inputs are ‗0‘
• If upper transistors in a stack switch, the intermediate and
output node voltages will be equalized, possibly leading to a
drop in the output voltage = noise
• Final output
V=(C
1
V
1
+C
2
V
2
)/(C
1
+C
2
)
may be higher if NMOS turns off
C1
C2
CADENCE CONFIDENTIAL 232
• Output is floating after clk = ‗1‘ if inputs are ‗0‘
• Since the current is not 0 when transistors are in cutoff, current
can leak away from the output when all inputs are ‗0‘
• Changes in input signals couple to the output and intermediate
nodes, also resulting in voltage drops
Charge Leakage & Cap. Coupling
CADENCE CONFIDENTIAL 233
Noise Solutions
• Charge sharing:
– Ensure the output capacitance is large enough such that the
voltage drop is minimal
– Precharge internal stack nodes to V
CC
– Pre-discharging internal stack nodes can increase performance,
but worsens noise
• Charge leakage/sharing and cap. coupling:
– Add a keeper PMOS (weak P pullup) – increased evaluation
contention
CADENCE CONFIDENTIAL 234
M
p
M
e
V
DD
|
Out
|
A
C
L
(1)
(2)
|
t
t
V
out
(b) Effect on waveforms (a) Leakage sources
precharge
evaluate
Minimum Clock Frequency: > 1 MHz
Reliability Problems -Charge Leakage
CADENCE CONFIDENTIAL 235
M
p
M
e
V
DD
|
Out
|
A
B = 0
C
L
C
a
C
b
M
a
M
b
X
C
L
V
DD
C
L
V
out
t
( )
C
a
V
DD
V
Tn
V
X
( )

( )
+ =
or
AV
out
V
out
t
( )
V
DD

C
a
C
L
-------- V
DD
V
Tn
V
X
( )

( )
– = =
AV
out
V
DD
C
a
C
a
C
L
+
----------------------
\ .
|
| |
– =
case 1) if AV
out
< V
Tn
case 2) if AV
out
> V
Tn
Charge Sharing (redistribution)
CADENCE CONFIDENTIAL 236
M
p
M
e
V
DD
|
Out
|
A
B
M
a
M
b
M
bl
M
p
M
e
V
DD
|
Out
|
A
B
M
a
M
b
M
bl
(b) Precharge of internal nodes
|
(a) Static bleeder
Charge Redistribution - Solutions
CADENCE CONFIDENTIAL 237
M
p
M
e
V
DD
|
Out
|
A
B
C
L
C
a
C
b
M
a
M
b
X
|
5V
overshoot
out
could potentially forward
bias the diode
Clock Feedthrough
CADENCE CONFIDENTIAL 238
M
p
M
e
V
DD
|
|
M
p
M
e
V
DD
|
|
In
Out1 Out2
|
Out2
Out1
In
V
t
A
V
V
Tn
(a)
(b)
Only 0
÷
1 Transitions allowed at inputs!
Cascading Dynamic Gates
CADENCE CONFIDENTIAL 239
Domino Logic
• Solves problem of cascading dynamic gates, but is non-inverting
– Add an inverter between dynamic gates
– Inverter drives the gate‘s fanout – increased performance
– Sometimes the inverter is replaced with a more complex static CMOS
gate
– Static CMOS gate improves dynamic noise margins
• Solve non-inverting problem by implementing both F and F separately
– Area/power doubles
CADENCE CONFIDENTIAL 240
Domino Logic
CADENCE CONFIDENTIAL 241
D
D
|
|
In
|
|
(a) Schematic diagram
(b) Non-overlapping clocks
Pseudo-static Latch
Charge-Based Storage
CADENCE CONFIDENTIAL 242
|
|
|
| D
In
A
B
|
|
Overlapping Clocks Can Cause
• Race Conditions
• Undefined Signals
Master-Slave Flip-Flop
CADENCE CONFIDENTIAL 243
|
2
|
1
|
1
|
2
D
In
|
1
|
2
t
|12
2 phase non-overlapping clocks
CADENCE CONFIDENTIAL 244
|
2
|
1
D In
Input Sampled
Output Enable
|
1
|
2
2-phase dynamic flip-flop
CADENCE CONFIDENTIAL 245
D In
|
| |
|
V
DD
V
DD
M1
M3
M4
M2 M6
M8
M7
M5
|÷section |÷section
C
L1
C
L2
X
C
2
MOS LATCH
Flip-flop insensitive to clock overlap
CADENCE CONFIDENTIAL 246
D In
1
M1
M3
M2 M6
M7
M5
1
D In
V
DD
V
DD
M1
M4
M2 M6
M8
M5
0 0
V
DD
V
DD
(a) (1-1) overlap (b) (0-0) overlap
X X
C
2
MOS avoids Race Conditions
CADENCE CONFIDENTIAL 247
In
F
Out
|
|
V
DD
|
|
V
DD
|
|
V
DD
C
2
C
1
G
C
3
NORA CMOS
What are the constraints on F and G?
Pipelined Logic using C
2
MOS
CADENCE CONFIDENTIAL 248

1
|
|
V
DD
|
|
V
DD
V
DD
Number of a static inversions should be even
Example
CADENCE CONFIDENTIAL 249
|
|
V
DD
V
DD
PDN
|
In
1
In
2
In
3
|
V
DD
PUN
|
|
Out
|
|
V
DD
Out
V
DD
PDN
|
In
1
In
2
In
3
|
V
DD
In
4
In
4
V
DD
(a) |-module
(b) |-module
Combinational logic Latch
NORA CMOS Modules
CADENCE CONFIDENTIAL 250
|
V
DD
Out
|
V
DD
Doubled n-C
2
MOS latch
In
|
V
DD
Out
|
V
DD
Doubled n-C
2
MOS latch
In
Doubled C
2
MOS Latches
CADENCE CONFIDENTIAL 251
|
V
DD
Out
|
V
DD
|
V
DD
|
V
DD
In
Static
Logic
PUN
PDN
Including logic into
the latch
Inserting logic between
latches
TSPC - True Single Phase Clock Logic
CADENCE CONFIDENTIAL 252
|
V
DD
D
V
DD
|
V
DD
D
|
V
DD
|
V
DD
D
V
DD
|
|
D
|
V
DD
|
V
DD
D
V
DD
|
|
D
(a) Positive edge-triggered D flip-flop (b) Negative edge-triggered D flip-flop
(c) Positive edge-triggered D flip-flop
using split-output latches
X
Y
Master-Slave Flip-flops
CADENCE CONFIDENTIAL 253
Cascading Domino
• For gates with all inputs coming from other domino gates, the
bottom NMOS transistor can be eliminated
– Why? All inputs will be ‗0‘ during precharge and can only
transition from ‗0‘ to ‗1‘ during evaluate
– Results in increased performance due to decreased stack height
– Precharge now depends on input precharge time
CADENCE CONFIDENTIAL 254
Dynamic Logic Power
• Power depends upon switching activity
– Switching activity depends upon the probability of a ‗1‘ input


– Effective capacitance is doubled when the gate evaluates because the
gate must later precharge
– Frequency must be multiplied by the probability that an evaluation will
occur
• Power is usually higher except for very high activity gates
f V C V C
T
P
DD load DD load avg
2 2
1
= =
CADENCE CONFIDENTIAL 255 CADENCE DESIGN SYSTEMS, INC.





SESSION 6: SCALING of MOS Lecture 1
•Velocity saturation
•Mobility degradation
•Threshold voltage variation
•DIBL
•Channel length modulation
•Scaling
•Constant field, constant voltage, Effects of scaling
CADENCE CONFIDENTIAL 256
Secondary effects
• Short-channel effects:
– Short channel device has channel length comparable to depth of
drain and source junctions and depletion width
– Causes threshold voltage and I/V curve variations
• Narrow-channel effects:
– Narrow channel device has small channel width
• Sub-threshold conduction (leakage current)

CADENCE CONFIDENTIAL 257
Short-channel effects
• Short-channel device: channel length is comparable to depth of
drain and source junctions and depletion width
– In general, visible when L ~ 1um and below

• Short-channel effects:
– Carrier velocity saturation
– Mobility degradation
– Threshold voltage variation
CADENCE CONFIDENTIAL 258
Carrier velocity saturation
• Electric field E
y
exists along channel
– As channel length is reduced, electric field increases (if voltage is
constant)
• Electron drift velocity v
d
is proportional to electric field
– only for small field values
– for large electric field, velocity saturates
source
drain
V
ds

0
V
gs

N
+
N
+

P
L
CADENCE CONFIDENTIAL 259
Carrier velocity saturation
• Effect of velocity saturation:
– Current saturates before ―saturation region‖
– V
DSAT
= voltage at which saturation occurs
– Drain current is reduced:

DSAT ox d D
V C sat v W sat I - - - = ) ( ) (
(no longer quadratic function of V
GS
)

– Saturation region is extended:
V
DSAT
< V
GS
-V
T


CADENCE CONFIDENTIAL 260
Mobility degradation
• MOS I/V equations depend on surface mobility µ
n
(or µ
p
)
• In short-channel devices, µ
n
and µ
p
are not constant
– As vertical electric field E
x
increases, surface mobility decreases



– µ0 = low-field mobility, q is empirical constant
– As V
GS
increases, surface mobility decreases

( )
T GS
V V ÷ +
=
q
µ
µ
1
0
CADENCE CONFIDENTIAL 261
Threshold voltage variation
• Until now, threshold voltage assumed constant
– V
T
changed only by substrate bias V
SB
• In threshold voltage equations, channel depletion region
assumed to be created by gate voltage only
• Depletion regions around source and drain neglected: valid if
channel length is much larger than depletion region depths
• In short-channel devices, depletion regions from drain and source
extend into channel
CADENCE CONFIDENTIAL 262
Threshold voltage variation
Short-channel effects cause threshold voltage variation:

• V
T
rolloff
– As channel length L decreases, threshold voltage decreases
• Drain-induced barrier lowering
– As drain voltage V
DS
increases, threshold voltage decreases
• Hot-carrier effect
– Threshold voltages drift over time
CADENCE CONFIDENTIAL 263
Source
depletion
region
Drain
depletion
region
Gate-induced
depletion region
Threshold voltage variation
• Even with V
GS
=0, part of channel is already depleted
• Bulk depletion charge is smaller in short-channel device → V
T
is
smaller
N+
source
N+
drain
CADENCE CONFIDENTIAL 264
• Change in V
T0
:
– x
dS
, x
dD
: depth of depletion regions at S, D
– x
j
: junction depth
(
(
¸
(

¸

|
|
.
|

\
|
÷ + +
|
|
.
|

\
|
÷ + - = A 1
2
1 1
2
1
2
2 2
1
0
j
dD
j
dS
j
F A Si
ox
T
x
x
x
x
L
x
N q
C
V | c
• AV
T0
is proportional to (x
j
/L)
– For short channel lengths, AV
T0
is large
– For large channel lengths, term approaches 0
Threshold voltage variation
CADENCE CONFIDENTIAL 265
Threshold voltage variations
Graphically: V
T0
versus channel length L
V
T0

L
Long-channel V
T

L
nom
V
T
Roll-off:
V
T
decreases rapidly with channel length
CADENCE CONFIDENTIAL 266
DIBL
• Drain-induced barrier lowering (DIBL)
– Drain voltage V
DS
causes change in threshold voltage
– As V
DS
is increased, threshold voltage decreases
• Cause: depletion region around drain
– Depletion region depth around drain depends on drain voltage
– As V
DS
is increased, drain depletion region gets deeper and
extends further into channel
– For very large V
DS
, source and drain depletion regions can
meet → punch-through!
• Issue: results in uncertainty in circuit design

CADENCE CONFIDENTIAL 267
Threshold voltage variation
• Hot-carrier effect
– increased electric fields causes increased electron velocity
– high-energy electrons can tunnel into gate oxide
– This changes the threshold voltage (increases V
T
for NMOS)
– Can lead to long-term reliability problems
CADENCE CONFIDENTIAL 268
Threshold voltage variation
• Hot electrons
– High-velocity electrons can also impact the drain, dislodging holes
– Holes are swept towards negatively-charged substrate → cause
substrate current
– Called impact ionization
– This is another factor which limits the process scaling → voltage
must scale down as length scales
CADENCE CONFIDENTIAL 269
Threshold voltage variations
• Summary of threshold variations in short-channel devices
– V
T
rolloff: threshold voltage reduces as channel length L
reduces
– DIBL: threshold voltage reduces as V
DS
increases
– Hot-carrier effect: threshold voltage drifts over time as
electrons tunnel into oxide
CADENCE CONFIDENTIAL 270
Short-channel summary
• Both devices have same effective W/L ratio → I/V curves should be
similar
• Short-channel device has ~ 40% less current at high V
DS

• Note linear dependence on V
GS
in short-channel device

Long-channel Short-channel
CADENCE CONFIDENTIAL 271
Sub-threshold conduction
• When V
GS
< V
T
, transistor is ―off‖
– However, small drain current I
D
still flows
– Called subthreshold leakage current
• Model for subthreshold current:



– Increases as V
GS
increases (potential barrier lowered)
– Increases as V
DS
increases (DIBL)

( )
DS GS
BV AV
kT
q
S D
We I ld subthresho I
+
= ) (
CADENCE CONFIDENTIAL 272
Subthreshold conduction
• Exponential relationship to V
GS
log I
DS
(sub)
V
GS
V
T
subthreshold slope
(mV/decade of current)
• Subthreshold slope:
• Shift in V
GS
required to reduce leakage by factor of
10
• Typical values: 80-120 mV/decade
CADENCE CONFIDENTIAL 273
Gate leakage
• Another source of leakage current is gate leakage (Fowler-Nordheim
Tunneling)
• For very thin gate oxide, electrons can tunnel through the gate oxide,
resulting in current from gate to drain or source
• Equation for gate leakage current:
ox
E
E
ox FN
e WLE C I
0
2
1
÷
=
E
0
, C
1
constants
E
ox
= electric field across oxide
• I
FN
proportional to area of gate
• Limits scaling of gate oxide
CADENCE CONFIDENTIAL 274
Leakage
• Effect of leakage current
– ―Wasted‖ power: power consumed even when circuit is inactive
– Leakage power raises temperature of chip
– Can cause functionality problem in some circuits: memory,
dynamic logic, etc.
• Reducing transistor leakage
– Long-channel devices
– Small drain voltage
– Large threshold voltage V
T

CADENCE CONFIDENTIAL 275
Leakage
• Leakage vs. performance tradeoff:
– For high-speed, need small V
T
and L
– For low leakage, need high V
T
and large L
• Process scaling
– V
T
reduces with each new process (historically)
– Leakage increases ~10X!
• One solution: dual-V
T
process
– Low-V
T
transistors: use in critical paths for high speed
– High-V
T
transistors: use to reduce power
CADENCE CONFIDENTIAL 276
Channel Length Modulation
• In saturation, pinch-off point moves
– As V
DS
is increased, pinch-off point moves closer to source
– Effective channel length becomes shorter
– Current increases due to shorter channel
( ) ( )
DS TN GS ox n D
V V V
L
W
C I
L L L
ì µ + ÷ =
A ÷ =
1
2
2
1
'
ì = channel length modulation coefficient
CADENCE CONFIDENTIAL 277
SPICE Model Equations
• SPICE Level 1
– Approximations (GCA) from SESSION 1
– Useful for hand calculations
• SPICE Level 2
– Variation of mobility with electric field
– Variation of channel length in saturation (more accurate)
– Carrier velocity saturation
– Subthreshold conduction
• SPICE Level 3
– Mostly empirical
– Accurate to 2µm
CADENCE CONFIDENTIAL 278
• Improvement in CMOS process technology. Reduction in device
dimensions, improved circuit performance
• First-order constant field scaling
Apply a dimensionless factor o > 1 to all dimensions, device
voltages and concentration densities
• Constant voltage scaling
VDD is kept constant, process is scaled
• Lateral scaling
Only the gate length is scaled (―gate shrink‖)
Scaling
CADENCE CONFIDENTIAL 279
MOSFET Scaling
• Constant Voltage
– Traditional, board-level compatible
• Constant Field
– Ideal, helps reliability
• Hybrid
– practical
CADENCE CONFIDENTIAL 280
Scaling
• Scaling has a threefold objective:
– Reduce the gate delay by 30% (43% increase in frequency)
– Double the transistor density
– Saving 50% of power (at 43% increase in frequency)
• How is scaling achieved?
– All the device dimensions (lateral and vertical) are reduced by 1/o
– Concentration densities are increased by o
– Device voltages reduced by 1/o (not in all scaling methods)
– Typically 1/o = 0.7 (30% reduction in the dimensions)
CADENCE CONFIDENTIAL 281
Constant Field
Before Scaling After Scaling
Length L L/s
Width W W/s
Oxide Thickness t
ox
t
ox
/s
Diffusion/Junction Depth X
j
X
j
/s
Supply Voltage V
DD
V
DD
/s
Threshold Voltage V
T
V
T
/s
Doping Densities N
A
,N
D
sN
A
,sN
D

dx E
}
=
c
µ
dx E V
}
=
CADENCE CONFIDENTIAL 282
Constant Voltage
Before Scaling After Scaling
Length L L/s
Width W W/s
Oxide Thickness t
ox
t
ox
/s
Diffusion/Junction Depth X
j
X
j
/s
Supply Voltage V
DD
V
DD

Threshold Voltage V
T
V
T

Doping Densities N
A
,N
D
s
2
N
A
,s
2
N
D

dx E
}
=
c
µ
dx E V
}
=
CADENCE CONFIDENTIAL 283
Scaling: Capacitance Effects
• Constant Field



• Constant Voltage

ox scaled ox
sC C =
,
s
C
C
g
scaled g
=
,
ox scaled ox
sC C =
,
s
C
C
g
scaled g
=
,
CADENCE CONFIDENTIAL 284
Scaling: Current Effects
• Constant Field


Current density increases by s

• Constant Voltage



Current density increases by s
3

s
I
s
V
s
V
s L
s W
s t
I
D
T GS
ox
ox
scaled D
=
|
.
|

\
|
÷ =
2
,
2
µc
( )
D T GS
ox
ox
scaled D
sI V V
s L
s W
s t
I = ÷ =
2
,
2
µc
CADENCE CONFIDENTIAL 285
Scaling: Power Effects
• Constant Field



• Constant Voltage

2
s
P
s
I
s
V
P
D DS
scaled
= =
( )( )
P
s L s W
s P
A
P
scaled
scaled
= =
2
sP sI V P
D DS scaled
= =
( )( )
P s
s L s W
sP
A
P
scaled
scaled
3
= =
CADENCE CONFIDENTIAL 286
Scaling: Performance Effects
• Constant Field



• Constant Voltage

( )( )
s s I
s V s C
scaled
t
t = =
2
) / (
s sI
V s C
scaled
t
t = =
CADENCE CONFIDENTIAL 287
Technology scaling
Some consequencies 30% scaling in the constant field regime (s =
1.43, 1/s = 0.7):
• Device/die area:
W × L ÷ (1/s)
2
= 0.49
– In practice, microprocessor die size grows about 25% per technology
generation! This is a result of added functionality.
• Transistor density:
(unit area) /(W × L) ÷ s
2
= 2.04
– In practice, memory density has been scaling as expected. (not true for
microprocessors…)
CADENCE CONFIDENTIAL 288
Technology scaling
• Gate capacitance:
W × L / t
ox
÷ 1/s = 0.7
• Drain current:
(W/L) × (V
2
/t
ox
) ÷ 1/s = 0.7
• Gate delay:
(C × V) / I ÷ 1/s = 0.7
Frequency ÷ s = 1.43
– In practice, microprocessor frequency has doubled every technology
generation (2 to 3 years)! This faster increase rate is due to two factors:
– the number of gate delays in a clock cycle decreases with time (the designs
become highly pipelined)
– advanced circuit techniques reduce the average gate delay beyond 30% per
generation.
CADENCE CONFIDENTIAL 289
Technology scaling
• Power:
C × V
2
× f ÷ (1/s)
2
= 0.49
• Power density:
1/t
ox
× V
2
× f ÷ 1
• Active capacitance/unit-area:
Power dissipation is a function of the operation
frequency, the power supply voltage and of the circuit
size (number of devices).

CADENCE CONFIDENTIAL 290
Technology scaling
• Interconnects scaling:
– Higher densities are only possible if the interconnects also scale.

– Reduced width ÷ increased resistance

– Denser interconnects ÷ higher capacitance
CADENCE CONFIDENTIAL 291
Technology scaling
– To account for increased parasitics and integration
complexity
– more interconnection layers are added:
– thinner and tighter layers ÷ local interconnections
– thicker and sparser layers ÷ global
interconnections and power
Interconnects are scaling as expected
CADENCE CONFIDENTIAL 292 CADENCE DESIGN SYSTEMS, INC.





SESSION 7: CMOS Technology Lecture 1
•Photolithography
•CMOS Fabrication Sequence
•Latch up
CADENCE CONFIDENTIAL 293
Lithography
Lithography: process used to transfer patterns to each layer of the IC
Lithography sequence steps:
• Designer:
– Drawing the layer patterns on a layout editor
• Silicon Foundry:
– Masks generation from the layer patterns in the design data base
– Printing: transfer the mask pattern to the wafer surface
– Process the wafer to physically pattern each layer of the IC

CADENCE CONFIDENTIAL 294
Lithography
Basic sequence
• The surface to be patterned is:
– spin-coated with photoresist
– the photoresist is dehydrated in an oven (photo
resist: light-sensitive organic polymer)
• The photoresist is exposed to ultra violet light:
– For a positive photoresist exposed areas
become soluble and non exposed areas remain
hard
• The soluble photoresist is chemically removed
(development).
– The patterned photoresist will now serve as an
etching mask for the SiO
2

1. Photoresist coating
SiO
2
Photoresist
Substrate
3. Development
Substrate
Substrate
Mask
Ultra violet light
Opaque
Exposed
Unexposed
2. Exposure
CADENCE CONFIDENTIAL 295
Lithography
• The SiO
2
is etched away leaving the
substrate exposed:
– the patterned resist is used as the etching
mask
• Ion Implantation:
– the substrate is subjected to highly
energized donor or acceptor atoms
– The atoms impinge on the surface and
travel below it
– The patterned silicon SiO
2
serves as an
implantation mask
• The doping is further driven into the bulk
by a thermal cycle

4. Etching
Substrate
Substrate
5. Ion implant
Substrate
6. After doping
diffusion
CADENCE CONFIDENTIAL 296
Lithography
• The lithographic sequence is repeated for each physical layer
used to construct the IC. The sequence is always the same:
– Photoresist application
– Printing (exposure)
– Development
– Etching
CADENCE CONFIDENTIAL 297
Lithography
Patterning a layer above the silicon surface
Substrate
SiO
2
Polysilicon
1. Polysilicon deposition
2. Photoresist coating
photoresist
Substrate
Substrate
3. Exposure
UV light
Substrate
4. Photoresist developmen t
Substrate
5. Polysilicon etching
Substrate
6. Final polysilicon pattern
CADENCE CONFIDENTIAL 298
Lithography
• Etching:
– Process of removing unprotected
material
– Etching occurs in all directions
– Horizontal etching causes an under
cut
– ―preferential‖ etching can be used to
minimize the undercut
• Etching techniques:
– Wet etching: uses chemicals to
remove the unprotected materials
– Dry or plasma etching: uses ionized
gases rendered chemically active by
an rf-generated plasma
anisotropic etch (ideal)
resist
layer 1
layer 2
resist
layer 1
layer 2
isotropic etch
undercut
resist
layer 1
layer 2
preferential etch
undercut
CADENCE CONFIDENTIAL 299
CMOS fabrication sequence
0. Start:
– For an n-well process the starting point is a p-type silicon wafer:
– wafer: typically 75 to 230mm in diameter and less than 1mm thick
1. Epitaxial growth:
– A single p-type single crystal film is grown on the surface of the
wafer by:
– subjecting the wafer to high temperature and a source of
dopant material
– The epi layer is used as the base layer to build the devices
P+ -type wafer
p-epitaxial layer
Diameter = 75 to 230mm
< 1mm
CADENCE CONFIDENTIAL 300
CMOS fabrication sequence
2. N-well Formation:
– PMOS transistors are fabricated in n-well regions
– The first mask defines the n-well regions
– N-well‘s are formed by ion implantation or deposition and diffusion
– Lateral diffusion limits the proximity between structures
– Ion implantation results in shallower wells compatible with today‘s fine-
line processes
p-type epitaxial layer
n-well
Lateral
diffusion
Physical structure cross section Mask (top view)
n-well mask
CADENCE CONFIDENTIAL 301
CMOS fabrication sequence
3. Active area definition:
– Active area:
– planar section of the surface where transistors are build
– defines the gate region (thin oxide)
– defines the n+ or p+ regions
– A thin layer of SiO
2
is grown over the active region and covered with
silicon nitride

n-well
Silicon Nitride
Stress-relief oxide
p-type
Active mask
CADENCE CONFIDENTIAL 302
CMOS fabrication sequence
4. Isolation:
– Parasitic (unwanted) FET‘s exist between unrelated transistors (Field
Oxide FET‘s)
– Source and drains are existing source and drains of wanted devices
– Gates are metal and polysilicon interconnects
– The threshold voltage of FOX FET‘s are higher than for normal FET‘s

p-substrate (bulk)
n+ n+
Parasitic FOX device
n+ n+
CADENCE CONFIDENTIAL 303
CMOS fabrication sequence
– FOX FET‘s threshold is made high by:
– introducing a channel-stop diffusion that raises the impurity concentration in
the substrate in areas where transistors are not required
– making the FOX thick
4.1 Channel-stop implant
– The silicon nitride (over n-active) and the photoresist (over n-well)
act as masks for the channel-stop implant

n-well
p-type
channel stop mask = ~(n-well mask)
resit
Implant (Boron)
p+ channel-stop implant
CADENCE CONFIDENTIAL 304
CMOS fabrication sequence
4.2 Local oxidation of silicon (LOCOS)
– The photoresist mask is removed
– The SiO
2
/SiN layers will now act as a masks
– The thick field oxide is then grown by:
– exposing the surface of the wafer to a flow of oxygen-rich gas
– The oxide grows in both the vertical and lateral directions
– This results in a active area smaller than patterned

n-well
p-type
Field oxide (FOX)
patterned active area
active area after LOCOS
CADENCE CONFIDENTIAL 305
CMOS fabrication sequence
• Silicon oxidation is obtained by:
– Heating the wafer in a oxidizing atmosphere:
– Wet oxidation: water vapor, T = 900 to 1000ºC (rapid process)
– Dry oxidation: Pure oxygen, T = 1200ºC (high temperature required to achieve an
acceptable growth rate)
• Oxidation consumes silicon
– SiO
2
has approximately twice the volume of silicon
– The FOX is recedes below the silicon surface by 0.46X
FOX

X
FOX
0.54 X
FOX
0.46 X
FOX
Silicon wafer
Silicon surface
Field oxide
CADENCE CONFIDENTIAL 306
CMOS fabrication sequence
5. Gate oxide growth
– The nitride and stress-relief oxide are removed
– The devices threshold voltage is adjusted by:
– adding charge at the silicon/oxide interface
– The well controlled gate oxide is grown with thickness t
ox

n-well
p-type
n-well
p-type
t
ox
t
ox
Gate oxide
CADENCE CONFIDENTIAL 307
CMOS fabrication sequence
6. Polysilicon deposition and patterning
– A layer of polysilicon is deposited over the entire wafer surface
– The polysilicon is then patterned by a lithography sequence
– All the MOSFET gates are defined in a single step
– The polysilicon gate can be doped (n+) while is being deposited to
lower its parasitic resistance (important in high speed fine line
processes)
n-well
p-type
Polysilicon gate
Polysilicon mask
CADENCE CONFIDENTIAL 308
CMOS fabrication sequence
7. PMOS formation
– Photoresist is patterned to cover all but the p+ regions
– A boron ion beam creates the p+ source and drain regions
– The polysilicon serves as a mask to the underlying channel
– This is called a self-aligned process
– It allows precise placement of the source and drain regions
– During this process the gate gets doped with p-type impurities
– Since the gate had been doped n-type during deposition, the final type (n or p) will
depend on which dopant is dominant
n-well
p-type
p+ implant (boron)
p+ mask
Photoresist
CADENCE CONFIDENTIAL 309
CMOS fabrication sequence
8. NMOS formation
– Photoresist is patterned to define the n+ regions
– Donors (arsenic or phosphorous) are ion-implanted to dope the n+
source and drain regions
– The process is self-aligned
– The gate is n-type doped
n-well
p-type
n+ implant (arsenic or phosphorous)
n+ mask
Photoresist
CADENCE CONFIDENTIAL 310
CMOS fabrication sequence
9. Annealing
– After the implants are completed a thermal annealing cycle is
executed
– This allows the impurities to diffuse further into the bulk
– After thermal annealing, it is important to keep the remaining
process steps at as low temperature as possible
n-well
p-type
n+
p+
CADENCE CONFIDENTIAL 311
CMOS fabrication sequence
10. Contact cuts
– The surface of the IC is covered by a layer of CVD oxide
– The oxide is deposited at low temperature (LTO) to avoid that
underlying doped regions will undergo diffusive spreading
– Contact cuts are defined by etching SiO
2
down to the surface to
be contacted
– These allow metal to contact diffusion and/or polysilicon regions
n-well
p-type
n+
p+
Contact mask
CADENCE CONFIDENTIAL 312
CMOS fabrication sequence
11. Metal 1
– A first level of metallization is applied to the wafer surface and
selectively etched to produce the interconnects
n-well
p-type
n+
p+
metal 1 mask
metal 1
CADENCE CONFIDENTIAL 313
CMOS fabrication sequence
12. Metal 2
– Another layer of LTO CVD oxide is added
– Via openings are created
– Metal 2 is deposited and patterned
n-well
p-type
n+
p+
Via
metal 1
metal 2
CADENCE CONFIDENTIAL 314
CMOS fabrication sequence
13. Over glass and pad openings
– A protective layer is added over the surface:
– The protective layer consists of:
– A layer of SiO
2

– Followed by a layer of silicon nitride
– The SiN layer acts as a diffusion barrier against contaminants
(passivation)
– Finally, contact cuts are etched, over metal 2, on the passivation
to allow for wire bonding.
CADENCE CONFIDENTIAL 315
Yield


• The yield is influenced by:
– the technology
– the chip area
– the layout
• Scribe cut and packaging also
contribute to the final yield
• Yield can be approximated by:

A - chip area (cm
2
)
D - defect density (defects/cm
2
)
Y
number
=
of good chips on wafer
total number of chips
Y e
A D
=
÷ ·
0 2 4 6 8 10
10
100
Y
i
e
l
d

(
%
)
Yield tendency
20
40
60
80
1.0 defects/cm
2

2.5 defects/cm
2
5.0 defects/cm
2

Chip edge ( area in mm)
CADENCE CONFIDENTIAL 316
Other processes
• P-well process
– NMOS devices are build on a implanted p-well
– PMOS devices are build on the substrate
– P-well process moderates the difference between the p- and the
n-transistors since the P devices reside in the native substrate
– Advantages: better balance between p- and n-transistors

p-well
n-type
n+
p+
CADENCE CONFIDENTIAL 317
Other processes
• Twin-well process
– n+ or p+ substrate plus a lightly doped epi-layer (latchup
prevention)
– wells for the n- and p-transistors
– Advantages, simultaneous optimization of p- and n-transistors:
– threshold voltages
– body effect
– gain

p-well
n+ substrate
n+
p+
n-well
epitaxial layer
CADENCE CONFIDENTIAL 318
Other processes
• Silicon On Insulator (SOI)
– Islands of silicon on an insulator form the transistors
• Advantages:
– No wells ¬ denser transistor structures
– Lower substrate capacitances
n+ p- n+
S
D
G
p+ n- p+
S
D
G
sapphire (insulator)
polysilicon
thinoxide
SiO
2
phosphorus glass or SiO
2
CADENCE CONFIDENTIAL 319
Other processes
– Very low leakage currents
– No FOX FET exists between unrelated devices
– No latchup
– No body-effect:
– Radiation tolerance
• Disadvantages:
– Absence of substrate diodes (hard to implement protection
circuits)
– Higher number of substrate defects ¬ lower gain devices
– More expensive processing

CADENCE CONFIDENTIAL 320
Advanced CMOS processes
• Shallow trench isolation
• n+ and p+-doped polysilicon gates (low threshold)
• source-drain extensions LDD (hot-electron effects)
• Self-aligned silicide (spacers)
• Non-uniform channel doping (short-channel effects)
n-well
p+ p+
n+ n+
p-doping n-doping
Silicide
Oxide spacer
n+ poly p+ poly
Shallow-trench isolation
p-type substrate
Source-drain
extension
CADENCE CONFIDENTIAL 321
Process enhancements
• Up to six metal levels in modern processes
• Copper for metal levels 2 and higher
• Stacked contacts and vias
• Chemical Metal Polishing for technologies with several metal levels
• For analogue applications some processes offer:
– capacitors
– resistors
– bipolar transistors (BiCMOS)

CADENCE CONFIDENTIAL 322
Latchup
• CMOS process contains parasitic bipolar transistors
• Under certain conditions, these parasitic transistors can turn on,
shorting power and ground rails and usually destroying the chip
→ latchup
• Avoiding latchup requires certain layout design rules, and careful
control of process
• Latchup was a major problem in early CMOS processes
• Now, latchup is mainly issue for I/O circuits, with high current
demands and possibly noisy voltages
CADENCE CONFIDENTIAL 323
Latchup
• Current flowing in well or substrate can forward-bias bipolar transistor
• Positive feedback between transistors: when one turns on, V
dd
and Gnd are
connected
• Solution: reduce R
nwell
and R
psubs
: use many substrate taps in layout
• High-current circuits use guard rings
NMOS PMOS
substrate tap
n-well tap
CADENCE CONFIDENTIAL 324 CADENCE DESIGN SYSTEMS, INC.





SESSION 8: DESIGN RULES Lecture 1
•Eular graph
•Stick diagrams
•Design rules
•Layout example
CADENCE CONFIDENTIAL 325
Why we need design rules
• Masks are tooling for manufacturing.
• Manufacturing processes have inherent limitations in
accuracy.
• Design rules specify geometry of masks which will provide
reasonable yields.
• Design rules are determined by experience
CADENCE CONFIDENTIAL 326
Manufacturing problems
• Photoresist shrinkage, tearing.
• Variations in material deposition.
• Variations in temperature.
• Variations in oxide thickness.
• Impurities.
• Variations between lots.
• Variations across a wafer.
CADENCE CONFIDENTIAL 327
Transistor problems
• Variations in threshold voltage:
– oxide thickness;
– ion implantation;
– poly variations.
• Changes in source/drain diffusion overlap.
• Variations in substrate.
CADENCE CONFIDENTIAL 328
Wiring problems
• Diffusion: changes in doping -
variations in resistance, capacitance.
• Poly, metal: variations in height, width - variations
in resistance, capacitance.
• Shorts and opens.
CADENCE CONFIDENTIAL 329
Oxide problems
• Variations in height.
• Lack of planarity -> step coverage
metal 1
metal 2
metal 2
CADENCE CONFIDENTIAL 330
Via problems
• Via may not be cut all the way through.
• Undersize via has too much resistance.
• Via may be too large and create short.
CADENCE CONFIDENTIAL 331
Constraints on Layout
Resolution constraints
– What is the smallest width feature than can be printed
– What is the smallest spacing that will guarantee no shorts
– Depends on lithography and processing steps that follow
– Resolution often depends on the smoothness of the surface
– need to keep the image in focus, since depth of field is small
– Most modern processes are planarized, to keep surface flat
CADENCE CONFIDENTIAL 332
Constraints on Layout
– Alignment/overlap constraints
– Like printing a color picture, need to align layers to each other
– Need to choose which layer to align to
– That layer will have better registration than the others.
CADENCE CONFIDENTIAL 333
Design Rules
• Interface between designer and process engineer
• Guidelines for constructing process masks
• Unit dimension: Minimum line width
– scalable design rules: lambda parameter
– absolute dimensions (micron rules)
CADENCE CONFIDENTIAL 334
MOSIS SCMOS design rules
• Designed to scale across a wide range of technologies.
• Designed to support multiple vendors.
• Designed for educational use.
• Ergo, fairly conservative.
CADENCE CONFIDENTIAL 335
ì and design rules
• ì is the size of a minimum feature.
• Specifying ì particularizes the scalable rules.
• Parasitics are generally not specified in ì units.
CADENCE CONFIDENTIAL 336
Resolution design rules
• Minimum line-width:
– smallest dimension
permitted for any object in
the layout drawing (minimum
feature size)
• Minimum spacing:
– smallest distance permitted
between the edges of two
objects
• This rules originate from the
resolution of the optical printing
system, the etching process, or
the surface roughness
Minimum spacing
Minimum width
CADENCE CONFIDENTIAL 337
ì and design rules
• Contacts and vias:
– minimum size limited by the
lithography process
– large contacts can result in
cracks and voids
– Dimensions of contact cuts
are restricted to values that
can be reliably
manufactured
– A minimum distance
between the edge of the
oxide cut and the edge of
the patterned region must be
specified to allow for
misalignment tolerances
(registration errors)
n+
p
metal 1
n+ diffusion
metal 1
d
d
Contact size
Registration tolerance
Contact
x
2
n+ diffusion
metal 1
x
1
CADENCE CONFIDENTIAL 338
ì and design rules
• MOSFET rules
– n+ and p+ regions are formed
in two steps:
– the active area openings
allow the implants to
penetrate into the silicon
substrate
– the nselect or pselect
provide photoresist
openings over the active
areas to be implanted
– Since the formation of the
diffusions depend on the
overlap of two masks, the
nselect and pselect regions
must be larger than the
corresponding active areas to
allow for misalignments
Correct mask sizing
overlap
x
x
active
nselect
n+
p-substrate
Incorrect mask sizing
overlap
x
x
active
nselect
p-substrate
n+
CADENCE CONFIDENTIAL 339
ì and design rules
• Gate overhang:
– The gate must overlap the
active area by a minimum
amount
– This is done to ensure that
a misaligned gate will still
yield a structure with
separated drain and
source regions
• A modern process has may
hundreds of rules to be
verified
– Programs called Design
Rule Checkers assist the
designer in that task
gate overhang
no overhang
no overhang
and misalignment
Short circuit
CADENCE CONFIDENTIAL 340
CMOS Process Layers
Layer
Polysilicon
Metal1
Metal2
Contact To Poly
Contact To Diffusion
Via
Well (p,n)
Active Area (n+,p+)
Color Representation
Yellow
Green
Red
Blue
Magenta
Black
Black
Black
Select (p+,n+)
Green
CADENCE CONFIDENTIAL 341
Wires
metal 2
3
metal 1
3
pdiff/ndiff
3
poly
2
CADENCE CONFIDENTIAL 342
Intra-Layer Design Rules
Metal2
4
3
10
9
0
Well
Active
3
3
Polysilicon
2
2
Different Potential
Same Potential
Metal1
3
3
2
Contact
or Via
Select
2
or
6
2
Hole
CADENCE CONFIDENTIAL 343
Transistor Layout
2
3
1
3
2
5
CADENCE CONFIDENTIAL 344
Via’s and Contacts
• In SCMOS, the spacing from contacts is often slightly larger
than base material
– Poly contact to poly spacing is 3 ì
– Diffusion contact to diffusion is 4 ì
• This is done so the fabricator can make the surround of the
actual contact cut slightly larger than 1 ì, if needed
CADENCE CONFIDENTIAL 345
Via’s and Contacts
1
2
1
Via
Metal to
Poly Contact
Metal to
Active Contact
1
2
5
4
3 2
2
CADENCE CONFIDENTIAL 346
Select Layer
1
3 3
2
2
2
Well
Substrate
Select
3
5
CADENCE CONFIDENTIAL 347
CMOS Inverter Layout
A A’
n
p-substrate Field
Oxide
p
+
n
+
In
Out
GND V
DD
(a) Layout
(b) Cross-Section along A-A’
A
A’
CADENCE CONFIDENTIAL 348
Stick diagrams
• A stick diagram is a cartoon of a layout.
• Does show all components/vias (except possibly tub ties),
relative placement.
• Transistor 1 is to the right of transistor 2, and under transistor 3
• Does not show exact placement, transistor sizes, wire lengths,
wire widths, tub boundaries.
– Each wire is assigned a layer, and crossing wires must be on
different layers
CADENCE CONFIDENTIAL 349
Stick Diagrams
But
– Wires are drawn as stick figures with no width
– The size of the objects is not to scale
– If you forgot a wire you can squeeze it in between two other wires
– It does not have to be beautiful

It is faster to draw a stick diagram first with pencils and paper
CADENCE CONFIDENTIAL 350
Stick layers
metal 2
metal 1
poly
ndiff
pdiff
CADENCE CONFIDENTIAL 351
Dynamic latch stick diagram
VDD
in
VSS
phi
out
phi‟
CADENCE CONFIDENTIAL 352
Using the Design Rules
• SCMOS design rules are simplified, there are still a number of rules to
remember.
• Begin with a stick diagram of the cell you want to layout.
• Use a subset of the rules to estimate what the layout will look like,
• if it meets your standards-begin the actual layout.
• Good idea to have a plan on where things go before you start.
• Warning:
Layout is often (sometimes) fun to do- can be an infinite time sink
Can find a way to shrink the cell a few more microns.
CADENCE CONFIDENTIAL 353
Layout Issues
In CMOS there are two types of diffusion
• ndiff (green surrounded by hatched pwell)
– Poly crossing ndiff makes NMOS transistors
• pdiff (green surrounded by dotted nwell)
– Poly crossing pdiff makes PMOS transistors
Be careful, ndiff and pdiff are different
• Can’t directly connect ndiff to pdiff
– Must connect ndiff to metal and then metal to pdiff
• Can’t get ndiff too close to pdiff because of wells
– Large spacing rule between ndiff and pdiff
– Means you need to group NMOS devices together and PMOS devices together
CADENCE CONFIDENTIAL 354
Basic Layout Planning
Simple guidelines to CMOS layouts
• You need to route power and ground. (in metal)
– No one will auto connect it for you.
• Keep NMOS devices near NMOS devices and PMOS devices near PMOS
devices.
– So NMOS usually are placed near Gnd, and PMOS near Vdd You need
to route power and ground. (in metal)
– No one will auto connect it for you.
• Run poly vertically and diffusion horizontally, with metal1 horizontal (or the
reverse, just keep them orthogonal)
– Good default layout plan
CADENCE CONFIDENTIAL 355
Basic Layout Planning
Simple guidelines to CMOS layouts
• Keep diffusion wires as short as possible (just connect to transistor)
• All long wires (wire that go outside a cell, for example) should be in
either m1 or m2.
• Try to design/layout as little stuff as possible (use repetition/tools)
– Critical issue
CADENCE CONFIDENTIAL 356
Typical Cell Layout Plan
• The Parity
(note: no PMOS and no Vdd Gnd) (very unusual)



• CMOS Inverter/Buffer
Even
Odd
A A_b
Even Out
Odd Out
A
A_b
Vdd
Gnd
CADENCE CONFIDENTIAL 357
Estimating Area from Sticks
• Draw stick diagram
• Find the critical length path in X and in Y
• Count the number of contacted pitches
– If transistors are not minimum width, remember to take that into account
• If you not happy with the answer, goto step 1 and try again.
– Else you are done, and you can try to layout the cell.
• May miss the real critical length path
• Will get better at seeing the critical path as you do more layout.
CADENCE CONFIDENTIAL 358
CMOS gate layout
• Goal: minimum area
• Method
– Minimize diffusion breaks (reduces capacitance on internal nodes)
– Align transistors with common gates above each other in layout
(minimizes poly length)
– Group PMOS and NMOS transistors together
• Approach:
– Use Euler path method to find ordering of transistors in layout
CADENCE CONFIDENTIAL 359
Layout: Euler path method
• Goal: layout without diffusion breaks
• Method for finding ordering of transistors in layout → Euler
path
– Euler path → path through a graph that traverses each edge
only once
– Find common Euler path in pullup and pulldown graph
– This gives the ordering of inputs in the layout
CADENCE CONFIDENTIAL 360
Euler path method
• Example: complex CMOS gate
A
B
C
D
E
A
D
C
E
B
NMOS network PMOS network
Euler path: B→A→C→E→D Euler path: B→A→C→E→D
Common Euler path!
gnd
F
F
Vdd
CADENCE CONFIDENTIAL 361
Layout: Euler path method
A
B
C
D E
C E
D
B A
Euler path: B→A→C→E→D
B A C E D
V
DD
Gnd
F
F
1. Order transistors gates according to
Euler path
2. Connect V
DD
and Gnd
3. Make other connections according
to circuit diagram
CADENCE CONFIDENTIAL 362
GND
x
a
b
c
d
V
DD x
GND
x
a
b
c
d
V
DD x
(a) Logic graphs for (ab+cd)
(b) Euler Paths {a b c d}
a c d
x
V
DD
GND
(c) stick diagram for ordering {a b c d}
b
Example: x = (ab+cd)’
CADENCE CONFIDENTIAL 363
CMOS layout styles
• Full-custom
– Design broken into complex logic blocks
– Each block is laid out “by hand”
– Limited re-usability
• Standard cell
– Design broken into gates, either by logic designer or automated
synthesis tool
– Library of standard cells created
– Correct cells chosen from library, connected by layout designer or
place and route tool
CADENCE CONFIDENTIAL 364
Standard cells
• Example standard cell gates:
– inverters, buffers, XOR gates
– 2,3,4-input NAND, NOR
– And-Or-Invert (AOI) gates
– Or-And-Invert (OAI) gates
– Latches, flip-flops, etc
• Multiple versions of each gate:
– Designed for different output loads
• Detailed specifications
– Delays for each input combination

CADENCE CONFIDENTIAL 365



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