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**Presented by : Indranil Nandy MTech, Roll : 06CS6010 Under the guidance of : Prof. I. Sengupta
**

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What will be the difficulties when we will try to build classical computers (Turing machines) on the atomi c scal e? One of the toughest problems to scale down computers is the di ssi pa ted hea t tha t is di f fi cul t to r emo ve. Physical limitations placed on computation by hea t di ssi pa tion wer e stud ied for m any yea r s (Landauer , 1961) .

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**Typical Computer performs Irreversible operations
**

The usual digital computer program frequently performs operations that seem to throw away information about the computer's history, leaving the machine in a state whose immediate predecessor is ambiguous. Such operations include erasure or overwriting of data, and entry into a portion of the program addressed by several different transfer instructions. In other words, the typical computer is logically irreversible -its transition function (the partial function that maps each whole-machine state onto its successor, if the state has a successor) lacks a single-valued inverse.

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**Heat dissipation due to irreversibility
**

-R. Launder : “Fundamental Physical Limitations of the computational Process (1985)”

Landauer showed that whenever a physical computer throws away information about its previous state it must generate a corresponding amount of entropy. Therefore, a computer must dissipate at least kT ln 2 of energy (about 3 ×10-21 joule at room temperature) for each bit of information it erases where -k is Boltzmann’ constant and -T is the temperature of the system

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Reversible Logic

Bennett showed that for power not be dissipated in the circuit it is necessary that arbitrary circuit can . be built fromreversible gates

-Bennett (1973)

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**An irreversible computer can always be made reversible
**

– Logical Reversibility of Computation : Bennett (1973)

Bennett showed : An irreversible computer can always be made reversible by having it save all the information it would otherwise throw away. For example. the machine might be given an extra tape (initially blank) on which it could record each operation as it was being performed The preceding state would be uniquely determined by the present state and the last record on the tape.

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Lead to Reversible Logic Gate & Circuit Tomasso Toffoli, 1980: There exists a reversible gate which could play a role of a universal gate for reversible circuits. Bennett’s Theorem and Tomasso Toffoli’s proof both simultaneously have lead to the exploration in the field of Reversible Logic Gates and Circuits.

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**Conditions for reversibility
**

Two conditions must be satisfied for reversible computation The first Condition : for any deterministic device to be reversible its input and output must be uniquely retrievable from each other. - this is called logical reversibility. The second Condition : the device can actually run backwards, i.e., in another term it can be said that each operation converts no energy to heat and produces no entropy. - this is called physical reversibility. - Second Law of Thermodynamics guarantees that no heat is dissipated.

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Definitions

Reversible Gate : A gate is reversible if the (Boolean) function it computes is bijective. If arbitrary signals are allowed on the inputs, a necessary condition for reversibility is that the gate has the same number of input and output wires. If it has k input and output wires, it is called a k×k gate, or a gate on k wires To be explicit, there must exist one-to one mapping between vectors of inputs and outputs; thus the vector of input states can be always reconstructed from the vector of output states

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**Reversible Gate (contd.)
**

In a k-output the output permutation 0 to 2k-1. reversible gate vectors are a of the numbers

Reversible gates are balanced, i.e. the outputs are 1s for exactly half of the inputs. The number of inputs/outputs is called the width of the gate, i.e., the width of a kinput gate is k.

Fig. 1 : Toffoli’s Gate – a reversible gate

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Toffoli’s Gate

a 0 0 0 0 1 From the truth table of Toffoli’s gate .it is clear that it is a reversible gate There exists a one-to-one mapping from the input vectors to the output vectors. More over, the output is .balanced 1 1 1 b 0 0 1 1 0 0 1 1 c 0 1 0 1 0 1 0 1 x 0 0 0 0 1 1 1 1 y 0 0 1 1 0 0 1 1 z 0 1 0 1 0 1 1 0

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Definition :

K-CNOT : A k-CNOT is a (k+1)×(k+1) gate. It leaves the first k inputs unchanged, and inverts the last iff all others are 1. The unchanged lines are referred to as control lines. Clearly the k-CNOT gates are all reversible. The first three of these have special names. In the next slides we will discuss the special cases for k=0,1 and 2 as well as some other

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**Some special irreversible gates : (K = 0,1,2)
**

K=0: The 0-CNOT is just an inverter or NOT gate, and is denoted by N. It performs the operation (x) → (x XOR 1). K=1: The 1-CNOT, performs the operation (y,x) →(y,x XOR y). It is referred as a controlled-NOT or CNOT or C. K=2: The 2-CNOT is normally called a TOFFOLI (T) gate. It performs the operation (z,y,x) → (z,y,x XOR yz). SWAP Gate : We will also be using another reversible gate, called the SWAP (S) gate. It is a 2×2 gate which exchanges the inputs; that is, (x,y) → (y,x).

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Fredkin’s Gate :

output lines corresponding to a, b and c are x, y and z respectively. a 0 0 0 0 1 1 From the truth table of Fredkin’s gate .it is clear that it is a reversible gate There exists a one-to-one mapping from the input vectors to the output vectors. More over, the output is .balanced 1 1 b 0 0 1 1 0 0 1 1 c 0 1 0 1 0 1 0 1 x 0 0 0 0 1 1 1 1 y 0 1 0 1 0 0 1 1 z 0 0 1 1 0 1 0 1

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**Fredkin’s Gate (contd.) :
**

The functions computed by the outputs of Fredkin’s Gate can be interpreted as follows : X=a Y = if a then c else b Z = if a then b else c Every boolean function can be interpreted by 3x3 Fredkin’s gate (shown in the next slide).

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Different operations simulated by Fredkin’s Gate :

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Definition :

Reversible Logic Circuit : A well-formed reversible logic circuit is an acyclic combinational logic circuit in which all gates are reversible, and are interconnected without fanout. As with reversible gates, a reversible circuit has the same number of input and output wires. We will call a reversible circuit with n inputs an n×n circuit, or a circuit on n wires. We draw reversible circuits as arrays of horizontal lines representing wires. Gates are represented by verticallyoriented symbols. (Figure in the next slide)

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How to represent a reversible circuit truth table?

in the above Figure, we see a reversible circuit drawn in the notation introduced by Feynman. The symbols represent inverters and the • symbols represent controls. A vertical line connecting a control to an inverter means that the inverter is only applied if the wire on which the control is set carries a 1 signal. Thus, the gates used are, from left to right, TOFFOLI, NOT, TOFFOLI, and NOT. 18

**How to represent a reversible circuit truth table? (contd.)
**

Since we will be dealing only with bijective functions, i.e., permutations, we represent them using the cycle notation where a permutation is represented by disjoint cycles of variables. For example, the truth table in the previous Figure is represented by (2,3)(6,7) because the corresponding function swaps 010 (2) and 011 (3), and 110 (6) and 111 (7). The set of all permutations of n indices is denoted Sn, so the set of bijective functions with n binary inputs is S2n . We will call (2,3)(6,7) CNT-constructible since it can be computed by a circuit with gates from the CNT gate library

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**How to represent a reversible circuit truth table? (contd.)
**

Let us consider another example. See the truth table of a reversible logic gate. Then from the previous discussion, we can represent the truth table as the following disjoint cycle of variables : (2,4),(3,6,5).

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How to encode a reversible circuit?

To encode the circuit in the above figure, we number wires top-down from 0 to 3. Then the gates can be written as following : T(2,3;1)T(0,1;3)C(3;2)C(1;2)C(3;0)T(0,2;1)N(2)

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More definitions :

Let, L be a (reversible) gate library. Then the following definitions are defined on gate library L. L-Circuit : An L-circuit is a circuit composed only of gates from L L-constructible : A permutation p Є S2n is L-constructible if it can be computed by an n×n L-circuit Equivalent Circuits : Pairs of circuits computing the same function are called Equivalent Circuits.

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Equivalence (contd.) :

Pairs of circuits computing the same function are very useful, since we can substitute one for the other. On the right, we see similarly that three C gates can be used to replace the S gate appearing in the middle circuit of Figure 3b. If allowed by the physical implementation, the S gate may itself be replaced with a wire swap. This, however, is not possible in some forms of quantum computation. Figure a therefore shows us that the C and S gates in the CNTS gate library can be removed without losing computational power. We will still use the CNTS gate library in synthesis to reduce gate counts and potentially speed up synthesis. This is motivated by the above Figure, which shows how to replace four gates with one C gate, and thus up to 12 gates with one S gate.

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Temporary Storage :

The top n−k lines transfer n−k signals, collectively designated Y, to the corresponding wires on the other side of the circuit. The signals Y are arbitrary, in the sense that the circuit K must assume nothing about them to make its computation. Therefore, the output on the bottom k wires must be only a function of their input values X and not of the “ancilla” bits Y, hence the bottom output is denoted f (X). While the signals Y must leave the circuit holding the same values they entered it with, their values may be changed during the computation as long as they are restored by the end. These wires usually serve as an essential workspace for computing f (X) and hence, is called Temporary Storage. An example of this can be found in the previous Figure a: the C gate on the right needs two wires, but if we simulate it with two N gates and two T gates, we need a third wire. The signal applied to the top wire emerges unaltered.

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**Universal Reversible Gate :
**

Let L be a reversible gate library. Then L is universal if for all k and all permutations p Є S2k , there exists some l such that some Lconstructible circuit computes p using l wires of temporary storage. The concept of universality differs in the reversible and irreversible cases in two important ways. First, we do not allow ourselves access to constant signals during the computation. Second, we synthesize whole permutations rather 25 than just functions with one output bit

**Reversible Logic Constraints
**

Some of the major problems in Reversible Logic are as follows : Feedback not allowed in some papers allowed under certain conditions Fan-out not allowed in some papers allowed in a limited way in a near-reversible circuit

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Testable Reversible Gate :

The currently available reversible gates can be used to implement arbitrary logic functions. Here three reversible logic gates are introduced: R1 and R2 that can be used in pairs to design testable reversible logic circuits, and R3 that is used to construct two pair two rail checker. The first gate R1 is used for implementing arbitrary functions while the second gate R2 is employed to incorporate on-line testability features into the circuit

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R1 & R2 : Truth Table

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Testable Reversible Gate : R3

The testability feature is not incorporated in gate R3, as it will be used as the basic block for implementing the two pair two-rail checker

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**R1 can implement all boolean functions :
**

R1 can transfer a signal at input a to output u by setting input c to 0

OR & XOR

XNOR & NAND

OR

AND

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**Testable Logic Block
**

A testable logic block can be formed by cascading R1 and R2 as shown in the following figure. In this configuration gate R2 is used to check on-line whether there is a fault in R1 or in itself. If R1 is fault free, its parity output q and the parity output s of R2 should be complementary, otherwise the presence of a fault is assumed

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**Two pair rail checker
**

A two pair two-rail checker constructed using gate R3 is shown in the Fig. It is composed of eight R3 gates. The error checking functions of the two pair rail checker are as follows: e1 = x0y1 + y0x1 e2 = x0x1 + y0y1 Where x0/y0 and x1/ y1 are complementary. The fault-free checker will produce complementary output at e1 and e2 if the inputs are complementary.

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Required features (for logic synthesis using reversible gate) :

A logic synthesis technique using reversible gate should have the following features : Use minimum number of gates Keep the length of cascading gates minimum Use minimum number of garbage outputs Use minimum input constants

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Observations

Every reversible gate can be described by a permutation. Every reversible circuit can be described by a permutation. Synthesis of a reversible circuit can be considered as decomposition of a permutation to a sequence of elementary permutations. Group Theory has been successfully used for designing cascades of reversible gates.

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Conclusion

Many modern computational problems are inherently reversible in nature, meaning that information present in the input must be conserved by the computation and be recoverable from the output. Some fields where such problems arise include cryptography, digital signal processing, and communications. Another novel computing technology that circumvents physical limits-quantum circuits - also requires complete reversibility. Quantum circuits and algorithms offer additional benefits in terms of asymptotic runtime

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References :

Logical Reversibility of Computation : C.H. Bennett (1973) Irreversibility and the Heat Generation in the Computing Process : R.

Landauer (1961)

Energy Cost of Information : Jacob D. Bekenstein (1981) Notes on Landauer’s Principle : Bennett (2006) Synthesis of Reversible Logic Gates : Shende, Prasad, Markov & Hayes Data Structures and Algorithms for simplifying Reversible Circuits : Shende,

Prasad, Patel, Markov & Hayes

Testable Reversible Logic Circuit Design : Parkerson, Vasudevan & Lala

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**Paper :Logical Reversibility of Computation -Bennett (1973)
**

The usual general-purpose computing automaton (e.g., a Turing machine) is logically irreversible - its transition function lacks a single-valued inverse. Here it is shown that such machines may be made logically reversible at every step, while retaining their simplicity and their ability to do general computations. To prove this, in this paper Bennett proved the following theorem: Theorem: For every standard one-tape Tuning machine S, there exists a three-tape reversible deterministic Turing machine R such that if I and P are strings on the alphabet of S, containing no embedded blanks, then S halts on I if and only if 38 R halts on (I: B: B), and S: I → P if and only if R: (I:

**Landauer’s Principle(1961) Paper : Irreversibility and the Heat Generation in the Computing Process
**

The information-bearing degrees of freedom (IBDF) of a computer interact with the thermal reservoir represented by the remaining degrees of freedom (NBDF : non-information-bearing degrees of freedom).

Landauer noted that the logical he noted that some of a computer’s degrees of state often evolves irreversibly,: This interaction plays two roles are used to encode the logical state of freedom with all, or acts as a sink for the energy dissipation involved in the two it more distinct logical First of the computation states having a single logicaldissipation has an unavoidable minimum computation. This energy successor arising from the fact that the computer performs irreversible

operations. Secondly, the interaction acts as a source of noise causing errors.

because Hamiltonian/unitary dynamics conserves (fine-grained) entropy, the entropy decrease of the IBDF during alogically irreversible operation must be compensated by an equal or greater entropy increase in the NIBDF and environment. This is Landauer’s principle. Typically the entropy increase takes the form of energy imported into the computer, converted to heat, and dissipated into the environment

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