MSC 8101 NETWORK DIGITAL SIGNAL PROCESSOR

MSC 8101 is logically divided into three logic block : an extended core, a serial interface unit and a communication processor module as shown below

 Extended core consist of SC140 DSP core 512 KB SRAM Enhanced Filter Coprocessor (EFCOP) for performing filtering function. HDI16 is a 16-bit parallel port for interfacing host processor. Used for data transfer between the host or DMA controller and the DSP. PIC (Program Interrupt Controller) processes all interrupt request and gives an alert to the core or

an external device, of an interrupt request.

SC 140 DSP CORE

 Consist of four data ALU, each contains a MultiplierAccumulator unit, a barrel shifter unit . The address generator register file, two arithmetic address unit (AAU) and bit mask unit (BMU) together is referred to as address generation unit (AGU). The program sequencer is attached to the unified data program memory space through a 128-bit program data bus and a 32-bit program address bus.

 The address generator register file is attached to memory via a 32-bit X address bus A and a 32-bit X address bus B which allow the two AAUs to generate addresses in parallel. The ALU register file is attached to memory through two 64-bit buses, the X data bus A and X data bus B. Width of instruction bus is 128-bit. With four data ALU unit it is possible to execute four multiply and accumulate (MAC) operation in a single clock cycle.

The data ALU register file consist of 16 40-bit data register.

 DMA controller is used for the transfer of data between the internal and external memory and also between internal and external peripherals without the involvement of SC140 DSP core. Communication processor module has a user programmable RISC processor with an I/O interface which enables direct connection to high speed backbone networks using protocols such as ATM (Asynchronous Transfer Mode), fast ethernet. Three full-duplex fast serial communication controllers (FCCs) support IEEE802.3 and Fast Ethernet protocols

 The EFCOP performs filtering operations such as echo cancellation. These filtering operations include both adaptive and non-adaptive FIR and IIR filtering with 32-bit precision (the EFCOP contains a 32-bit x 32-bit multiply unit and 72-bitaccumulator). Echo cancellation is required for VOIP (Voice over internet protocol). This protocol is used for achieving voice communication over internet.

 Five stage pipelining

 It includes a pre-fetch, where an address is generated for a program fetch and the fetch counter is incremented. Then the fetch, where the eight instruction words are read from memory.

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