JOURNAL OF COMPUTING, VOLUME 4, ISSUE 9, SEPTEMBER 2012, ISSN (Online) 2151-9617 https://sites.google.com/site/journalofcomputing WWW.JOURNALOFCOMPUTING.

ORG

78

Design, Analysis and Simulation of 7-T SRAM Memroy Cell

Amit Kumar, Sukhveer Singh
Abstract The increasing market of portable and battery powered electronic devices is creating demands for chips that consume the smallest possible amount of power in electronics devices. SRAM consists of almost 60% power dissipation of the total digital system [2] and no digital system gets complete without memories. This paper focuses on the power dissipation during the Write operation in six-T CMOS SRAM as well as read operation also. In this paper analysis is done 7-T SRAM cell which will includes one more extra transistor that will control the overall capacitances during the write and read operation and will optimize the total capacitance will result out the decrease in the power dissipation. Here in this paper we are targeting the short circuit power dissipation as well as switching power dissipation which is also known as dynamic power optimization. The circuit is characterized by using the 130nm technology [9] which is having a supply voltage 0f 1.5 volt. Index Terms Power dissipation, delay, memory, switching capacitance, frequency.

1 INTRODUCTION

ith the increasing level of device integration and the growth in complexity of electronic circuits, increasing the demand of portable electronics devices and also dependence on the battery operated devices motivating the VLSI designers to reduce the power dissipation of the VLSI circuits so that they can be used for the long time for the given battery supply. That is why reduction of power is the most often used measures of the efficiency of VLSI Circuits has come to the fore as a primary design goal and also it is an most important entity that designers wants to optimize. Also as high speed circuits dissipate large amounts of energy in a short amount of time, power minimization algorithms and techniques are strongly recommend by most of the companies in these circuits. With ever increasing operating frequency and processing capacity per chip [8], large currents have to be delivered and the heat due to large power consumption must be removed by proper cooling techniques. Battery life in portable electronic devices is limited. Low power design directly leads to prolonged operation time in these portable devices. The most important part of any digital circuits is memory and SRAM memories are always frequently access by processors of any digital system. The Basic SRAM cell consists of the 6-transistor which consist of six MOS transistor is shown in the fig-1 It shows all the control circuitry which is needed to operate the SRAM memory. Memory accesses include read and write operations. Because Memory reads occur more frequently than writes, the memory power dissipated in reading However, the write power is usually larger than the read power due to the large power dissipated in driving the cell bit-lines to full swing. The power dissipated in the write operations become significant. Therefore, in this paper we are concentrating on reducing the write power

in both the case write 0 and write 1. Because power dissipation [1] in CMOS SRAM memory is given

P = Vdd2 f Ct
Where, = switching activity Vdd = Voltage supply f = Frequency of the signal Ct = Total switching capacitance of the circuit.

(1)

If we want to optimize the dynamic power in SRAM cell then any of the above parameters should be optimized here in this paper we are optimizing the Ct by keeping all other parameters as it is same as in the basic conventional SRAM cell.

Fig. 1. Basic SRAM cell

Amit Kumar is with the Bhai Maha Singh College of Engineering, Muktsar, Punjab Technical University, Jalandhar, Punjab, India. 2012 College of Engineering, Sukhveer Singh is with the Bhai Maha SinghJournal of Computing Press, NY, USA, ISSN 2151-9617 Muktsar, Punjab Technical University, Jalandhar, Punjab, India.

JOURNAL OF COMPUTING, VOLUME 4, ISSUE 9, SEPTEMBER 2012, ISSN (Online) 2151-9617 https://sites.google.com/site/journalofcomputing WWW.JOURNALOFCOMPUTING.ORG

79

The entire design is characterize in 130nm technology having a voltage supply of 1.5 volts and is simulated in the Tanner EDA tool [12].

Fig. 4. Write cycle of SRAM memory

2 ARCHITECTURE OF 7-T CELL

The new design of the SRAM consists 7-Transistor that is one extra transistor which will be controlled by one control signal and control signal will smartly on and off the extra transistor which will further produce the effect on the total switched capacitance and hence it will reduce the total switching power dissipation in the SRAM memory[7]. Fig 5 shows the basic architecture of the 7-T SRAM cell here single side writing structure is used. And data is written in the complement mode rather than the original form it breaks the path between Vdd and Gnd whenever the data is written by switch off the extra transistor the control signal control all the function, which is connected at the Gate of the transistor.

Fig. 2. Basic Memory Organization Fig. 1 shows the basic architecture of the 6-T SRAM cell it is having a bit lines and word lines and Fig. 2 shows the basic full control circuitry which is needed to control the operations of the SRAM memory cell.

Fig. 3. Read cycle of SRAM memory Fig. 3 shows the read cycle of SRAM memory it shows the transition on the bit lines which is very small and the Fig. 4 shows the write cycle which is having the large voltage swing [5] and hence responsible for higher power dissipation during the write cycle of the memory. During the rise and fall time of the bit lines there will be short circuit power dissipation.

Fig. 5. Architecture of 7-T cell The architecture shown above in Fig. 5 contains seven transistors and having a modification in the word line structure which is used to save the dynamic as well as leakage power dissipation in the SRAM cell while maintaining the functionality same as was in the conventional SRAM cell. The results of the power dissipation and the delay are shown in the result section of this paper.

2012 Journal of Computing Press, NY, USA, ISSN 2151-9617

JOURNAL OF COMPUTING, VOLUME 4, ISSUE 9, SEPTEMBER 2012, ISSN (Online) 2151-9617 https://sites.google.com/site/journalofcomputing WWW.JOURNALOFCOMPUTING.ORG

80

3 RESULTS
3.1 Dynamic Power Dissipation
TABLE 1 W RITE 1 POWER AT 100 MHZ FREQUENCY

Cell Type
6-T SRAM CELL 7-T SRAM CELL

Write 1 power
284 w 244 w

TABLE 2 W RITE 0 POWER AT 100 MHZ FREQUENCY

Cell Type
6-T SRAM CELL 7-T SRAM CELL

Write 0 power
187 w 160 w

Fig. 6. Layout of 7-T SRAM cell Fig. 6 shows the Layout of the 7-T SRAM memory cell which shows that area of the new 7-T SRAM cell is slightly more than the 6-T SRAM cell because of the introduction of the extra transistor in the design? From the layout of the 7-T SRAM cell it is calculated that low power cell takes 88.4 micrometer area while 6-T SRAM cell takes 67.7 micro meter silicon area, so 7-T SRAM cell consumes 23.4% more area.

TABLE 3 COMPARISON OF DELAY (6-T AND 7-T CELL)

Delay
Write 0 Write 1

6-T SRAM Cell

1.46ns

7-T SRAM Cell

1.2ns

% Improvement

4 CONCLUSION
In this paper 6-T and 7-T SRAM cell characterization is done by using the 130nm technology and results are observed, it is seen that the new cell is having a lesser dynamic power dissipation in the case, write 0 as well as write 1 and also delay is less as compared to 6-T SRAM cell. But it is using more silicon area as compared with the 6-T cell because of extra transistor but its advantages are having a higher weigh than the overheads which is justifying its design, one can further extends this work by optimizing this cell for further lesser area.

17%

1.0ns

0.94ns

6%

The above table shows that new 7-T SRAM cell consumes less power while writing 0 as well as writing 1 approximately improvement is 14% in case write 1 and 14.43% improvement in case of write 0 and also delay is improve 17 % incase of write 0 and 6% in case of write 1.

REFERENCES
[1]

Ashish Siwach, Rahul Rishi, Assymetric SRAM Power Dissipation and Delay International Journal of computation engineering and management , Vol. 11. Jan 2011. [2] Prashant Upadhyay and Mr. Rajesh Mehra,Low power design of 64-bits memory by using 8-t proposed SRAM cell, international journal of research and reviews in computer science (ijrrcs), vol. 1, no. 4, december 2010. [3] Sreerama Reddy G. M, P. Chandrashekara Reddy, Design and vlsi implementation of 8 mb low power SRAM in 90nm, european journal of scientific research issn 1450-216x, vol.26 no.2, pp.305-314, 2009. [4] Yung-Do Yang and Lee-Sup Kim, A low-power SRAM using hierarchical bit line and local sense amplifiers IEEE journal of 2012 Journal of Computing Press, NY, USA, ISSN 2151-9617 solid state circuits, vol.40, no. 6, june 2005.

JOURNAL OF COMPUTING, VOLUME 4, ISSUE 9, SEPTEMBER 2012, ISSN (Online) 2151-9617 https://sites.google.com/site/journalofcomputing WWW.JOURNALOFCOMPUTING.ORG

81

A. Islam, Mohd Hasan Leakage characterization of 10T SRAM cell Technique IEEE Transaction on electron devices. Vol 59, No.3 March 2012. [6] R. Aly, M. Faisal, and A. Bayoumi, Low-power cache design using 7-T SRAM cell in proc. IEEE system on chip confrence, pp. 171-174, 2005. [7] Neil H. E. Weste, David Harris and Ayan Banerjee, CMOS VLSI design, pearson education, third edition, pp. 55-57, 2006. [8] Ken Martin, Digital integrated circuit design Oxford University Press; New edition, Sept. 1999. [9] Varun Kumar Singhal, Balwinder Singh,Comparative study of power reduction techniques for staric access random memory, International Journal of VLSI and Signal Processing Applications, Vol. 1, Issue 2, pp. 80-88, May 2011. [10] http://www.tannereda.com/support/latest-version Amit Kumar received his B.E. degree in Electronics & Communication Engineering from Engineering College Bikaner, University of Rajasrhan, Jaipur and his M.Tech. degree in Microelectronics from Bhai Maha Singh College of Engineering, Muktsar, Punjab Technical University, Jalandhar, in 2007 and 2011 respectively. His research interests include Analog & Digital Communication and Digital Electronics. Sukhveer Singh received his B.Tech. degree in Electronics & Communication Engineering from Bhai Maha Singh College of Engineering, Muktsar, Punjab Technical University, Jalandhar, in 2009. His area of interest is Digital Circuits & Logic Design.

[5]

2012 Journal of Computing Press, NY, USA, ISSN 2151-9617