1999 Power Electronics Specialists Conference

Advances in Averaged Switch

Modeling and Simulation
Dragan Maksimovic
*
and Robert Erickson
Colorado Power Electronics Center
CoPEC
http://ece-www.colorado.edu/~pwrelect
* Acknowledgment: the work by Dragan Maksimovic was supported in part by the National Science Foundation
CAREER Award, Grant No. ECS-9703449.
ulIine
1. Introduction: converter modeling approaches and objectives
2. Averaged switch modeling of PWM converters operating in the
continuous conduction mode (CCM)
Basics of averaged switch modeling
Switch network steady-state and small-signal models
Using averaged-switch model to predict converter steady-state
characteristics and small-signal dynamics in CCM
PSpice implementation of the averaged switch model
Application examples: small-signal dynamics,
conduction losses and efficiency of a Sepic converter
Averaged switch modeling exercise: include switching losses
ulIine
conlinued
3. Averaged switch modeling of PWM converters operating in
discontinuous conduction mode (DCM)
Averaged switch model in DCM
Switch network steady-state and small-signal models in DCM
Using averaged-switch model to predict converter steady-state
characteristics and small-signal dynamics in DCM
Combined CCM/DCM averaged switch model
PSpice implementation of combined CCM/DCM models
Application examples:
Large-signal transient response of a SEPIC
Flyback converter small-signal frequency responses in CCM
and DCM
ulIine
conlinued
4. Averaged modeling of PWM converters with current-programmed
mode (CPM) control
Averaged switch model in CCM and DCM
Steady-state and AC models in CCM and DCM
Large-signal averaged CCM/DCM model for CPM controller
PSpice implementation of the CPM controller model
Application example: buck converter with CPM controller
5. Single-phase low-harmonic rectifiers
The ideal rectifier
Averaged models of rectifiers
Application examples:
DCM boost rectifier
SEPIC rectifier with nonlinear-carrier control
6. Summary
7. Bibliography
n-Line MaleiiaIs
http://ece-www.colorado.edu/~pwrelect/publications
seminar slides, collection of simulation examples, library of PSpice
models used in the examples, and many other CoPEC publications
and presentation materials
http://ece-www.colorado.edu/~pwrelect/ is the CoPEC home page
http://ece-www.colorado.edu/~pwrelect/book/bookdir.html
is the home page for the Textbook: R.W.Erickson, Fundamentals of
Power Electronics
Power Electronics courses at the University of Colorado:
Power Electronics 1: http://ece-www.colorado.edu/~ecen5797
Power Electronics 2: http:// ece-www.colorado.edu/~ecen5807
Power Electronics Lab: http:// ece-www.colorado.edu/~ecen4517
All simulation examples completed using free PSpice evaluation
version available from: http://www.orcad.com
1. IntrnductInn
Engineering design based on converter modeling:
Predict converter system behavior, validate models by experiments
Use the model to predict performance under worst-case conditions
Improve design until worst-case behavior meets specifications
(or until reliability and production yield are acceptably high)
Models:
Circuit models that yield design-oriented, analytical results
Models for computer simulation
Results of interest:
Steady-state characteristics
Component stresses, losses, efficiency
Large and small-signal dynamic responses
Seninai ljeclives
Describe basic averaged switch modeling approach
Develop averaged models for
Converters in continuous conduction mode (CCM)
Converters in discontinuous conduction mode (DCM)
Converters with Current-Programmed Mode (CPM) controller
Single-phase power-factor correctors
Summarize analytical results for steady-state and dynamic responses
Demonstrate PSpice implementations of averaged-switch models and
controllers
Present application examples
Large-signal transient responses and small-signal dynamics of DC-DC
converters and single-phase power-factor correctors
Aveiaged svilch nodeIing
Switch network is replaced by averaged circuit model. Switching
harmonics are removed, and low-frequency components of waveforms
are modeled in a simple way.
A very general approach to modeling converter losses, efficiency, and
dynamics.
Yields an intuitive understanding of converter behavior in CCM, DCM,
current-programmed mode, etc.
Applicable to all types of converters: dc-dc converters, as well as dc-ac
inverters, ac-dc low-harmonic rectifiers, ac-ac matrix converters.
Well-suited to simulation
Well developed and understood technique, easily taught to students.
Main reference for the material in this seminar:
R.W.Erickson, Fundamentals of Power Electronics, Chapman and
Hall, 1997.
Bibliography has a large collection of other selected references
Averaged switch modeling
+

Switching converter circuit

Switching
network
+

Large-signal averaged circuit model

Averaged
switch
model
d
+

DC and small-signal averaged circuit model

D+d
^
2
) / ( / ) / 1 ( 1
/ 1
) (
o o
s
co c
w s w s Q
w s
G s G
+ +

1
D
2
S
3
K
4
A
5
d
u
t
y
ccm-dcm1
+
-
DC, AC and Transient simulation
Model implementation for simulation
simulation
model
linearization
Analytical results:
steady-state characteristics
and small-signal dynamics
averaging
2. Averaged svilch nodeIing of IWM converlers
operaling in lhe conlinuous conduclion node
Basics of averaged switch modeling
Switch network steady-state and small-signal models
Using averaged-switch model to predict converter steady-state
characteristics and small-signal dynamics in CCM
PSpice implementation of averaged switch models
- ideal switches (ccm1)
- switches with conduction losses (ccm2)
- switches in converters with isolation transformer (ccm3)
- switch with conduction losses in converters with (possibly)
isolation transformer (ccm4)
Application example:
- SEPIC small-signal frequency response, conduction losses and
efficiency
Averaged switch modeling exercise: include switching losses
Averaged switch modeling
Basic approach
Given a PWM converter operating in continuous conduction mode:
+

D
1
L
1
C
2
+
v

Q
1
C
1
L
2
R V
g
SEPIC
example
Separate the switching elements from the remainder of the converter...
Definition of switch network,
SEPIC example
+
v
1
(t)

D
1
L
1
C
2
Q
1
C
1
L
2
R
i
L1
(t)
v
g
(t)
Switch network
i
L2
(t)
+ v
C1
(t)
+
v
C2
(t)

v
2
(t)
+
i
1
(t)
i
2
(t)
Duty
cycle
d(t)
Define a switch
network,
containing all of
the converter
switching
elements.
The remainder of
the converter is
linear and time-
invariant.
The terminal
voltages and
currents of the
switch network
can be arbitrarily
defined.
Switching converter system
with switch network explicitly defined
+

Time-invariant network
containing converter reactive elements
C
L
+ v
C
(t)
i
L
(t)
R
+
v(t)

v
g
(t)
Power input
Load
Switch network
p
o
r
t

1
p
o
r
t

2
d(t)
Control
input
+
v
1
(t)

+
v
2
(t)

i
1
(t) i
2
(t)
Discussion
l The number of ports in the switch network is less than or equal
to the number of SPST switches in the converter
l Simple dc-dc case, in which converter contains two SPST
switches: switch network contains two ports
The switch network terminal waveforms are then the port voltages and
currents: v
1
(t), i
1
(t), v
2
(t), and i
2
(t).
Two of these waveforms can be taken as independent inputs to the
switch network; the remaining two waveforms are then viewed as
dependent outputs of the switch network.
Switch network also includes control input d(t)
l Definition of the switch network terminal quantities is not unique.
Different definitions lead equivalent results having different
forms
Several ways to define the PWM switch network,
and the corresponding CCM models
+
v
2
(t)

i
1
(t) i
2
(t)
+
v
1
(t)

1 : D
D' : 1
+
v
2
(t)

i
1
(t) i
2
(t)
+
v
1
(t)

+
v
2
(t)

i
1
(t) i
2
(t)
+
v
1
(t)

D' : D
i
1
(t)
T
s
i
2
(t)
T
s
+
v
1
(t)
T
s

+
v
2
(t)
T
s

i
1
(t)
T
s
i
2
(t)
T
s
+
v
1
(t)
T
s

+
v
2
(t)
T
s

i
1
(t)
T
s
i
2
(t)
T
s
+
v
1
(t)
T
s

+
v
2
(t)
T
s

A few points
regarding averaged switch modeling
The switch network can be defined arbitrarily, as long as
its terminal voltages and currents are independent, and
the switch network contains no reactive elements.
It is not necessary that some of the switch network terminal quantities
coincide with inductor currents or capacitor voltages of the converter, or
be nonpulsating.
The object is simply to write the averaged equations of the switch network;
i.e., to express the average values of half of the switch network terminal
waveforms as functions of
the average values of the remaining switch network terminal waveforms,
and
the control input.
Terminal waveforms of the switch network
+
v
1
(t)

D
1
L
1
C
2
Q
1
C
1
L
2
R
i
L1
(t)
v
g
(t)
Switch network
i
L2
(t)
+ v
C1
(t)
+
v
C2
(t)

v
2
(t)
+
i
1
(t) i
2
(t)
Duty
cycle
d(t)
t
v
2
(t)
dT
s
T
s
0
0
v
2
(t)
T
2
0
v
C1
+ v
C2
t
i
1
(t)
dT
s
T
s
0
0
i
1
(t)
T
2
0
i
L1
+ i
L2
t
v
1
(t)
dT
s
T
s
0
0
v
1
(t)
T
s
0
v
C1
+ v
C2
t
i
2
(t)
dT
s
T
s
0
0
i
2
(t)
T
s
0
i
L1
+ i
L2
The averaging step
Now average all waveforms over one switching period:
+

Averaged time-invariant network

containing converter reactive elements
C
L
+ v
C
(t)
T
s

i
L
(t)
T
s
R
+
v(t)
T
s

v
g
(t)
T
s
Power input
Load
Averaged
switch network
p
o
r
t

1
p
o
r
t

2
d(t)
Control
input
+
v
2
(t)
T
s

i
1
(t)
T
s
i
2
(t)
T
s
+
v
1
(t)
T
s

x(t)
T
s
=
1
T
s
x(t)dt
t
t + T
s
The averaging step
The basic assumption is made that the natural time constants of the
converter are much longer than the switching period, so that the
converter contains low-pass filtering of the switching harmonics:
One may average the waveforms over an interval that is short
compared to the system natural time constants, without
significantly altering the system response.
In particular, averaging over the switching period T
s
removes the
switching harmonics, while preserving the low-frequency
components of the waveforms.
This step removes the small but mathematically-complicated
switching harmonics, leading to a relatively simple and tractable
converter model.
In practice, the only work needed for this step is to average the switch
dependent waveforms.
Averaged terminal equations
of the switch network
v
1
(t)
T
s
= d'(t) v
C1
(t)
T
s
+ v
C2
(t)
T
s
i
1
(t)
T
s
= d(t) i
L1
(t)
T
s
+ i
L2
(t)
T
s
v
2
(t)
T
s
= d(t) v
C1
(t)
T
s
+ v
C2
(t)
T
s
i
2
(t)
T
s
= d'(t) i
L1
(t)
T
s
+ i
L2
(t)
T
s
(small switching ripple is neglected)
t
v
1
(t)
dT
s
T
s
0
0
v
1
(t)
T
s
0
v
C1
+ v
C2
t
v
2
(t)
dT
s
T
s
0
0
v
2
(t)
T
2
0
v
C1
+ v
C2
t
i
1
(t)
dT
s
T
s
0
0
i
1
(t)
T
2
0
i
L1
+ i
L2
t
i
2
(t)
dT
s
T
s
0
0
i
2
(t)
T
s
0
i
L1
+ i
L2
Derivation of switch network equations
(Algebra steps)
i
L1
(t)
T
s
+ i
L2
(t)
T
s
=
i
1
(t)
T
s
d(t)
v
C1
(t)
T
s
+ v
C2
(t)
T
s
=
v
2
(t)
T
s
d(t)
We can write
Hence
v
1
(t)
T
s
=
d'(t)
d(t)
v
2
(t)
T
s
i
2
(t)
T
s
=
d'(t)
d(t)
i
1
(t)
T
s
+

v
2
(t)
T
s
+
i
1
(t)
T
s
Averaged switch network
+
v
1
(t)
T
s

i
2
(t)
T
s
d'(t)
d(t)
v
2
(t)
T
s
d'(t)
d(t)
i
1
(t)
T
s
Result
Modeling the switch network via
averaged dependent sources
Steady-state switch model:
Dc transformer model
D' : D
I
1
I
2
+
V
1

V
2
+
+
v
1
(t)

D
1
Q
1
Switch network

v
2
(t)
+
i
1
(t)
i
2
(t)
Duty
cycle
d(t)
Original switch network
Averaged steady-state model:
DC transformer
Correctly represents the
relationships between the dc
and low-frequency
components of the terminal
waveforms of the switch
network
Steady-state CCM SEPIC model
Replace switch network with dc transformer model
+

L
1
C
2
C
1
L
2
R
I
L1
V
g
I
L2
+ V
C1

+
V
C2

D' : D I
1
I
2
+
V
1

V
2
+
Can now let inductors
become short circuits,
capacitors become open
circuits, and solve for dc
conditions.
Can simulate this model
using PSPICE, to find
transient waveforms
Modeling converter dynamics:
Small-signal linearization of model
Perturb and linearize the switch
network averaged waveforms
about a quiescent operating
point. Let:
d(t) = D + d(t)
v
1
(t)
T
s
= V
1
+ v
1
(t)
i
1
(t)
T
s
= I
1
+ i
1
(t)
v
2
(t)
T
s
= V
2
+ v
2
(t)
i
2
(t)
T
s
= I
2
+ i
2
(t)
Voltage equation becomes
D + d V
1
+ v
1
= D' d V
2
+ v
2
Eliminate nonlinear terms
and solve for v
1
terms:
V
1
+ v
1
=
D'
D
V
2
+ v
2
d
V
1
+ V
2
D
=
D'
D
V
2
+ v
2
d
V
1
DD'
Linearization, continued
D + d I
2
+ i
2
= D' d I
1
+ i
1
Current equation becomes
Eliminate nonlinear terms
and solve for i
2
terms:
I
2
+ i
2
=
D'
D
I
1
+ i
1
d
I
1
+ I
2
D
=
D'
D
I
1
+ i
1
d
I
2
DD'
Switch network:
Small-signal ac model
+

D' : D
I
1
+ i
1
I
2
+ i
2
I
2
DD'
d
V
1
+ v
1
V
1
DD'
d
V
2
+ v
2
+

+
Reconstruct an equivalent circuit that corresponds to these small-
signal equations:
A general small-signal ac model for the PWM switch network
operating in CCM.
Transistor port Diode port
Small-signal ac model
of the CCM SEPIC
+

L
1
C
2
C
1
L
2
R
+

D' : D
I
2
DD'
d
V
1
DD'
d
V
g
+ v
g
I
L1
+ i
L1
I
L2
+ i
L2
V
C1
+ v
C1
V
C2
+ v
C2
+

Replace switch network with small-signal ac model:

Can now solve this
model to determine ac
transfer functions
Small-signal models
of several basic switch networks
+
v
2
(t)

i
1
(t) i
2
(t)
+
v
1
(t)

+
1 : D
I
1
+ i
1
I
2
+ i
2
I
2
d
V
1
+ v
1
V
1
d
V
2
+ v
2
+

+
D' : 1
I
1
+ i
1
I
2
+ i
2
I
1
d
V
1
+ v
1
V
2
d
V
2
+ v
2
+

+
v
2
(t)

i
1
(t) i
2
(t)
+
v
1
(t)

+
v
2
(t)

i
1
(t) i
2
(t)
+
v
1
(t)

+
D' : D
I
1
+ i
1
I
2
+ i
2
I
2
DD'
d
V
1
+ v
1
V
1
DD'
d
V
2
+ v
2
+

Table of results
Transfer functions of the basic buck, boost, and buck-boost converters
Converter
G
g0
G
d0

0
Q

z
buck D

V
D

1
LC

R
C
L

boost

1
D'

V
D'

D'
LC

D'R
C
L

D'
2
R
L
buck-boost

D
D'

V
D D'
2

D'
LC

D'R
C
L

D'
2
R
D L
where the transfer functions are written in the standard forms
G
vd
(s) = G
d0
1
s

z
1 +
s
Q
0
+
s

0
2
G
vg
(s) = G
g0
1
1 +
s
Q
0
+
s

0
2
Control-to-output and line-to-output transfer functions G
vd
(s) and G
vg
(s)
ISpice inpIenenlalion of lhe
lasic CCM averaged svilch nodeI (ccm1)
averaging
switch
network
1
2
3
4
D
S
K
A
+
_
v
1
(t)
+
_
v
2
(t)
i
1
(t) i
2
(t)
+

1
2
3
4
D
S
K
A
E
t
G
d
5
duty
averaged-switch
model
(sub-circuit)
d
1-d
d
v
2
1-d
d
i
1
+
_
v
2
+
_
v
1
i
2
i
1
Controlled voltage source E
t
replaces the transistor, controlled
current source G
d
replaces the diode
Duty ratio d is input to the subcircuit
Large-signal, nonlinear model suitable for DC, AC or Transient
simulation
The same model can be applied in any two-switch PWM converter
(the transistor and the diode need not have a common node)
Limitations: ideal switches, CCM only, valid for two-switch
converters without isolation transformer
CCM Averaged-Switch Model
PSpice Implementation: ccm1
**********************************************************
* MODEL: ccm1
* Application: two-switch PWM converters
* Limitations: ideal switches, CCM only, no transformer
**********************************************************
* Parameters: none
**********************************************************
* Nodes:
* 1: transistor+ (D)
* 2: transistor- (S)
* 3: diode cathode (K)
* 4: diode anode (A)
* 5: duty ratio (duty)
**********************************************************
.subckt ccm1 1 2 3 4 5
Et 1 2 value={(1-v(5))*v(3,4)/v(5)}
Gd 4 3 value={(1-v(5))*i(Et)/v(5)}
.ends
**********************************************************
+

1
2
3
4
D
S
K
A
E
t
G
d
5
duty
averaged-switch
network
(sub-circuit)
1
D
2
S
3
K
4
A
5
d
u
t
y
ccm1
U1
Sepic converter example
using ccm1 model
Objective: generate small-signal control-to-output frequency responses
800u
L1
0.1
R2
100u
L2
C1
100u
100u
C2
R1
0.5
+
-
ACMAG=1V
Vd
DC=0.5V
50
R3
1
D
2
S
3
K
4
A
5
d
u
t
y
U1
ccm1
+
-
50V
Vg
V
2x
1
2
3
4
sepic-ccm1.sch
Sepic converler exanpIe using ccm1 nodeI:
snaII-signaI conlroI-lo-oulpul response
(A) sepic-ccm1.dat
10Hz 100Hz 1.0KHz 10KHz 100KHz
Frequency
P(V(4))
0d
-100d
-200d
-270d
phase of vout/d
small-signal control-to-output response
Vout=50V, R=50, D=0.5
DB(V(4))
80
40
0
-20
magnitude || vout/d ||
Connenls
Subcircuit ccm1 is implementation of a large-signal, nonlinear
averaged model of the switch network
Averaged circuit model of the converter is obtained simply by replacing
switching devices with the averaged-switch subcircuit model
Linearization and AC small-signal analysis are performed by the
simulator
Small-signal dynamic responses can be easily generated for different
operating points or different sets of parameter values
CCM Averaged Svilch ModeI
Thal IncIudes Conduclion Losses
MOS transistor model: on-resistance R
ON
Diode model: constant forward voltage drop V
D
in series with R
d
resistance
Switch network
switch
network
1
2
3
4
D
S
K
A
+
_
v
1
(t)
+
_
v
2
(t)
i
1
(t) i
2
(t)
Waveforms
0 dT
s
T
s
t
v
1
(t)
0 dT
s
T
s
t
i
1
(t)
R
on
i
i v+V
D
+R
d
i
0 dT
s
T
s
t
v
2
(t)
0 dT
s
T
s
t
i
2
(t)
i
-V
D
-R
d
i
v-R
on
i
CCM Averaged Svilch ModeI ccm2
Thal IncIudes Conduclion Losses
0 dT
s
T
s
t
v
1
(t)
0 dT
s
T
s
t
i
1
(t)
R
on
i
i v+V
D
+R
d
i
0 dT
s
T
s
t
v
2
(t)
0 dT
s
T
s
t
i
2
(t)
i
-V
D
-R
d
i
v-R
on
i
s s
T T
i d i
1
s s
T T
i d i ) 1 (
2

s s
T T
i
d
d
i
1 2
1

( )( ) i R V v d i dR v
d D
T T
on
T
s s s
+ + + 1
1
s s s
T T T
v v v +
2 1
( )
( )
D
T
T
d
T
on
T
V v
d
d
d
i R d
d
i R
v
s
s s
s
+

+
1
2
1 1
1
1
1
CCM Averaged-Switch Model
PSpice Implementation: ccm2
**********************************************************
* MODEL: ccm2
* Application: two-switch PWM converters, includes
* conduction losses due to Ron, VD, Rd
* Limitations: CCM only, no transformer
**********************************************************
* Parameters:
* Ron=transistor on resistance
* VD=diode forward voltage drop (constant)
* Rd=diode on resistance
**********************************************************
* Nodes: (same as in ccm1)
**********************************************************
.subckt ccm2 1 2 3 4 5
+params: Ron=0 VD=0 Rd=0
Eron 1 1x value={i(Et)*(Ron+(1-v(5))*Rd/v(5))/v(5)}
Et 1x 2 value={(1-v(5))*(v(3,4)+VD)/v(5)}
Gd 4 3 value={(1-v(5))*i(Et)/v(5)}
.ends
**********************************************************
Subcircuit implementation
+

1
2
3
4
D
S
K
A
E
t
G
d
5
duty
averaged-switch
sub-circuit
+

E
ron
1
D
2
S
3
K
4
A
5
d
u
t
y
ccm2
U2
Sepic converter example using ccm2 model
Objective: find converter efficiency as a function of the transistor
on-resistance, for a range of loads
800u
L1
0.1
R2
100u
L2
C1
100u
100u
C2
R1
0.5
+
-
50V
Vg
+
-
DC=0.5V Vd
+
-
Iload
1A
10K
R4
1
D
2
S
3
K
4
A
5
d
u
t
y
VD=0.8V
ccm2
Rd=0.05
U1
Ron={Ron}
PARAMETERS:
Ron 0.0
V
2x
1
3
2 4
Sepic converler exanpIe using ccm2 nodeI:
Lfficiency vs. Ioad currenl and Ron
(D) sepic-ccm2.dat
1.0A 1.5A 2.0A 2.5A 3.0A 3.5A 4.0A 4.5A 5.0A
I_Iload
-100*V(4)* I(Iload)/ V(1)/ I(Vg)
100
95
90
85
80
Efficiency [%] (only conduction losses are included)
R
on
=0
R
on
=0.5
0.1
0.2
0.3
0.4
CCM Averaged Svilch ModeI ccm3
Ior Converlers Wilh IsoIalion Transforner
Switch network Waveforms
0 dT
s
T
s
t
v
1
(t)
0 dT
s
T
s
t
i
1
(t)
i
v
0 dT
s
T
s
t
v
2
(t)
0 dT
s
T
s
t
i
2
(t)
i/n
n v
switch
network
1
2
3
4
D
S
K
A
+
_
v
1
(t)
+
_
v
2
(t)
i
1
(t) i
2
(t)
1:n
PRIMARY
SECONDARY
Converters: Flyback, Cuk, Sepic, Inverse Sepic (Zeta), with isolation transformer
s s
T T
i
nd
d
i
1 2
1

s s
T T
v
nd
d
v
2 1
1

CCM Averaged-Switch Model

PSpice Implementation: ccm3
**********************************************************
* MODEL: ccm3
* Application: two-switch PWM converters,
* with (possibly) transformer
* Limitations: ideal switches, CCM only
**********************************************************
* Parameters:
* n=transformer turns ratio 1:n (primary:secondary)
**********************************************************
* Nodes: (same as in ccm1)
**********************************************************
.subckt ccm3 1 2 3 4 5
+params: n=1
Et 1 2 value={(1-v(5))*v(3,4)/v(5)/n}
Gd 4 3 value={(1-v(5))*i(Et)/v(5)/n}
.ends
**********************************************************
+

1
2
3
4
D
S
K
A
E
t
G
d
5
duty
averaged-switch
network
(sub-circuit)
1
D
2
S
3
K
4
A
5
d
u
t
y
ccm3
U3
CCM Averaged Svilch ModeI ccm4
(Conduclion Losses and IsoIalion Transforner)
Combined ccm2 and ccm3 averaged-switch models
Parameters:
Transistor on resistance R
on
Diode forward voltage drop V
D
Diode on resistance R
d
Transformer turns ratio n
A general model implementation valid for all two-switch converters
operating in CCM
CCM Averaged-Switch Model
PSpice Implementation: ccm4
* MODEL: ccm4
* Application: two-switch PWM converters, includes
* conduction losses due to Ron, VD, Rd
* and (possibly) transformer
* Limitations: CCM only
**********************************************************
* Parameters:
* Ron=transistor on resistance
* VD=diode forward voltage drop (constant)
* Rd=diode on resistance
* n=transformer turns ratio 1:n (primary:secondary)
**********************************************************
* Nodes: (same as in ccm1)
**********************************************************
.subckt ccm4 1 2 3 4 5
+params: Ron=0 VD=0 Rd=0 n=1
Eron 1 1x value={i(Et)*(Ron+(1-v(5))*Rd/n/n/v(5))/v(5)}
Et 1x 2 value={(1-v(5))*(v(3,4)+VD)/v(5)/n}
Gd 4 3 value={(1-v(5))*i(Et)/v(5)/n}
.ends
Subcircuit implementation
+

1
2
3
4
D
S
K
A
E
t
G
d
5
duty
averaged-switch
sub-circuit
+

E
ron
1
D
2
S
3
K
4
A
5
d
u
t
y
U4
ccm4
Averaged-Svilch ModeIing Lxercise:
IncIude Svilching Loss
Use averaged-switch modeling approach to construct an
averaged model that includes switching losses
Loss mechanism example: diode reverse recovery
Modeling switching loss
Example: diode stored
charge in boost converter
+
v
2
(t)

i
1
(t) i
2
(t)
+
v
1
(t)

L
C R v
g
(t)
i
L
(t)
+
v(t)

t
T
s
v
1
(t)
0
t
r
dT
s
t
0
i
1
i
2
(t)
0
v
2
v
2
0
i
1
Area
Q
r
Other switching loss mechanisms
are ignored in this example; one
can include other losses if
desired, using a similar procedure
Determine averaged terminal
waveforms of switch network
Construct averaged equivalent
circuit model
Waveforms:
Expressions for average terminal waveforms
Boost converter, switching loss example
t
T
s
v
1
(t)
0
t
r
dT
s
t
0
i
1
i
2
(t)
0
v
2
v
2
0
i
1
Area
Q
r
t
r
= diode reverse recovery time
Q
r
= diode recovered charge
( ) ( ) ( ) ( )
s s
T
r s
s
T
t v t T d
T
t v
2 1
1
1
+
( ) ( ) ( )
s
r
T T
T
Q
t i d t i
s s

1 2
1
Averaged equivalent circuit
of switch network
Diode reverse recovery time affects conversion ratio
Stored charge leads to power loss, modeled by current sink
( ) ( )
s s
T
s
r
T
t v
T
t
d t v
2 1
1

,
_

+
( ) ( )
( )

,
_

,
_

+
s
T
r r
T
s
r
T
T
t i t Q
t i
T
t
d t i
s
s s
1
1 2
1
+
_
+
_
+
_
+
_
switch network
averaged switch model
( ) t v
1
( ) t i
1
( ) t i
2
( ) t v
2
( )
s
T
t v
1
( )
s
T
t i
1
( )
s
T
t i
2
( )
s
T
t v
2
1 : 1

,
_

+
s
r
T
t
d
s
T
r r
T
i t Q
s
1
+
Insert averaged switch model into converter circuit
Original
converter
Averaged
model
+
v
2
(t)

i
1
(t) i
2
(t)
+
v
1
(t)

L
C R v
g
(t)
i
L
(t)
+
v(t)

L
C
R
i
1
(t)
T
s
i
2
(t)
T
s
+
v
1
(t)
T
s

+
v
2
(t)
T
s

t
r
T
s
+ (1 d) : 1
Q
r
T
s
+
v(t)
T
s

i
L
(t)
T
s
v
g
(t)
T
s
Efficiency Analysis
Boost converter, switching loss example
1
2
I V
VI
P
P
g in
out

D
T
Q
I
I
s
r

1
2
1
D
T
t
V
V
s
r
g
+

1
( )

,
_

,
_

,
_

,
_

s load
r
s
r
s
r
s
r
g
T I
Q
T D
t
T
Q
I
I
T
t
D
D
I V
VI
1
1
1
1
1
1
1
2
2
1
2

Efficiency due to diode reverse recovery. Other switching loss mechanisms

can be included using a similar procedure.
Sunnary of Iarl 2
Basic idea of average-switch modeling:
Define a switch network, containing all of the converter switching
elements
Average terminal waveforms over a switching period
Use controlled sources with values equal to average of the switch
network terminal waveforms
The result is a large-signal, nonlinear, time-invariant model that can be
inserted back into the converter network
The choices of the switch network and the independent terminal
waveforms are not unique - there are many ways to construct averaged
switch models
Averaged-switch model (suitable for circuit analysis or simulation)
yields predictions of converter steady-state and low-frequency dynamic
properties
Next: apply the averaged-switch modeling approach to other cases of
interest.
3. Avcragcd swItch mndc!Ing nf PWM cnnvcrtcrs
npcratIng In thc dIscnntInunus cnnductInn mndc
Averaged switch model in DCM
Using averaged-switch model to predict converter steady-state
characteristics and small-signal dynamics in DCM
Combined CCM/DCM averaged switch model
PSpice implementation of combined CCM/DCM models
- ideal switches (ccm-dcm1)
- ideal switches in converters with isolation transformer (ccm-dcm2)
Application examples:
- comparison of transient simulation results in a SEPIC example
using (1) switching circuit model and (2) averaged model
- small-signal dynamic responses of a flyback converter operating in
CCM or DCM
- more converter examples using averaged-switch subcircuits
Change in characteristics at the CCM/DCM boundary
l Steady-state output voltage becomes strongly load-dependent
l Simpler dynamics: one pole and the RHP zero are moved to very high
frequency, and can normally be ignored
l Traditionally, boost and buck-boost converters are designed to operate
in DCM at full load
l All converters may operate in DCM at light load
So we need equivalent circuits that model the steady-state and small-
signal ac models of converters operating in DCM
The averaged switch approach yields an intuitive result that is relatively
easy to solve
Derivation of DCM averaged switch model
Buck-boost example
+

L
C R
+
v

v
g
i
L
+
v
L

Switch network
+
v
1

v
2
+
i
1
i
2
Define switch terminal
quantities v
1
, i
1
, v
2
, i
2
, as
shown
Let us find the averaged
quantities v
1
, i
1

, v
2
,
i
2
, for operation in DCM,
and determine the
relations between them
d
1
T
s
T
s
t
i
1
(t)
i
pk
Area q
1
i
1
(t)
T
s
v
1
(t)
0
v
g
v
v
1
(t)
T
s
v
g
i
2
(t)
i
pk Area q
2
v
2
(t)
0
v
g
v
v
i
2
(t)
T
s
v
2
(t)
T
s
d
2
T
s
d
3
T
s
DCM waveforms
t
i
L
(t)
0
i
pk
v
g
L
v
L
v
L
(t)
v
g
v
0
+

L
C R
+
v

v
g
i
L
+
v
L

Switch network
+
v
1

v
2
+
i
1
i
2
Basic DCM equations
d
1
T
s
T
s
t
i
1
(t)
i
pk
Area q
1
i
1
(t)
T
s
v
1
(t)
0
v
g
v
v
1
(t)
T
s
v
g
i
2
(t)
i
pk Area q
2
v
2
(t)
0
v
g
v
v
i
2
(t)
T
s
v
2
(t)
T
s
d
2
T
s
d
3
T
s
i
pk
=
v
g
L
d
1
T
s
v
L
(t)
T
s
= d
1
v
g
(t)
T
s
+ d
2
v(t)
T
s
+ d
3
0
Peak inductor current:
Average inductor voltage:
In DCM, the diode switches off when the
inductor current reaches zero. Hence, i(0)
= i(T
s
) = 0, and the average inductor
voltage is zero. This is true even during
transients.
v
L
(t)
T
s
= d
1
(t) v
g
(t)
T
s
+ d
2
(t) v(t)
T
s
= 0
Solve for d
2
:
d
2
(t) = d
1
(t)
v
g
(t)
T
s
v(t)
T
s
Average switch network terminal voltages
d
1
T
s
T
s
t
i
1
(t)
i
pk
Area q
1
i
1
(t)
T
s
v
1
(t)
0
v
g
v
v
1
(t)
T
s
v
g
i
2
(t)
i
pk Area q
2
v
2
(t)
0
v
g
v
v
i
2
(t)
T
s
v
2
(t)
T
s
d
2
T
s
d
3
T
s
Average the v
1
(t) waveform:
v
1
(t)
T
s
= d
1
(t) 0 + d
2
(t) v
g
(t)
T
s
v(t)
T
s
+ d
3
(t) v
g
(t)
T
s
Eliminate d
2
and d
3
:
v
1
(t)
T
s
= v
g
(t)
T
s
Similar analysis for v
2
(t) waveform leads to
v
2
(t)
T
s
= d
1
(t) v
g
(t)
T
s
v(t)
T
s
+ d
2
(t) 0 + d
3
(t) v(t)
T
s
= v(t)
T
s
Average switch network terminal currents
d
1
T
s
T
s
t
i
1
(t)
i
pk
Area q
1
i
1
(t)
T
s
v
1
(t)
0
v
g
v
v
1
(t)
T
s
v
g
i
2
(t)
i
pk Area q
2
v
2
(t)
0
v
g
v
v
i
2
(t)
T
s
v
2
(t)
T
s
d
2
T
s
d
3
T
s
Average the i
1
(t) waveform:
Eliminate i
pk
:
Note i
1
(t)
Ts
is not equal to d i
L
(t)
Ts
!
Similar analysis for i
2
(t) waveform leads to
i
1
(t)
T
s
=
1
T
s
i
1
(t)dt
t
t + T
s
=
q
1
T
s
The integral q
1
is the area under the i
1
(t)
waveform during first subinterval. Use triangle
area formula:
q
1
= i
1
(t)dt
t
t + T
s
=
1
2
d
1
T
s
i
pk
i
1
(t)
T
s
=
d
1
2
(t) T
s
2L
v
1
(t)
T
s
i
2
(t)
T
s
=
d
1
2
(t) T
s
2L
v
1
(t)
T
s
2
v
2
(t)
T
s
Input port: Averaged equivalent circuit
i
1
(t)
T
s
=
d
1
2
(t) T
s
2L
v
1
(t)
T
s
i
1
(t)
T
s
=
v
1
(t)
T
s
R
e
(d
1
)
R
e
(d
1
) =
2L
d
1
2
T
s
v
1
(t)
T
s
i
1
(t)
T
s
R
e
(d
1
)
+

Low-frequency components of input port waveforms

obey Ohms law
Output port: Averaged equivalent circuit
i
2
(t)
T
s
=
d
1
2
(t) T
s
2L
v
1
(t)
T
s
2
v
2
(t)
T
s
i
2
(t)
T
s
v
2
(t)
T
s
=
v
1
(t)
T
s
2
R
e
(d
1
)
= p(t)
T
s
p(t)
+
v(t)

i(t)
Output port is a source of power p(t)
Power p(t) is independent of load characteristics
Power p(t) is dependent on (equal to) the power apparently
consumed by the switch network input port
The dependent power source
p(t)
+
v(t)

i(t)
v(t)i(t) = p(t)
v(t)
i(t)
Must avoid open- and short-circuit
connections of power sources
Power sink: negative p(t)
How the power source arises
in lossless two-port networks
In a lossless two-port network without internal energy storage:
instantaneous input power is equal to instantaneous output power
In all but a small number of special cases, the instantaneous power
throughput is dependent on the applied external source and load
If the instantaneous power depends only on the external elements
connected to one port, then the power is not dependent on the
characteristics of the elements connected to the other port. The other
port becomes a source of power, equal to the power flowing through
the first port
A power source (or power sink) element is obtained
Properties of power sources
P
1
P
2
P
3
P
1
+ P
2
+ P
3
P
1
P
1
n
1
: n
2
Series and parallel
connection of power
sources
Reflection of power
source through a
transformer
The loss-free resistor (LFR)
i
2
(t)
T
s
+

v
2
(t)
T
s
v
1
(t)
T
s
i
1
(t)
T
s
R
e
(d
1
)
+

p(t)
T
s
A two-port lossless network
Input port obeys Ohms Law
Power entering input port is transferred to output port
Averaged switch model: buck-boost example
+

L
C R
+
v

v
g
i
L
+
v
L

Switch network
+
v
1

v
2
+
i
1
i
2
i
2
(t)
T
s
v
2
(t)
T
s
v
1
(t)
T
s
i
1
(t)
T
s
R
e
(d)
+

L
C R
+

+
v(t)
T
s
v
g
(t)
T
s
p(t)
T
s
Original circuit
Averaged model
Solution of averaged model: steady state
P
R
e
(D)
+

R
+
V

V
g
I
1
Let
L short circuit
C open circuit
Converter input power:
Converter output power:
Equate and solve:
P =
V
g
2
R
e
P =
V
2
R
P =
V
g
2
R
e
=
V
2
R
V
V
g
= t
R
R
e
Steady-state LFR solution
V
V
g
= t
R
R
e
is a general result, for any system that can
be modeled as an LFR.
For the buck-boost converter, we have
R
e
(D) =
2L
D
2
T
s
Eliminate R
e
:
V
V
g
=
D
2
T
s
R
2L
=
D
K
which agrees with the results of previous steady-state analyses.
Averaged models of other DCM converters
Determine averaged terminal waveforms of switch network
In each case, averaged transistor waveforms obey Ohms law, while
averaged diode waveforms behave as dependent power source
Can simply replace transistor and diode with the averaged
model as follows:
i
2
(t)
T
s
+

v
2
(t)
T
s
v
1
(t)
T
s
i
1
(t)
T
s
R
e
(d
1
)
+

+
v
2
(t)

+
v
1
(t)

i
1
(t) i
2
(t)
p(t)
T
s
DCM buck, boost
R
e
(d)
+

L
C R
+

v(t)
T
s
v
g
(t)
T
s
R
e
(d)
+

L
C R
+

v(t)
T
s
v
g
(t)
T
s
Buck
Boost
p(t)
T
s
p(t)
T
s
R
e
=
2L
d
2
T
s
DCM Cuk, SEPIC
Cuk
+

L
1
C
2
R
C
1
L
2
v
g
(t)
T
s
+

v(t)
T
s
R
e
(d)
+

L
1
C
2
R
C
1
L
2
v
g
(t)
T
s
+

v(t)
T
s
R
e
(d)
SEPIC
p(t)
T
s
p(t)
T
s
R
e
=
2 L
1
||L
2
d
2
T
s
Steady-state solution: DCM buck, boost
P
R
e
(D)
+

R
+
V

V
g
P R
e
(D)
+

R
+
V

V
g
Let L short circuit
C open circuit
Buck
Boost
Steady-state solution of DCM/LFR models
Converter M, CCM M, DCM
Buck D

2
1 + 1 + 4R
e
/R
Boost

1
1 D
1 + 1 + 4R/R
e
2
Buck-boost, Cuk

D
1 D

R
R
e
SEPIC

D
1 D

R
R
e
I > I
crit
for CCM
I < I
crit
for DCM
I
crit
=
1 D
D
V
g
R
e
(D)
Small-signal ac modeling of the DCM switch network
d(t) = D + d(t)
v
1
(t)
T
s
= V
1
+ v
1
(t)
i
1
(t)
T
s
= I
1
+ i
1
(t)
v
2
(t)
T
s
= V
2
+ v
2
(t)
i
2
(t)
T
s
= I
2
+ i
2
(t)
i
2
(t)
T
s
+

v
2
(t)
T
s
v
1
(t)
T
s
i
1
(t)
T
s
R
e
(d)
+

p(t)
T
s
d(t)
Large-signal averaged model Perturb and linearize: let
i
1
(t)
T
s
=
d
1
2
(t) T
s
2L
v
1
(t)
T
s
i
2
(t)
T
s
=
d
1
2
(t) T
s
2L
v
1
(t)
T
s
2
v
2
(t)
T
s
i
1
=
v
1
r
1
+ j
1
d + g
1
v
2
i
2
=
v
2
r
2
+ j
2
d + g
2
v
1
A more convenient way to model the buck and boost
small-signal DCM switch networks
+
v
2
(t)

i
1
(t) i
2
(t)
+
v
1
(t)

+
v
2
(t)

i
1
(t) i
2
(t)
+
v
1
(t)

v
1
r
1
j
1
d
g
1
v
2
i
1
g
2
v
1
j
2
d
r
2
i
2
v
2
In any event, a small-signal two-port model is used, of the form
Small-signal DCM switch model parameters

+
+

v
1
r
1
j
1
d
g
1
v
2
i
1
g
2
v
1
j
2
d
r
2
i
2
v
2
Switch type
g
1
j
1
r
1
g
2
j
2
r
2
Buck,
Fig. 10.16(a)

1
R
e

2(1 M)V
1
DR
e

R
e

2 M
MR
e

2(1 M)V
1
DMR
e
M
2
R
e
Boost,
Fig. 10.16(b)

1
(M 1)
2
R
e

2MV
1
D(M 1)R
e

(M 1)
2
M
R
e

2M 1
(M 1)
2
R
e

2V
1
D(M 1)R
e
(M 1)
2
R
e
Buck-boost,
Fig. 10.7(b)
0

2V
1
DR
e

R
e

2M
R
e

2V
1
DMR
e

M
2
R
e
DCM small-signal transfer functions
l When expressed in terms of R, L, C, and M (not D), the small-
signal transfer functions are the same in DCM as in CCM
l Hence, DCM boost and buck-boost converters exhibit two poles
and one RHP zero in control-to-output transfer functions
l But, value of L is small in DCM. Hence
RHP zero appears at high frequency, usually greater than
switching frequency
Pole due to inductor dynamics appears at high frequency, near
to or greater than switching frequency
So DCM buck, boost, and buck-boost converters exhibit
essentially a single-pole response
l A simple approximation: let L 0
The simple approximation L 0
Buck, boost, and buck-boost converter models all reduce to
+

r
1
j
1
d
g
1
v
2
g
2
v
1
j
2
d
r
2 C R
DCM switch network small-signal ac model
v
g
v
Transfer functions
G
vd
(s) =
v
d
v
g
= 0
=
G
d0
1 +
s

p
G
d0
= j
2
R || r
2

p
=
1
R || r
2
C
G
vg
(s) =
v
v
g
d = 0
=
G
g0
1 +
s

p
G
g0
= g
2
R || r
2
= M
with
control-to-output
line-to-output
Transfer function salient features
Converter
G
d0
G
g0

p
Buck

2V
D
1 M
2 M M

2 M
(1 M)RC
Boost

2V
D
M 1
2M 1 M

2M 1
(M 1)RC
Buck-boost

V
D M

2
RC
R = 12
L = 5 H
C = 470 F
f
s
= 100 kHz
The output voltage is regulated to be V = 36 V. It is desired to determine G
vd
(s) at the
operating point where the load current is I = 3 A and the dc input voltage is V
g
= 24 V.
DCM boost example
Control-to-output transfer function G
vd
(s)
+

Q
1
L
C R
+
v(t)

D
1
V
g
i(t)
+ v
L
(t)
i
D
(t)
i
C
(t)
Evaluate simple model parameters
P = I V V
g
= 3 A 36 V 24 V = 36 W
R
e
=
V
g
2
P
=
(24 V)
2
36 W
= 16
D =
2L
R
e
T
s
=
2(5 H)
(16 )(10 s)
= 0.25
G
d0
=
2V
D
M 1
2M 1
=
2(36 V)
(0.25)
(36 V)
(24 V)
1
2
(36 V)
(24 V)
1
= 72 V 37 dBV
f
p
=

p
2
=
2M 1
2 (M 1)RC
=
2
(36 V)
(24 V)
1
2
(36 V)
(24 V)
1 (12 )(470 F)
= 112 Hz
Control-to-output transfer function, boost example
20 dB/decade
f
p
112 Hz
G
d0
37 dBV
f
0
0
90
180
270
|| G
vd
||
|| G
vd
||


G
vd
0 dBV
20 dBV
40 dBV
20 dBV
40 dBV
60 dBV

G
vd
10 Hz 100 Hz 1 kHz 10 kHz 100 kHz
A Nole on High-Irequency Irediclions of lhe
Averaged Svilch ModeI
Observed high-frequency response due to inductor dynamics
Averaged-switch model derivation used:
0
s
T
L
v
which is consistent with the fact that in DCM the inductor current starts
from zero and ends at zero in each switching cycle, even in transients
However, high-frequency dynamics due to the inductor indicates that
the AC voltage across the inductor in the small-signal model is not zero
Model predictions at high frequencies are not quite correct
Corrected averaged models that include the inductor in the averaged
switch model have recently been described
See References: [Sun et. al. PESC99], [Ben-Yaakov et.al. PESC94]
Conlined CCM/DCM
Average Svilch ModeI
Objective: a general large-signal averaged-switch model
Valid in CCM and DCM
5 terminals:
transistor port (2 terminals)
diode port (2 terminals)
duty ratio input (1 terminal)
DCM/CCM boundary resolved within the model, based only on the
terminal voltages/currents of the model
Spice compatible
Conlined CCM/DCM
Average Svilch ModeI
v
1
(t)
d
+
v
1
1
2
3
4
5
duty
d
+
_
v
2
_
i
2
i
1
R
e
(d)
p(t)
switch
network
1
2
3
4
+
_
+
_
v
2
(t)
i
1
(t) i
2
(t)
1
2
3
4
5
duty
d
+
_
v
2
_
i
2
i
1
averaged-switch
model
CCM
+

1
2
3
4
E
t
G
d
5
duty
1-d
d
v
2
1-d
d
i
1
+
_
v
2
+
_
v
1
i
2
i
1
?
averaged-switch
model
DCM
averaged-switch
model
CCM/DCM
Conlined CCM/DCM
Average Svilch ModeI
3
4
K
A
E
t
G
d
5
duty
averaged-switch
model
CCM/DCM
d
1-u
u
i
1
+
_
v
2
i
2
+

1
2
D
S
1-u
u
v
2
+
_
v
1
i
1

'

DCM
v
i
Lf d
d
CCM d
u
s
,
2
,
2
1
2
2
CCM/DCM boundary:

,
_

2
1
2
2
2
,
v
i
Lf d
d
d MAX u
s
u = equivalent switch duty ratio
CCM/ DCM Averaged-Switch Model
PSpice Implementation: ccm-dcm1
**************************************************************************************
* MODEL: ccm-dcm1
* Application: two-switch PWM converters, CCM or DCM
* Limitations: ideal switches, no transformer
**************************************************************************************
* Parameters:
* L=equivalent inductance (relevant for DCM)
* fs=switching frequency
**************************************************************************************
* Nodes: (same as in ccm1)
**************************************************************************************
.subckt ccm-dcm1 1 2 3 4 5 params: L=1 fs=1E6
Et 1 2 value={(1-v(u))*v(3,4)/v(u)}
Gd 4 3 value={(1-v(u))*i(Et)/v(u)}
Ga 0 a value={MAX(i(Et),0)}
Va a b
Rdummy b 0 10
Eu u 0 table {MAX(v(5), v(5)*v(5)/(v(5)*v(5)+2*L*fs*i(Va)/v(3,4)))} (0 0) (1 1)
.ends
**************************************************************************************
Conlined CCM/DCM
Average Svilch ModeI
Wilh IsoIalion Transforner

'

DCM
v
i
nLf d
d
CCM d
u
s
,
2
,
2
1
2
2
CCM/DCM boundary:

,
_

2
1
2
2
2
,
v
i
nLf d
d
d MAX u
s
u = equivalent switch duty ratio
3
4
K
A
E
t
G
d
5
duty
averaged-switch
model
CCM/DCM
d
1-u
i
1
+
_
v
2
i
2
+

1
2
D
S
1-u
v
2
+
_
v
1
i
1
n u
n u
CCM/ DCM Averaged-Switch Model
PSpice Implementation: ccm-dcm2
* MODEL: ccm-dcm2
* Application: two-switch PWM converters, CCM or DCM with (possibly) transformer
* Limitations: ideal switches, no transformer
****************************************************************************************
* Parameters:
* L=equivalent inductance (relevant for DCM), referred to primary
* fs=switching frequency
* n=transformer turns ratio 1:n (primary:secondary)
****************************************************************************************
* Nodes: (same as in ccm1)
****************************************************************************************
.subckt ccm-dcm2 1 2 3 4 5 params: L=1 fs=1E6 n=1
Et 1 2 value={(1-v(u))*v(3,4)/v(u)/n}
Gd 4 3 value={(1-v(u))*i(Et)/v(u)/n}
Ga 0 a value={MAX(i(Et),0)}
Va a b
Rdummy b 0 10
Eu u 0 table {MAX(v(5), v(5)*v(5)/(v(5)*v(5)+2*L*n*fs*i(Va)/v(3,4)))} (0 0) (1 1)
.ends
****************************************************************************************
CCM/DCM ModeI AppIicalions
ccm-dcm1 (for non-isolated converters) and ccm-dcm2 (for converters
that may include isolation transformer) are general, large-signal
averaged-switch models (PSpice subcircuits) valid for both CCM and
DCM
Can be applied to DC, AC, or Transient simulation of any two-switch
PWM converter
Limitations: ideal switches, no losses are modeled, but the model can
be refined further to include conduction losses
Application examples:
Comparison of Transient simulation results in a Sepic converter
example using:
(1) switching circuit model
(2) ccm-dcm2 averaged switch model
AC simulation results for a flyback converter operating in CCM or
DCM
Sepic converter example:
switching circuit model
Switching frequency 100kHz, duty ratio D=0.5
100u
L4
100u
C4
0.5
R6
800u
L3
MUR820
D1
IRF640
M1
100
R5
100u
C3
0.1
R4
Resr3
0.2
+
-
+
-
S2
switch
R11
20
R7
10
+
-
V4
+
-
V3
+
-
Vg2
50V
V
24
23
22
21
22x
Sepic converter example:
averaged model using ccm-dcm2
Exactly the same PSpice circuit, except the MOSFET M1 and the
diode D1 replaced by the ccm-dcm2 subcircuit, and pulsating
gate drive V3 replaced by a duty-ratio voltage source Vd
800u
L1
100u
L2
+
-
ACMAG=1V
Vd
DC=0.5V
100u
C2
0.5
R1
100
R3
C1
100u
0.1
R2
Resr1
0.2
1
D
2
S
3
K
4
A
5
d
u
t
y
ccm-dcm2
U6
R10
20
+
-
V4
+
-
+
-
S1
switch
+
-
Vg
50V
V
2x
1
2
3
4
Sepic converler exanpIe:
averaged vs. svilching nodeI
(B) sepic-switch.dat
0s 5ms 10ms 15ms 20ms
Time
V(24) V(4)
80V
60V
40V
20V
0V
Averaged model
Switching model
V
out
start-up transient load transient
Start-up and load transient response
Sepic converler exanpIe:
averaged vs. svilching nodeI
(B) sepic-switch.dat
10.0ms 10.2ms 10.4ms 10.6ms 10.8ms 11.0ms 11.2ms 11.4ms
Time I(D1) I(X_U6.Gd)
10A
8A
6A
4A
2A
0A
-2A
Diode current during load transient
switching model
averaged model
Details of the diode current waveform around the load transient
Flyback converter example
using ccm-dcm2 averaged-switch model
CCM for Rload=1 Ohm, DCM for Rload=2 Ohm
+
- 0.25
Vd
AC=1
500uF
C1
+
-
48V
Vg
0.2
R2
* *
1:n
Lm
2
3
4
1
Lm=50u
n=0.25
transformer
T1
1
D
2
S
3
K
4
A
5
d
u
t
y
n=0.25
ccm-dcm2
U1
L=50u
fs=100K
PARAMETERS:
Rload 2
R1
{Rload}
V
1
2
3
4
IIylacI converler exanpIe
using ccm-dcm2 averaged-svilch nodeI
(C) flyback-ccm-dcm2.dat
10Hz 100Hz 1.0KHz 10KHz 100KHz
Frequency
P(V(4))
0d
-100d
-200d
DB(V(4))
50
0
-50
Magnitude response, control-to-output v/d
Phase response, control-to-output v/d
R
load
= 1, CCM
R
load
= 2, DCM
R
load
= 2, DCM
R
load
= 1, CCM
Frequency responses generated by PSpice AC analyses
Other Converter Examples
Watkins-Johnson converter
Pspice averaged circuit model
using ccm-dcm2
averaged-switch subcircuit
+
-
Vg
*
*
1
:
n
L
m
2
3 4
1
transformer
+
-
Vd
1
D
2
S
3
K
4
A
5
duty
ccm-dcm2
*
*
1
:
n
L
m
2
3 4
1
transformer
+
-
Vg
Other Converter Examples
Cuk converter with
isolation transformer
PSpice averaged circuit model
using ccm-dcm2
averaged-switch subcircuit
+
-
Vg * *
1:n
Lm
2
3
4
1
transformer
+
-
Vg * *
1:n
Lm
2
3
4
1
transformer
1
D
2
S
3
K
4
A
5
d
u
t
y
ccm-dcm2
U2
4. Averaged nodeIing of IWM converlers vilh
currenl-progranned node (CIM) conlroI
Averaged switch model for current-programmed mode (CPM) in
CCM
Steady-state and simple AC model in CCM
Averaged switch model for CPM in DCM
Steady-state and small-signal AC model in DCM
Large-signal averaged CCM/DCM model for current-mode
controller
PSpice implementation of the averaged CPM controller model
Application examples
- Buck converter with current-programmed mode controller
Current-programmed control
+

Buck converter
Current-programmed controller
R v
g
(t)
i
s
(t)
+
v(t)

i
L
(t)
Q
1
L
C
D
1
+

Analog
comparator
Latch
T
s
0
S
R
Q
Clock
i
s
(t)
R
f
Measure
switch
current
i
s
(t)R
f
Control
input
i
c
(t)R
f

+
v
ref
v(t)
Compensator
Conventional output voltage controller
Switch
current
i
s
(t)
Control signal
i
c
(t)
m
1
t 0 dT
s
T
s
on off
Transistor
status:
Clock turns
transistor on
Comparator turns
transistor off
The peak transistor current
replaces the duty cycle as the
converter control input.
A simple approximation
i
L
(t)
T
s
= i
c
(t)
Neglects switching ripple and artificial ramp (slope compensation)
Yields physical insight and simple first-order model
Accurate when converter operates well into CCM (so that switching
ripple is small) and when the magnitude of the artificial ramp is not
too large
Well-accepted by practicing engineers
Resulting small-signal relation:
i
L
(s) i
c
(s)
Averaged switch modeling
with the simple approximation
+

L
C R
+
v(t)

v
g
(t)
i
L
(t)
+
v
2
(t)

i
1
(t) i
2
(t)
Switch network
+
v
1
(t)

v
2
(t)
T
s
= d(t) v
1
(t)
T
s
i
1
(t)
T
s
= d(t) i
2
(t)
T
s
Averaged terminal waveforms,
CCM:
The simple approximation:
i
2
(t)
T
s
i
c
(t)
T
s
Buck converter example
CPM averaged switch equations
v
2
(t)
T
s
= d(t) v
1
(t)
T
s
i
1
(t)
T
s
= d(t) i
2
(t)
T
s
i
2
(t)
T
s
i
c
(t)
T
s
Eliminate duty cycle:
i
1
(t)
T
s
= d(t) i
c
(t)
T
s
=
v
2
(t)
T
s
v
1
(t)
T
s
i
c
(t)
T
s
i
1
(t)
T
s
v
1
(t)
T
s
= i
c
(t)
T
s
v
2
(t)
T
s
= p(t)
T
s
So:
Output port is a current source
Input port is a dependent power sink
CPM averaged switch model
+

L
C R
+
v(t)
T
s

v
g
(t)
T
s
i
L
(t)
T
s
+
v
2
(t)
T
s

i
1
(t)
T
s
i
2
(t)
T
s
Averaged switch network
+
v
1
(t)
T
s

i
c
(t)
T
s
p(t)
T
s
Results for other converters
+

L
C R
+
v(t)
T
s

v
g
(t)
T
s
i
L
(t)
T
s
Averaged switch network
i
c
(t)
T
s
p(t)
T
s
+

L
C R
+
v(t)
T
s

v
g
(t)
T
s
i
L
(t)
T
s
Averaged switch network
i
c
(t)
T
s
p(t)
T
s
Boost
Buck-boost
Perturbation and linearization
to construct small-signal model, CCM
v
1
(t)
T
s
= V
1
+ v
1
(t)
i
1
(t)
T
s
= I
1
+ i
1
(t)
v
2
(t)
T
s
= V
2
+ v
2
(t)
i
2
(t)
T
s
= I
2
+ i
2
(t)
i
c
(t)
T
s
= I
c
+ i
c
(t)
Let
V
1
+ v
1
(t) I
1
+ i
1
(t) = I
c
+ i
c
(t) V
2
+ v
2
(t)
Resulting input port equation:
Small-signal result:
i
1
(t) = i
c
(t)
V
2
V
1
+ v
2
(t)
I
c
V
1
v
1
(t)
I
1
V
1
Output port equation:

2
=
c
Resulting small-signal model
Buck example
+

L
C R
+

Switch network small-signal ac model

+

v
g

V
1
I
1
i
1
i
2
i
c
V
2
V
1
i
c
v
1 v
2
I
c
V
1
v
2 v
i
1
(t) = i
c
(t)
V
2
V
1
+ v
2
(t)
I
c
V
1
v
1
(t)
I
1
V
1
Predicted transfer functions of the CPM buck converter
+

L
C R
+

v
g
i
c
v

D
2
R
D
R
v i
c
D 1 +
sL
R
i
g
i
L
G
vc
(s) =
v(s)
i
c
(s)
v
g
= 0
= R ||
1
sC
G
vg
(s) =
v(s)
v
g
(s)
i
c
= 0
= 0
Table of results
basic converters
+

i
g
v
g R C
r
1
f
1
(s) i
c
g
1
v g
2
v
g
f
2
(s) i
c
r
2
v
+

Converter
g
1
f
1
r
1
g
2
f
2
r
2
Buck

D
R

D 1 +
sL
R

R
D
2
0 1
Boost
0 1

1
D'R

D' 1
sL
D'
2
R
R
Buck-boost

D
R

D 1 +
sL
D'R

D'R
D
2

D
2
D'R

D' 1
sDL
D'
2
R

R
D
Discontinuous conduction mode
in current-programmed converters
Again, use averaged switch modeling approach
Result: simply replace
Transistor by power sink
Diode by power source
Inductor dynamics appear at high frequency, near to or greater
than the switching frequency
Small-signal transfer functions contain a single low frequency pole
DCM CPM boost and buck-boost are stable without artificial ramp
DCM CPM buck without artificial ramp is stable for D < 2/3. A
small artificial ramp m
a
0.086m
2
leads to stability for all D.
DCM CPM buck-boost example
+

L
C R
+
v(t)

v
g
(t)
i
L
(t)
Switch network
+
v
1
(t)

v
2
(t)
+
i
1
(t) i
2
(t)
m
1
=
v
1
T
s
L
m
2
=
v
2
T
s
L
t
i
L
(t)
0
i
pk
v
L
(t)
0
v
1
(t)
T
s
v
2
(t)
T
s
i
c
m
a
Analysis
m
1
=
v
1
T
s
L
m
2
=
v
2
T
s
L
t
i
L
(t)
0
i
pk
v
L
(t)
0
v
1
(t)
T
s
v
2
(t)
T
s
i
c
m
a
i
pk
= m
1
d
1
T
s
m
1
=
v
1
(t)
T
s
L
i
c
= i
pk
+ m
a
d
1
T
s
= m
1
+ m
a
d
1
T
s
d
1
(t) =
i
c
(t)
m
1
+ m
a
T
s
Averaged switch input port equation
d
1
T
s
T
s
t
i
1
(t)
i
pk
Area q
1
i
1
(t)
T
s
d
2
T
s
d
3
T
s
i
2
(t)
i
pk Area q
2
i
2
(t)
T
s
i
1
(t)
T
s
=
1
T
s
i
1
()d
t
t + T
s
=
q
1
T
s
i
1
(t)
T
s
=
1
2
i
pk
(t)d
1
(t)
i
1
(t)
T
s
=
1
2
m
1
d
1
2
(t)T
s
i
1
(t)
T
s
=
1
2
Li
c
2
f
s
v
1
(t)
T
s
1 +
m
a
m
1
2
i
1
(t)
T
s
v
1
(t)
T
s
=
1
2
Li
c
2
f
s
1 +
m
a
m
1
2
= p(t)
T
s
Discussion: switch network input port
Averaged transistor waveforms obey a power sink characteristic
During first subinterval, energy is transferred from input voltage
source, through transistor, to inductor, equal to
W =
1
2
Li
pk
2
This energy transfer process accounts for power flow equal to
p(t)
T
s
= Wf
s
=
1
2
Li
pk
2
f
s
which is equal to the power sink expression of the previous slide.
Averaged switch output port equation
d
1
T
s
T
s
t
i
1
(t)
i
pk
Area q
1
i
1
(t)
T
s
d
2
T
s
d
3
T
s
i
2
(t)
i
pk Area q
2
i
2
(t)
T
s
i
2
(t)
T
s
=
1
T
s
i
2
()d
t
t + T
s
=
q
2
T
s
q
2
=
1
2
i
pk
d
2
T
s
d
2
(t) = d
1
(t)
v
1
(t)
T
s
v
2
(t)
T
s
i
2
(t)
T
s
=
p(t)
T
s
v
2
(t)
T
s
i
2
(t)
T
s
v
2
(t)
T
s
=
1
2
Li
c
2
(t) f
s
1 +
m
a
m
1
2
= p(t)
T
s
Discussion: switch network output port
Averaged diode waveforms obey a power sink characteristic
During second subinterval, all stored energy in inductor is
transferred, through diode, to load
Hence, in averaged model, diode becomes a power source,
having value equal to the power consumed by the transistor
power sink element
Averaged equivalent circuit
i
2
(t)
T
s
v
2
(t)
T
s
v
1
(t)
T
s
i
1
(t)
T
s
+

L
C R
+

+
v(t)
T
s
v
g
(t)
T
s
p(t)
T
s
Steady state model: DCM CPM buck-boost
+

R
+
V

V
g
P
V
2
R
= P
Solution
P =
1
2
LI
c
2
(t) f
s
1 +
M
a
M
1
2
V= PR = I
c
RLf
s
2 1 +
M
a
M
1
2
for a resistive load
Models of buck and boost
+

L
C R
+

v(t)
T
s
v
g
(t)
T
s
p(t)
T
s
+

L
C R
+

v(t)
T
s
v
g
(t)
T
s
p(t)
T
s
Buck
Boost
Summary of steady-state
DCM CPM characteristics
Converter M
I
crit
Stability range
when m
a
= 0
Buck

P
load
P
P
load

1
2
I
c
M m
a
T
s

0 M <
2
3
Boost

P
load
P
load
P

I
c

M 1
M
m
a
T
s
2 M
0 D 1
Buck-boost
Depends on load characteristic:
P
load
= P

I
c

M
M 1
m
a
T
s
2 M 1
0 D 1
I > I
crit
for CCM
I < I
crit
for DCM
Linearized small-signal models
+

v
1
r
1
f
1
i
c
g
1
v
2
i
1
g
2
v
1
f
2
i
c
r
2
i
2
v
2
+

L
C R
+

v
g
v
i
L
Buck
+

v
1
r
1
f
1
i
c
g
1
v
2
i
1
g
2
v
1
f
2
i
c
r
2
i
2
v
2
+

L
C R
+

v
g
v
i
L
Boost
Linearized small-signal models: Buck-boost
+

v
1
r
1
f
1
i
c
g
1
v
2
i
1
g
2
v
1
f
2
i
c
r
2
i
2
v
2

+
L
C R
+

v
g
v
i
L
DCM CPM small-signal parameters: input port
Converter
g
1
f
1
r
1
Buck

1
R
M
2
1 M
1
m
a
m
1
1 +
m
a
m
1

2
I
1
I
c

R
1 M
M
2
1 +
m
a
m
1
1
m
a
m
1
Boost

1
R
M
M 1

2
I
I
c

R
M
2 2 M
M 1
+
2
m
a
m
1
1 +
m
a
m
1
Buck-boost
0

2
I
1
I
c

R
M
2
1 +
m
a
m
1
1
m
a
m
1
DCM CPM small-signal parameters: output port
Converter
g
2
f
2
r
2
Buck

1
R
M
1 M
m
a
m
1
2 M M
1 +
m
a
m
1

2
I
I
c

R
1 M 1 +
m
a
m
1
1 2M +
m
a
m
1
Boost

1
R
M
M 1

2
I
2
I
c

R
M 1
M
Buck-boost

2M
R
m
a
m
1
1 +
m
a
m
1

2
I
2
I
c
R
Simplified DCM CPM model, with L = 0
+

r
1
f
1
i
c
g
1
v g
2
v
g
f
2
i
c
r
2 C R
v
g
v
Buck, boost, buck-boost all become
G
vc
(s) =
v
i
c
v
g
= 0
=
G
c0
1 +
s

p
G
c0
= f
2
R || r
2

p
=
1
R || r
2
C
G
vg
(s) =
v
v
g
i
c
= 0
=
G
g0
1 +
s

p
G
g0
= g
2
R || r
2
Currenl-Irogranned (CIM) ConlroIIer:
Large-SignaI CCM/DCM Averaged ModeI
t
0 dT
s
T
s
i
c
-m
a
m
1
-m
2
i
pk
i
L
(t)
d
2
T
s
=(1-d)T
s
t
0 dT
s
T
s
i
c
-m
a
m
1
-m
2
i
pk
(d+d
2
)T
s
i
L
(t)
d
2
T
s
s a c pk
dT m i i

,
_

,
_

2 2
2 2
2
1 s
pk
s
pk
T
L
T d m
i d
dT m
i d i
s

'

DCM
T m
i
CCM d
d
s
pk
2
2
1

,
_

s
pk
T m
i
d MIN d
2
2
, 1
CCM/DCM:
CIM ConlroIIer:
Large-SignaI CCM/DCM Averaged ModeI
( )
( )
s a s
s
T
L c
T d d m dT m
T d m i d d i
d
s
2 1
2
2 2 2
2
2 2
+ +
+

,
_

s
s a c
T m
dT m i
d MIN d
2
2
, 1
c
i
1
m
2
m
d
s
T
L
i
Inputs:
Model:
Output: duty ratio
2
d
CPM Large-Signal Averaged Model:
PSpice Implementation
**********************************************************
* MODEL: CPM
* Current-Programmed-Mode CCM/DCM controller model.
* All parameters and inputs are referred to
* the primary side.
**********************************************************
* Parameters:
* L=equivalent inductance, referred to primary
* fs=switching frequency
* va=amplitude of the artificial ramp, va=Rf*ma/fs
* Rf=equivalent current-sense resistance
**********************************************************
* Nodes:
* ctr: control input, v(ctr)=Rf*ic
* current: sensed average inductor current v(current)=Rf*iL
* 1: voltage across L in interval 1, slope m1=v(1)/L
* 2: (-) voltage across L in interval 2, slope m2=v(2)/L
* d: duty ratio (output of the controller)
**********************************************************
.subckt CPM ctr current 1 2 d
+params: L=100e-6 fs=1e5 va=0.5 Rf=0.1
*
* generate d2 for CCM/DCM
Ed2 d2 0 table
+ {MIN(
+ L*fs*(v(ctr)-va*v(d))/Rf/(v(2)),
+ 1-v(d)
+ )} (0,0) (1,1)
*
Em1 m1 0 value={Rf*v(1)/L/fs}
Em2 m2 0 value={Rf*v(2)/L/fs}
*
* generate duty-ratio d (valid CCM and DCM operation)
*
Eduty d 0 table
+ {
+ 2*(v(ctr)*(v(d)+v(d2))
+ -v(current)-v(m2)*v(d2)*v(d2)/2)
+ /(v(m1)*v(d)+2*va*(v(d)+v(d2)))
+ } (0.01,0.01) (0.99,0.99)
*
.ends ; end of subcircuit CPM
**********************************************************
AppIicalion LxanpIe:
BucI Converler vilh Currenl-Mode ConlroI
Demonstrate how CCM/DCM averaged-switch model can be used
together with CCM/DCM averaged model of the current-mode controller
Use DC sweep simulation to show steady-state characteristics
including operation in DCM or CCM
Use AC simulation to show control-to-output responses compared for
duty-ratio control and current-mode control, in DCM or CCM
Use parametric sweep simulation to find the amplitude of the artificial
ramp to minimize input-to-output audio-susceptibility
Specifications:
Input V
g
= 28V, output V = 5-20V, 0.5-2A
Switching frequency f
s
=100kHz, inductance L = 35uH
Equivalent current-sense resistance R
f
= 1
Artificial-ramp amplitude V
a
= 0-3V
Buck Converter with Current-Mode Control
Example: Cpm-buck
10
R2 C1
100u
0.05
R1 L1
35uH
1
D
2
S
3
K
4
A
5
d
u
t
y
fs=100K
ccm-dcm1
U2
L=35uH
CTR
Vc
CURRENT
Rf iL
1
V
1
2
V
2
D
duty
va={Va}
Rf=1
CPM
U1
L=35uH
fs=100kHz
O
U
T
+
O
U
T
-
I
N
+
I
N
-
V(2x)
E4
EVALUE
OUT+
OUT-
IN+
IN-
i(L1)
E2
EVALUE
O
U
T
+
O
U
T
-
I
N
+
I
N
-
V(1)-V(2x) EVALUE
E3
PARAMETERS:
Va 1
+
-
Vc
DC=2V
+
-
DC=28V
Vg
VDB
2x
d
ctr
1
3
531.52mV
177.09mV
5.315V
BucI Converler vilh Currenl-Mode ConlroI
DC Sveep SinuIalion
(E) cpm-buck.dat
0.5V 1.0V 1.5V 2.0V 2.5V 3.0V
Vc V(d) 1-V(d) V(Xs.u) V(Xcpm.d2)
1.0V
0.8V
0.6V
0.4V
0.2V
0V
DCM CCM
u
d
d2
1-d
Duty ratio d, equivalent duty ratio u, and diode conduction
interval d
2
as functions of the control input V
c
BucI Converler vilh Currenl-Mode ConlroI
DC Sveep SinuIalion
(F) cpm-buck.dat
0.5V 1.0V 1.5V 2.0V 2.5V 3.0V
Vc I(L1) v(ctr)
3.0
2.5
2.0
1.5
1.0
0.5
0
iL
Vc=Rf*Ic
Average inductor current iL as a function of the control input V
c
BucI Converler vilh Currenl-Mode ConlroI
Irequency Responses in CCM
(H) cpm-buck.dat
10Hz 100Hz 1.0KHz 10KHz 100KHz
Frequency
DB(V(3)) DB(V(3)/v(d)) P(V(3)) P(V(3)/v(d))
100
50
0
-50
-100
-150
-200
Vc=2.0, CCM
v/d
v/vc
v/d
v/vc
MAGNITUDE
PHASE
Control-to-output frequency responses for duty-ratio control (v/d)
and current-mode control (v/v
c
). The converter operates in CCM.
BucI Converler vilh Currenl-Mode ConlroI
Irequency Responses in DCM
(H) cpm-buck.dat
10Hz 100Hz 1.0KHz 10KHz 100KHz
Frequency
DB(V(3)) DB(V(3)/v(d)) P(V(3)) P(V(3)/v(d))
50
0
-50
-100
-150
Vc=1.5, DCM
PHASE
MAGNITUDE
v/vc
v/d
v/vc
v/d
Control-to-output frequency responses for duty-ratio control (v/d)
and current-mode control (v/v
c
). The converter operates in DCM.
BucI Converler vilh Currenl-Mode ConlroI
Audio-suscepliliIily AnaIysis
Va=0.8, v/vg(0) = -62.848dB
(A) cpm-buck.dat
0 0.5 1.0 1.5 2.0
Va
VDB(3)
-20
-30
-40
-50
-60
-70
Audio-susceptibility v/v
g
as a function of the artificial-ramp amplitude V
a
Parametric sweep used to determine amplitude of the artificial ramp
V
a
to minimize input-to-output response (audio-susceptibility) v/v
g
.
. Averaged nodeIing of singIe-phase Iov-
harnonic reclifiers
Ideal rectifier
Averaged model obtained by averaging over switching period
Averaged model obtained by averaging over line period
Application examples:
- Power factor corrector based on boost converter operating in DCM
- Power factor corrector based on SEPIC with nonlinear-carrier control
Properties of the Ideal Rectifier
It is desired that the rectifier present a resistive load to the ac power
system. This leads to
unity power factor
ac line current has same waveshape as voltage
i
ac
(t) =
v
ac
(t)
R
e
R
e
is called the emulated resistance R
e
+

v
ac
(t)
i
ac
(t)
Control of power throughput
R
e
(v
control
)
+

v
ac
(t)
i
ac
(t)
v
control
P
av
=
V
ac,rms
2
R
e
(v
control
)
Power apparently consumed by R
e
is actually transferred to rectifier dc
output port. To control the amount
of output power, it must be possible
to adjust the value of R
e
.
Output port model
R
e
(v
control
)
+

v
ac
(t)
i
ac
(t)
v
control
v(t)
i(t)
+

p(t) = v
ac
2
/R
e
Ideal rectifier (LFR)
ac
input
dc
output
The ideal rectifier is
lossless and contains no
internal energy storage.
Hence, the
instantaneous input
power equals the
instantaneous output
power. Since the
instantaneous power is
independent of the dc
load characteristics, the
output port obeys a
power source
characteristic.
p(t) =
v
ac
2
(t)
R
e
(v
control
(t))
v(t)i(t) = p(t) =
v
ac
2
(t)
R
e
Equations of the ideal rectifier / LFR
i
ac
(t) =
v
ac
(t)
R
e
(v
control
)
v(t)i(t) = p(t)
p(t) =
v
ac
2
(t)
R
e
(v
control
(t))
V
rms
V
ac,rms
=
R
R
e
I
ac,rms
I
rms
=
R
R
e
Defining equations of the
ideal rectifier:
When connected to a
resistive load of value R, the
input and output rms voltages
and currents are related as
follows:
A switch network that is capable of satisfying the above (averaged)
equations can be employed in low-harmonic rectifier applications
Single-phase system with internal energy storage
v
ac
(t)
i
ac
(t)
R
e
+

Ideal rectifier (LFR)

C
i
2
(t) i
g
(t)
p
ac
(t)
T
s
v
g
(t)
i(t)
load
+
v(t)

p
load
(t) = VI = P
load
Energy storage
capacitor
v
C
(t)
+

Dcdc
converter
Energy storage capacitor
voltage v
C
(t) must be
independent of input and
output voltage waveforms, so
that it can vary according to
=
d
1
2
Cv
C
2
(t)
dt
= p
ac
(t) p
load
(t)
This system is capable of
Wide-bandwidth control of
output voltage
Wide-bandwidth control of
input current waveform
Internal independent energy
storage
Large signal model
averaged over switching period T
s
R
e
(v
control
) v
g
(t)
T
s
v
control
+

Ideal rectifier (LFR)

ac
input
dc
output
+

i
g
(t)
T
s
p(t)
T
s
i
2
(t)
T
s
v(t)
T
s
C Load
Ideal rectifier model, assuming that inner wide-bandwidth loop
operates ideally
High-frequency switching harmonics are removed via averaging
Ac line-frequency harmonics are included in model
Nonlinear and time-varying
Predictions of large-signal model
R
e
(v
control
) v
g
(t)
T
s
v
control
+

Ideal rectifier (LFR)

ac
input
dc
output
+

i
g
(t)
T
s
p(t)
T
s
i
2
(t)
T
s
v(t)
T
s
C Load
v
g
(t) = 2 v
g,rms
sin t
If the input voltage is
Then the
instantaneous power
is:
p(t)
T
s
=
v
g
(t)
T
s
2
R
e
(v
control
(t))
=
v
g,rms
2
R
e
(v
control
(t))
1 cos 2t
which contains a constant term plus a second-
harmonic term
Separation of power source into its constant and
time-varying components
+

i
2
(t)
T
s
v(t)
T
s
C Load
V
g,rms
2
R
e

V
g,rms
2
R
e
cos
2
2t
Rectifier output port
The second-harmonic variation in power leads to second-harmonic
variations in the output voltage and current
Removal of even harmonics via averaging
t
v(t)
v(t)
T
2L
v(t)
T
s
T
2L
=
1
2
2

Resulting averaged model

+

i
2
(t)
T
2L
v(t)
T
2L
C Load
V
g,rms
2
R
e
Rectifier output port
Time invariant model
Power source is nonlinear
Perturbation and linearization
v(t)
T
2L
= V + v(t)
i
2
(t)
T
2L
= I
2
+ i
2
(t)
v
g,rms
= V
g,rms
+ v
g,rms
(t)
v
control
(t) = V
control
+ v
control
(t)
V >> v(t)
I
2
>> i
2
(t)
V
g,rms
>> v
g,rms
(t)
V
control
>> v
control
(t)
Let with
The averaged model predicts that the rectifier output current is
i
2
(t)
T
2L
=
p(t)
T
2L
v(t)
T
2L
=
v
g,rms
2
(t)
R
e
(v
control
(t)) v(t)
T
2L
= f v
g,rms
(t), v(t)
T
2L
, v
control
(t))
Linearized result
I
2
+ i
2
(t) = g
2
v
g,rms
(t) + j
2
v(t)
v
control
(t)
r
2
g
2
=
df v
g,rms
, V, V
control
)
dv
g,rms
v
g,rms
= V
g,rms
=
2
R
e
(V
control
)
V
g,rms
V
where

1
r
2
=
df V
g,rms
, v
T
2L
, V
control
)
d v
T
2L
v
T
2L
= V
=
I
2
V
j
2
=
df V
g,rms
, V, v
control
)
dv
control
v
control
= V
control
=
V
g,rms
2
VR
e
2
(V
control
)
dR
e
(v
control
)
dv
control
v
control
= V
control
Small-signal equivalent circuit
C
Rectifier output port
r
2
g
2
v
g,rms
j
2
v
control
R
i
2
+

v
v(s)
v
control
(s)
= j
2
R||r
2
1
1 + sC R||r
2
v(s)
v
g,rms
(s)
= g
2
R||r
2
1
1 + sC R||r
2
Predicted transfer functions
Control-to-output
Line-to-output
Constant power load
v
ac
(t)
i
ac
(t)
R
e
+

Ideal rectifier (LFR)

C
i
2
(t) i
g
(t)
v
g
(t)
i(t)
load
+
v(t)

p
load
(t) = VI = P
load
Energy storage
capacitor
v
C
(t)
+

Dc-dc
converter
+

P
load
V
p
ac
(t)
T
s
Rectifier and dc-dc converter operate with same average power
Incremental resistance R of constant power load is negative, and is
R =
V
2
P
av
which is equal in magnitude and opposite in polarity to rectifier
incremental output resistance r
2
for all controllers except NLC
Transfer functions with constant power load
v(s)
v
control
(s)
=
j
2
sC
v(s)
v
g,rms
(s)
=
g
2
sC
When r
2
= R, the parallel combination r
2
|| R becomes equal to zero.
The small-signal transfer functions then reduce to
AppIicalion LxanpIe:
Iover-Iaclor Correclor Based on Boosl Converler
peraling in DCM
Objectives:
Example of how large-signal averaged-switch model can be used for
analysis and simulation of a power-factor corrector
Show examples of averaged pulse-width modulator model, and
implementation of closed-loop control
Use transient simulation to study start-up transient response of the PFC
and harmonic distortion of the AC line current in steady state
Specifications:
Input: 120Vrms, 50Hz. Output: 300VDC, 100W
Switching frequency: 100kHz
DCM Boosl IIC
L
v
line
i
line
+
_
v
g
+
_
V
C
o
+
_
v
co
i
g
= <i
L
>
L
v
line
i
line
i
s
+
_
v
g
+
_
V
o
C
o
+
_
v
co
i
g
= <i
L
>
i
d
R
e p(t)
<i
s
>
<i
d
>
Switching circuit model Averaged circuit model (in DCM)
) (
2
g e
g
e
g
g e
g
T
d
T
s g
v V R
v
R
v
v V
p
R
v
i i i
s s

+ +

,
_

V
v
R
v
i
g
e
g
g
1
1
s
e
T D
L
R
2
2

Line current distrortion due

to this term
Boost converter operates in DCM at constant duty ratio, constant frequency
DCM Boost PFC
Averaged
model of
the boost
rectifier
Averaged PWM model: d=v
m
/V
M
=0.5v
m
,
D
min
=0.1, D
max
=0.9 limits
Closed-loop output
voltage control
VAMPL=170
diode
D3
diode
D4
L1
200uH
0.2
R2
+
-
VCC
12V
10K R6
+
-
Vref
5V
10K
R4
R3
600K
C2 1u
0.9
0.1
0.5
+ -
Voffset
2V
diode
D2
diode
D1
1
+
3
-
2
V+
4
V-
11
U2A
LM324
+
-
Vac
FREQ=50
R5 3.3K
C1
150uF
{Rload}
R1
1
D
2
S
3
K
4
A
5
d
u
t
y
L=200uH
U1
ccm-dcm1
fs=100KHz
PARAMETERS:
Rload 900
V
m
d
output
PWM
DCM Boosl IIC: Slarl-Up Transienl
(A) dcm-boost-rectifier-closed-loop.dat
0s 50ms 100ms 150ms 200ms
Time
V(output)
400V
200V
0V
V(d)
0.8
0.4
0
100W load
50W load
Duty ratio d
100W load
50W load
Start-up transient response for full load and 50% load
DCM Boosl IIC:
AC Line Currenl Waveforns
(A) dcm-boost-rectifier-closed-loop.dat
180ms 185ms 190ms 195ms 200ms
Time I(Vac)
1.5A
1.0A
0.5A
0A
-0.5A
-1.0A
-1.5A
100W load
1st harmonic: 0.87A
3rd harmonic: 0.14A (16.4%)
THD: 16.4%
50W load
1st harmonic: 0.48A
3rd harmonic: 0.08A (16.2%)
THD: 16.2%
AC line current waveforms at full load and 50% load
DCM Boosl IIC:
AC Line Currenl Dislorlion in CCM
AC line current waveforms at full load (100W),
50% load, and 150% load
(A) dcm-boost-rectifier-closed-loop.dat
500ms 505ms 510ms 515ms 520ms
Time
I(Vac)
2.0A
0A
-2.0A
-4.0A
-6.0A
-8.0A
Converter operates in CCM
150W load
100W load
50W load
AppIicalion LxanpIe:
Sepic IIC vilh NLC ConlroI
Nonlinear-Carrier
Controller
R
s
i
s
i
s
+
v
m
voltage-loop
error amplifier
V
ref
AC line
voltage
120V, 60Hz
Magnetics 1F19 UU
53 turns
53 turns
#18
#18
136 turns #18
IRF840
1uF
2400uF
Active current shaping using Nonlinear Carrier Control method
Sepic converter has integrated magnetics designed for zero switching
ripple in the AC line current
Specifications:
Input: 90-120Vrms, 60Hz. Output: 48VDC, 200W
Switching frequency: 90kHz
AppIicalion LxanpIe:
Sepic IIC vilh NLC ConlroI
Objectives:
Show application of the CCM/DCM averaged-switch model in power-
factor correctors with active current shaping and closed-loop output
voltage control
Show average model implementation of a nonlinear pulse-width
modulator (NLC controller)
Compare average model predictions to experimental results:
AC line current waveshapes
Start-up and load transient responses
NLC ConlroIIer peralion
+

NLC generator
v
c
(t) = v
m
f(t/T
s
)
switch
current sensor
switch
drive
Q R
S
Q
v
m
v
c
(t)
v
q
(t) = R
s
< i
s
>
clock
d
i
s
[5A/div]
v
c
v
q
c(t)

,
_

s
s
m s
T
t
t
T
v T t f 1 ) / (
d
d
v i R
m
T
s s
s

1
m
T
s s
m
v i R
v
d
s
+

s
T
s g
i i
g
s
m
g
v
V R
v
i

,
_

V
v
d
d
g

1
Ideal current shaping
NLC Controller Model
Sepic PFC with NLC Control:
Simulation Model
Coupled-
inductor
model
NLC controller model
Closed-loop output
voltage control
diode
D2
diode
D3
diode
D4
diode
D1
+
-
Vsense
* *
1:n
Lm
2
3
4
1
n=1
transformer
T1
Lm=180uH
1
D
2
S
3
K
4
A
5
d
u
t
y
L=180uH
ccm-dcm1
U1
fs=90kHz
OUT+
OUT-
IN+
IN-
V(m)/(Rs*I(Vsense)+V(m))
E1
EVALUE
L-13-23
950uH
*
*
1
:
n
1 2
3 4
TX1 n=0.94
2400uF
C3
Rload
17
+
-
VAMPL=170
Vac
1
+
3
-
2
V+
4
V-
11
LM324
U2A
R3
18K
R2
68K
R4 15k C4
1uF
+ -
Vref
10.4V
+ -
Vcc
12V
C1
1uF
0
0
0 0
0
0
0
0
0
0
0 0
0
m
NLC controller
Sepic IIC vilh NLC ConlroI
LxperinenlaI vs. SinuIalion ResuIls
i
line
[2A/div]
Line current harmonics [1.6%/div]
3 5 7 9 11 13 15 17
0
2A
0A
-2A
i
line
Experiment
Simulation
i
line
[1A/div]
Line current harmonics [2.4%/div]
Experiment
Simulation
1A
0.5A
0 A
-0.5A
-1A
0
3 5 7 9 11 13 15 17
i
line
AC line current waveform and spectrum at 50W load (left) and
170W load (right)
Sepic IIC vilh NLC ConlroI
LxperinenlaI vs. SinuIalion ResuIls
-3A
v
o
v
m
i
line
50V
30V
10V
0V
3A
0A
v
m
v
o
i
line
[2A/div]
Experiment
Simulation
50W to 125W load transient in the Sepic PFC
Sepic IIC vilh NLC ConlroI
LxperinenlaI vs. SinuIalion ResuIls
v
g
v
m
i
line
200V
0V
3A
-3A
10V
0V
100V
0V
0A
v
o
v
o
v
m
v
g
i
line
[2A/div]
Experiment Simulation
Start-up transient in the Sepic PFC at 50W load
6. 5ummary
The averaged switch modeling approach: replace switch network with
an equivalent circuit that correctly predicts the low-frequency
components of the switch network terminal waveforms
Seminar addressed:
- PWM converters in continuous and discontinuous conduction modes
- PWM converters with current-programmed mode (CPM) control
- Single-phase low-harmonic rectifiers (power-factor correctors)
In each case, the large-signal averaged switch model can be used:
- to develop steady-state and (by linearization) small-signal circuit
models suitable for analysis
- to construct Spice-compatible model implementations suitable for
DC, Transient and AC simulations
A number of PSpice model implementation examples and converter
application examples were presented
7. BIb!Ingraphy
Selected books:
R.W. Erickson, Fundamentals of Power Electronics, Chpman & Hal, 1997.
Web page: http://ece-www.colorado.edu/~pwrelect/book/bookdir.html
J.G.Kassakian, M.F.Schlecht, G.C.Verghese, Principles of Power Electronics, Addison-Wesley, 1991.
A.Kislovski, R.Redl, N.Sokal, Dynamic Analysis of Switched-Mode DC/DC Converters, New York: Van
Nostrand Reinhold, 1994.
P.T. Krein, Elements of Power Electronics, Oxford University Press, 1998.
Daniel M. Mitchel, DC-DC Switching Regulator Analysis, New York: McGraw-Hill, 1988.
N.Mohan, T.Undeland, W.Robbins, Power Electronics: Converters, Applications and Design, Second Edition,
John Wiley & Sons, 1995.
S.M. Sandler, SMPS Simulation with Spice 3, McGraw Hill, 199.
BilIiography (conlinued)
Selected papers on averaged modeling of switching power converters
R. M. Bass, J. Sun, Averaging under large-signal conditions, IEEE PESC 1998, pp. 630-632.
R.Erickson, M.Madigan, S.Singer, Design of a simple high power factor rectifier based on the flyback
converter, IEEE APEC, 1990, pp.792-801.
P. Krein, et al, "On the Use of Averaging for the Analysis of Power Electronic Systems," IEEE Transactions on
Power Electronics, Vol. 5, No. 2, pp 182-190, April
1990.
K.Mahabir, G.Verghese, J.Thottuvelil, A.Heyman, Linear averaged and sampled data models for large signal
control of high power factor AC-DC converters, IEEE PESC, 1990, pp. 372-381.
D.Maksimovic, S.Cuk, ``A unified analysis of PWM converters in discontinuous modes,'' IEEE Trans. on Power
Electronics, Vol.6, No.3, July 1991.
D.~Maksimovic, Y.Jang and R.Erickson, ``Nonlinear-carrier control for high power factor boost rectifiers,'' IEEE
Transactions on Power Electronics, Vol.11, No.4, July 1996, pp.578-584.
R.D.Middlebrook and Slobodan Cuk, A general unified approach to modeling switching-converter power
stages, International Journal of Electronics, Vol.42, No.6, pp.521-550, June 1977.
R.D.Middlebrook, Topics in multiple-loop regulators and current-mode programming, IEEE PESC, 1985, pp.
716-732.
BilIiography (conlinued)
Selected papers on averaged modeling of switching power converter (continued)
R.D.Middlebrook, Modeling current programmed buck and boost regulators, IEEE Trans. On Power
Electronics, Vol.4, No.1, January 1989, pp.36-52.
S.R.Sanders, G.C.Verghese, Synthesis of averaged circuit models for switched power converters, IEEE
Transactions on Circuits and Systems, Vol.38, No.8, pp.905-915, August 1991.
S.Singer, R.W. Erickson, Power source element and its properties, IEE Proceedings - Circuits Devices
Systems, Vol.141, Np.3, pp.220-226, June 1994.
J.Sun, D.M.Mitchel, M.Greuel, P.T.Krain, R.M.Bass, Averaged modeling of PWM converters in discontinuous
conduction mode: a reexamination, IEEE PESC 1998, pp.615-622.
J.Sun, D.M.Mitchel, M.Greuel, P.T.Krain, R.M.Bass, Averaged models for PWM converters in discontinuous
conduction mode, HFPC 1998.
J.Sun, R.M.Bass, Modeling and practical design issues for average current control, IEEE APEC 1999.
R. Tymerski and V. Vorperian, Generation, classification and analysis of switched-mode DC-to-Dcconverters
by the use of converter cells, INTELEC 1986, pp.181-195.
E. Van Dijk, H.J.N.Spruijt, D.M.OSullivan, J.B.Klaassens, PWM switch modeling of DC/DC converters, IEEE
Transactions on Power Electronics, Vol.10, No.6, November 1995, pp. 659-665.
BilIiography (conlinued)
Selected papers on averaged modeling of switching power converter (continued)
G. Verghese, C. Bruzos, K. Mahabir, Averaged and sampled-data models for current mode control: a
reexamination, IEEE PESC, 1989, pp.484-491.
V.Vorperian, R.Tymerski, F.C.Lee, Equivalent circuit models for resonant and PWM switches, IEEE
Transactions on Power Electronics, Vol.4, No.2, pp.205-214.
V.Vorperian, Simplified analysis of PWM converters using the model of the PWM switch: Parts I and II, IEEE
Transactions on Aerospace and Electronic Systems, Vol.AES-26, pp.490-505, May 1990.
G.W.Wester and R.D.Middlebrook, Low-frequency characterization of switched Dc-Dc converters, IEEE
Transactions on Aerospace and Electronic Systems, Vol.AES-9, pp.376-385, May 1973.
R.~Zane, D.~Maksimovic, ``Nonlinear-carrier control for high-power-factor rectifiers based on flyback, Cuk or
Sepic converters,' Proc. IEEE APEC, March 3-7, 1996, San Jose, CA, pp.814-820.
BilIiography (conlinued)
Selected papers on averaged model implementation for computer simulation
V. Bello, "Computer Aided Analysis of Switching Regulators Using SPICE2," IEEE PESC, 1980 Record, pp 3-
11.
V. Bello, "Using The SPICE2 CAD Package for Easy Simulation of Switching Regulators in Both Continuous
and Discontinuous Conduction Modes," Powercon 8, April, 1981, pp H3-1-14.
V. Bello, "Using the SPICE2 CAD Package to Simulate and Design the Current Mode Converter," Powercon
11, April 1984.
Y. Amran, F. Huliehel, S. Ben-Yaakov, A unified SPICE compatible average model of PWM converters, IEEE
Transactions on Power Electronics, Vol. 6, No. 4, pp. 585-594, 1991.
S. Ben-Yaakov, Average simulation of PWM converters by direct implementation of behavioral relationships,
IEEE APEC, pp.510-516, 1993.
S.Ben-Yaakov, D.Adar, Average models as tools for studying dynamics of switch mode DC-DC converters,
IEEE PESC 1994, pp.1369-1376
S. Ben-Yaakov, Z. Gaaton, Generic SPICE compatible model of current feedback in switch mode converters,
Electronics Letters, Vol. 28, No. 14, 2nd July 1992.
V.M.Canalli, J.A.Cobos, J.A.Oliver, J.Uceda, Bihavioral large signal averaged model for DC/DC switching
power converters, IEEE PESC 1996.
BilIiography (conlinued)
Selected papers on averaged model implementation for computer simulation
D. Edry, M. Hadar, O. Mor, S. Ben-Yaakov, A SPICE compatible model of tapped inductor PWM converter,
IEEE APEC 1994, pp.1035-1041.
S. Hageman, "Behavioral Modeling and PSPICE Simulate SMPS Control Loops, PCIM, April 1990, pp 13-24
and May 1990, pp 47-50.
N. Jayaram, D. Maksimovic, Power factor correctors based on coupled-inductor Sepic and Cuk converters
with nonlinear-carrier control, IEEE APEC 1998.
D. Kimhi, S. Ben-Yaakov, A SPICE model for current mode PWM converters operating under continuous
inductor current conditions, IEEE Transactions on Power Electronics, Vol.6, No.2, pp.281-286, 1991.
R. Michelet and W. Roehr, "Evaluating Power Supply Designs with CAE Models APEC 89, pp 323-334.
D. Monteith and D. Salcedo, "Modeling Feedforward PWM Circuits Using the Nonlinear Function Capabilities
of SPICE II," Powercon 10,March 1983.