Common Flash Memory Interface (CFI) Controller

Core Overview:The
Common Flash MemoryInterface Controller IP Core is a hardware component that facilitates the use of flash memory devices present on the Altera Cyclone FPGA board. The document describes thefunctionality ofCFIController IP Core.

Functional Description:The CFI interface diagram is shown in Figure 1. It consists of user

interface signals(bus signals) on the left-hand side, and a flash memory chip signals on the right-hand side. The signals on the left-hand side are control signals, Data signals and Address signals that allow the flashmemory to be read and write.

top_clk top_rst_n top_read top_write top_ cs top_address_in top_write_data top_read_data top_wt_req top_beginburst top_burst_count top_vio top_address_out top_ce_n

CFI Controller

top_oe_n top_we_n top_ry/by

Figure 1.CFI Controller

Pin Description:
Inputs :Inputs to the CFI controller.
top_clk: clock to the controller. top_rst_n: Active low reset to the controller. top_write , read ,chipselect : The other output signals are 1-bit wide each, and control data transfer. top_address_in, top_write_data, top_read_data : Input signals to the controller from the which consists of data &adress . top_wt_req: Controller is busy when it is set to 0, controller is ready when it is set to 1.

Outputs :Outputs to the CFI controller.

top_vio:Thisis a bidirectionalsignal that carries the data to and from the flash memory deviceto the controller top_ address_out:signal specifies an address in the memory to be accessed. top_Oe_n, top_we_n, top_ce_n : The other output signals to the memory to enable the chip and bidirectional data signal. top_ry_by: Flash memory is ready when it is in active high else it is busy.

Core Diagram:

clk
rst_n
rs_ry_by rs_wt_data rs_address rs_rd_data

cfi_ce cfi_do cfi_address Controller cfi_oe cfi_we cfi_ry_by cfi_di

write read begin_burst cs addressrs_ write_data read_data wt_req burst_count Register Set

rs_wt_n rs_rd_n rs_cs_n rs_beginburst rs_burst_count

Register Set: Control Register

Data Register (Input) Data Register(Output) Address Register Reset Register

Control Register:The Control register is 8 bit wide. The first (LSB) three bits are used in control register. The 0th bit is high it indicates, Controller will do reading operation. If 1st bit is high it indicates, controller will do writing operation. If 2nd bit is high it indicates it is busy. Data Register (Input):It is a 15 bit register, It gets the data from bus,Data in the register is fromthe controller. Data Register (Output): It is a 15 bit register, It gets the data from the controller,Data in the register is from bus for every read. Address Register: It is a 25 bit register, It indicates read address and write address. Reset Register: It is a Single bit register,which receives reset signal from the bus. The CFIController Core consists of bus interface signals on the left-hand side, and a flash memory chip signals on the right-hand side. The signals from the bus are storing in a register set. The stored signals in the register set are used to allow the flashmemory to be read, written and erased.The flash

memory controller signals shown on the right hand side connect to the flash memory device on a FPGA board.

Signal Description(Top Block):

Name Top_address_out top_vio top_ce_n top_oe_n top _we_n top _rst_n top _wt_req top clk top rst_n top read top write top_cs top_address_in top_write_data top_read_data top_ry_by Beginburst Burst_count Size 25 15 1 1 1 1 1 1 1 1 1 1 32 32 32 1 1 8 Description Input address to the memory from the controller Data inputs/outputs to the controller Chip Enable is an active low output from the controller, which enables the memory Output Enable is active low output from the controller, which controls the read operation. Write Enable is active low output from the controller, which controls the write operation. Reset is an active low output. Read/Busy,If the input is high(1) it indicates controller is ready,If it is low(0) it indicates it is busy. Input clock from the bus to the controller Reset is an active low input which resets the controller. Read is an input signal which initiate the Controller to read It is an input signal which initiate the Controller to write from the memory Which stores in register to enable the memory Address to the register where to read ,write and erase Input data to the register to write in to memory Output Data from the memory High (1) Indicates memory is ready to perform the operation Low (0) Indicates memory is busy, it is performing previous operation Enables the Burst count It indicates size of continous read /write.