The University of Victoria Faculty of Engineering CENG499A

Final Project Report

Wireless ECG/EKG Monitoring System

By Matthew Green Dennis Leote Kevin Harmon

Submitted to Dr. Pan Agathoklis July 28, 2006

Table of Contents Abstract ------------------------------------------------------------------------------ Page 1 Objective ----------------------------------------------------------------------------- Page 2 Project Design ----------------------------------------------------------------------- Page 3 Hardware ---------------------------------------------------------------------------- Page 3 The Power Supply --------------------------------------------------------- Page 4 Instrumentation Amplifier ----------------------------------------------- Page 5 Operational Amplifiers --------------------------------------------------- Page 5 Filters ------------------------------------------------------------------------ Page 6 Microcontroller ------------------------------------------------------------ Page 8 Transceivers ---------------------------------------------------------------- Page 8 MAX232 -------------------------------------------------------------------- Page 9 Software ------------------------------------------------------------------------------ Page 10 Transmitter Module ------------------------------------------------------- Page 10 Programming the PIC16F877A --------------------------------- Page 10 Analog to Digital Conversion (ADC) ---------------- Page 10 Sampling Rate -------------------------------------------- Page 11 Formatting ------------------------------------------------ Page 11 SPI --------------------------------------------------------- Page 11 RF Transmitter ---------------------------------------------------- Page 12 Receiver Module ---------------------------------------------------------- Page 12 RF Receiver ------------------------------------------------------- Page 12 PC Display ------------------------------------------------------------------ Page 13

Receiving the Data ------------------------------------------------ Page 14 X Plot --------------------------------------------------------------- Page 14 Y Plot --------------------------------------------------------------- Page 15 Reliability Considerations ------------------------------------------------ Page 15 Discussion and Recommendations ----------------------------------------------- Page 15 References ----------------------------------------------------------------------------Page 17

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List of Tables and Figures Figure 1 ECG/EKG Lead Placement ------------------------------------------- Page 1 Figure 2 Ideal I-Waveform ------------------------------------------------------ Page 1 Figure 3 Present Day ECG -------------------------------------------------------Page 2 Figure 4 Excessive Amount of Wires in the Operating Room -------------- Page 2 Figure 5 Block Diagram of Transmitter and Receiver ----------------------- Page 3 Figure 6 Power Supply Circuit ------------------------------------------------- Page 4 Figure 7 An Instrumentation Amplifier ---------------------------------------- Page 5 Figure 8 The AD620 ------------------------------------------------------------- Page 5 Figure 9 ECG Waveform with 60 Hz not removed -------------------------- Page 6 Figure 10 High Pass RC Filter -------------------------------------------------- Page 6 Figure 11 Low Pass RC Filter --------------------------------------------------- Page 6 Figure 12 2nd Order Active Butterworth Filter -------------------------------- Page 7 Figure 13 RS232 voltages --------------------------------------------------------Page 9 Figure 14 Transmitter Module Block Diagram ------------------------------- Page 10 Figure 15 Activity Diagram for Transmitter Module ------------------------ Page 12 Figure 16 Receiver Module Block Diagram ---------------------------------- Page 12 Figure 17 Single Lead Display (Lead I) --------------------------------------- Page 13 Figure 18 Multiple Lead Display -----------------------------------------------Page 14

Table 1 Voltage Requirements ------------------------------------------------- Page 4 Table 2 Filter Values ------------------------------------------------------------- Page 7 Table 3 Data Format -------------------------------------------------------------- Page 11

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Abstract In the human body, the heart is responsible for pumping oxygen carrying blood to the entire body. To do this, it emits a small electrical charge that will cause the muscles around the heart to contract in a sequential way such that the blood is pumped through arteries to the intended tissues. If there are deficiencies or abnormalities, the individual may be susceptible to serious health issues including cardiac arrest. Care givers in hospitals world wide must be able to monitor these electrical charges and, in doing so, be able to predict complications before they cause serious harm. To do this, a device called an electrocardiogram (ECG/EKG) is used. An ECG involves placing small pads in a triangular fashion on the patients chest, with the perimeter of the triangle completely encompassing the heart (Figure 1). The lead placements are labelled according to their location on the human body; Left Arm (LA), Right Arm (RA) and Left Leg (LL). The corresponding waveforms are numbered using Roman numerals. These pads are actually small leads connected back to a monitoring system that will measure the potential voltage differences around the heart. Figure 2 depicts an ideal IWaveform taken from a healthy human body. When these results are displayed, the doctors and nurses will be able to verify proper operation or predict possible complications.

Figure 1 ECG/EKG Lead Placement Figure 2 Ideal I-Waveform

Objective As mentioned above, currently the ECG/EKG machines consist of a minimum of 3 pads being placed on the body. These pads are wired back to a monitoring station where all of the required data manipulation is performed before displaying the results on a monitor. The main problem with the current method of monitoring a patients heart is very awkward and restricting. The leads are constantly being dislodged from the patient by the nurses, doctors, and even the patient themselves. This causes complications because it appears to the monitoring station that the patient is going into cardiac arrest. (Figures 3 & 4 show a typical operating room with an excess of wires)

Figure 3 Present Day ECG

Figure 4 Excessive Amount of Wires in the Operating Room Another problem with the current system is that the mobility of the care givers is limited due to the number of wires connecting the patient to various monitoring equipment. It is not possible for a nurse or doctor to completely walk around the patient without having to navigate the wires. A solution to this would be to make the hospital utilize wireless data transmission as much as possible to eliminate the need for wires. This process is currently being experimented with. Currently there are various wireless applications in use in the hospital industry. The most common are wireless pulse oxymetry, a method for

measuring the oxygen content in the blood. Another example is wireless temperature sensors in which the patient swallows a small transponder that will constantly transmit the bodys core temperature. The objective of this project is to design a Wireless ECG Monitoring System. This product will reliably measure the electrical activity around the heart and transmit this data to a receiver connected to a PC. The data will then be displayed on the PC in the same manner that the current method already does. Project Design This project was split into two main tasks, hardware and software. It is the responsibility of the hardware to collect and compare the data, filter out the harmful 60 Hz signals and transmit the data. It is the softwares responsibilities to digitize the signal, package the data and synchronize the receiver and the transmitter. Hardware As mentioned above, the hardware is responsible for capturing and isolating the signal. The hardware was divided up into stages; the power supply, instrumentation amplifiers, operational amplifiers, filters, analog to digital converters, microcontroller, transceivers and a MAX232. Figure 5 shows a block diagram of how the transmitter and receiver are configured. The schematics and PCB layout are attached in Appendix A.

Figure 5 Block Diagram of Transmitter and Receiver

The Power Supply To supply power to the wireless transmitter of this project, a 12 Volt battery was chosen. Table 1 shows a list of all various components and their minimum input voltages. Device Instrumentation Amplifiers Operational Amplifiers Microcontroller MAX232 Transceiver Vmin 2.3 -18 Volts 18 Volts 2.0 5.5 Volts 0.3 6 Volts 3 Volts

Table 1 Voltage Requirements To guarantee the microcontroller received the required 5 volts, a voltage regulator was used, which required a minimum of 7 volts. Another issue that needed to be resolved was the DC offset. Since the typical ECG wave will contain both positive and negative values, it was important to bias the signal such that the ADC (analog to digital converter) would only see a level between zero and five volts. To accomplish this, a small power supply was designed (Figure 6) using zener diodes. Point A is regulated by the 5.1V Zener Diode. This level would be used as a virtual ground reference for the instrumentation and operational amplifier stages. The benefit of this is that the amplifier stage would have supply voltage of +6.9V and 5.1V. This allowed the signal to be shifted slightly closer to ground. Point B, which is regulated to 3.3V, supplies the ground reference for the microcontroller stage. This leaves 8.7V for the voltage regulator. It had to be slightly below the reference voltage for the amplifiers to compensate for the signal when it dips below zero volts. The signal from the amplifiers can now be tuned to range from 0 to 5 volts at the ADC. Figure 6 Power Supply Circuit

Instrumentation Amplifier To measure the difference in voltage between any two points on the human body, we used an instrumentation amplifier made by Analog Devices, called an AD620 (Data Sheets Attached in Appendix B). An instrumentation amplifier is a special type of differential amplifier that will amplify the difference between its two inputs (Figure 7). The gain can be set by adjusting only one resistor, Rgain. The resulting output will be:

Vout = (V2 V1 )(1 +

R R gain

Figure 7 An Instrumentation Amplifier The AD620 is an instrumentation amplifier that has been combined in an integrated circuit. The benefit of this is that internal resistor values (R) are all perfectly matched. The gain can still be set by adjusting the one resistor between pins 1 and 8.

Figure 8 The AD620 Operational Amplifiers The signal that is being analyzed on the individuals chest has a typical maximum value of 1mV. To make this useful, the signal would need to be amplified to approximately 5Vpp, which equates to a gain of roughly 5000. The AD620 does offer a certain amount of gain; however it was observed that it functioned best when the gain was kept quite low. We therefore divided up the amplification into 2 stages. The first was done using the AD620 and the second done using a non-inverting op-amp. We chose the gain to be 5 for the first stage and 1000 2000 for the next. We included a potentiometer in the feedback loop of the op-amp to allow for some adjustment to the gain as necessary.

Filters The line interference (the 60Hz signal from the power lines) is abundant in the ECG signal. The human body acts like a giant antenna to this frequency, and the amplitude of the noise is roughly the same size of the ECG signal. It is therefore very difficult to monitor the ECG wave through the noise. Figure 9 shows a typical display of an ECG signal if the 60 Hz noise has not been removed.

Figure 9 ECG Waveform with 60 Hz not removed The actual signal that is measured on the human body is in the range of 1-2 mV. The useful information is in the frequency range of 1-250 Hz, although the most important data is below 40Hz. It is therefore desirable to filter out all of unwanted signals. To do this some 4 stages of filtering was used. The intended result was to produce a Band Pass Filter with the pass frequency between 1 - 40Hz. The first stage of filtering was done prior to any amplification. It was a simple high pass filter (HPF) that was designed using a simple RC circuit (Figure 10). This pre-filter was designed to eliminate all of the low frequency noise. It was designed with a cut-off frequency of 0.5 Hz.

f cutoff =

1 2RC

Figure 11 Low Pass RC Filter Figure 10 High Pass RC Filter

To eliminate the 60 Hz signal, a 4th order low pass filter (LPF) was used. This was designed by using a 1st order RC filter in series with a 2nd order Butterworth Filter and finally another the 1st order RC circuit. The RC circuit (Figure 11) is very similar to the HPF defined above. In fact the cut-off frequency is calculated the same way. These were designed to eliminate signals above 40Hz.

The Butterworth Filter (Figure 12) is an active filter that uses an op-amp to help get rid of the noise. All filters will attenuate frequencies above and below the desired cut-off frequency. The goal is to pick a filter that will be the least damaging to the desired signal while offering maximum filtering to the unwanted signal. The benefit of the Butterworth is that it will have a much more accurate cut-off frequency. It will therefore allow for more of the desired signal to get through unscathed.

f cutoff =

1 2 R1 R2 C1C 2

Figure 12 2nd Order Active Butterworth Filter

The filter values were chosen according to the above formulas. In practice, however, these values were only helpful in getting us close to the desired signal. The actual values used were found by using a trial and error method. Various values were tested until the best signal resulted. The final values of our filters were: Filter # 1 2 3 Filter Type Passive RC Active Butterworth Passive RC Filter Order 1 2 1 Cut-off Frequency 20 Hz 61.4 Hz 35 Hz

Table 2 Filter Values

Microcontroller

The microcontroller performed all of the decision making processes. It was responsible for the analog to digital conversion (ADC), data packaging and transceiver synchronization. Refer to the following section on software for more information about this. The microcontroller used was a PIC16F877. The main reason this microcontroller was used was because we were most familiar with it. The main features that it has that made it quite useful are: Synchronous Serial Port with SPI In circuit programming via RS232 10 bit ADC Universal Synchronous Asynchronous Receiver Transmitter (USART) Low operating current < 0.6 mA 3 timers Simple (35 single word instructions to learn)

Transceivers

To transmit and receive all of the data, a single chip transceiver was chosen. The nRF24L01 by Nordic Semiconductor was used. This was chosen because of its wide range of features: Operates in the free to air ISM frequency band at 2.45 GHz Built in power amplifier Fully integrated frequency synthesizer Receiver chain with demodulator Crystal oscillator and modulator ShockBurstTM for low power operation Automatic CRC and preamble generation Automatic retransmission of data packet SPI interface Low current consumption Carrier detect for listen before transmit protocol Adjustable transmit power

MAX232

The final piece of hardware that was involved in the design of the wireless ECG machine was the MAX232. This IC is used to convert TTL to RS232 and vice versa. RS232 data will range from -5V to -15V for a logical high and +5V to +15V for a logical low (Figure 13). The microcontroller will output data in the range of 0-5V (TTL). The data must therefore be buffered before the two devices will be able to communicate with one another.

Figure 13 RS232 voltages

The MAX232 buffers the signal in both directions allowing the microcontroller to communicate with the PC. The data can now be passed to the PC and displayed on the graphic user interface (GUI)

Software

Once the electrical potential difference between leads has been acquired, the signal must then be converted to the digital domain and communicated to the monitor display. The software component of the ECG monitor includes processing the signal with the PIC 16f877A microprocessor, transmitting the signal to the display using the Nordic nRF24L01 transceiver modules and displaying the information on a PC oscilloscope application. The software was written in C for the microprocessor and in Basic to write the display application. The C compiler used was Hi-Tech C Trial version from Hi-Tech Software. The display application was designed using Visual Basic 6.0 by Microsoft.
Transmitter Module

The transmitter module is responsible for obtaining and converting the analog ECG signal into an 8-bit digital representation. It is also responsible for formatting and transmitting the data. The transmitter module is within the immediate proximity of the patient being monitored. As the system diagram presented in figure 1 shows, there are four main steps required to transmit the ECG signal.

PIC 16f877A

ADC Analog DAQ

timing & Formatting

SPI
nRF24L0 1 TX

Figure 14 Transmitter Module Block Diagram Programming the PIC 16f877A Analog to Digital Conversion (ADC)

The amplified ECG signal is fed into the on-board ADC of the PIC. The PIC is capable of 10-bit resolution but an 8-bit digital representation provides enough accuracy and reduces the bit-rate by half. The three analog leads each have their own ADC channel and are sampled sequentially.

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Sampling Rate

The sampling rate was determined by observing the highest frequency component of the ECG signal, the QRS complex as depicted in figure 2, and using the Nyquist criteria. The QRS complex has a possible range of frequencies between 12 Hz and 28 Hz. The Nyquist frequency is thus taken to be 28 Hz and a sampling rate of 2 * Nyquist frequency = 56 Hz must be observed. A sampling rate of 2 KHz was used for increased accuracy. The timing was accomplished manually using delay routines that wait 500us between sampling.
Formatting

The data obtained from the ADC is bundled into an array of 30 bytes. This is done to conform to the Enhanced ShockburstTM protocol employed by the nRF24L01 transceiver module. Enhanced ShockburstTM allows for packets containing up to 30 bytes of data. To maximize the ratio of data bits to total bits in a packet and thus increase efficiency, the full 30 bytes allowed was utilized. The format of used in constructing the 30-byte array is shown in Table 3 below. A/D A/D A/D Chan1 Chan2 Chan2 Sample 1 Sample 1 Sample 1

...

A/D A/D Chan1 Chan2 Sample 30 Sample 30

A/D Chan2 Sample 30

Table 3 Data Format SPI

To communicate with the nRF24L01 transceiver module, the Serial Port Interface (SPI) module on the PIC was used. The SPI mode allows 8 bits of data to be synchronously transmitted and received simultaneously. The SPI was configured with the following parameters: Master Mode PIC is master with Clock as output Clock Polarity Idle state for clock is a low level Clock rate 1.25 MHz (fosc / 16). Data Sampling Input data sampled at middle of data output time

The activity diagram shown in figure depicts the general process followed by the PIC microprocessor.

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A/D Conver

Wait 500 us [array not full]

Three channel conversion complete Store Data

[array full]

Trans mit

Figure 15 Activity Diagram for Transmitter Module RF Transmitter

The nRF24L01 transceivers are configured to transmit 2Mbps at a frequency of 2.45GHz, within the ISM band. The data is encoded using Enhanced ShockburstTM (refer to nRF24L01 datasheet for detailed description).
Receiver Module

The process of receiving the digital data from the patient is the responsibility of the receiver module. The receiver is connected to a PC for display. As the system diagram presented in figure 16 shows, there are four main components required to receive before the data can be sent to the PC.

PIC 16f877A

SPI Nf24L0 1 Rx

Pars ing

U A R T

PC Display

Figure 16 Receiver Module Block Diagram RF Receiver

The nRF24L01 transceiver configured to perform as a receiver is much the same as the transmitter with the same parameters. Only one data pipe is used to transfer the data. This is in contrast to using a separate data pipe for each lead of the ECG. The reasoning behind this is that there is less overhead involved by eliminating the need to continuously change between data pipes.

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The data is transferred from the transceiver to the PIC via an SPI interface. The data is received in the format described in figure 16 and the 30 bytes of data is traversed beginning with byte 0. As each byte is received, the data is sent to the PC through the PICs on-board USART module at a baud rate of 115.2 kbps. The data is transmitted at regular intervals of 500 us which corresponds to the sampling rate.
PC display

The ECG signal is displayed on a PC through a basic oscilloscope application. The application was written in Visual Basic is included on the project CD as ECGMonitor.exe. The application includes one control bar for rescaling the time interval displayed.

Figure 17 Single Lead Display (Lead I)

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Figure 18 Multiple Lead Display Receiving the Data

The data is received through the serial port using COMM 2 at a baud rate of 115.2 kbps in 500us intervals. The application receives the data for the three leads of the ECG signal continuously in the following order: LeadI data byte, LeadII data byte, LeadIII, data byte. As the data is received, the appropriate display area is updated.
X Plot

The display is meant to behave as an oscilloscope although limited in functionality. To observe the ECG signal moving in time from the left to right, the x-coordinate is incremented with each new data value received. A scale factor controls the rate that the screen is refreshed. Horizontal scaling provides a means of controlling the number of pulses displayed. The person observing the signal has limited control over how long it takes the ECG signal to pan the width of the display through a scroll bar located directly beneath the display. The horizontal range was chosen to be able to display 2 beats. Heart rates can vary between 40 and 240 beats per minute or 1.5 and 0.25 seconds per beat respectively so the refresh rate was chosen to vary between 0.125 sec and 3 sec. To achieve refresh rates

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wihthin0.125 sec and 3 sec, the display width was set to be between 500 and 6000 pixels. The scroll bar controls this scale factor
Y Plot

The y-coordinate is obtained directly from the incoming data. Since the incoming data is within the range of 0 to 255, the vertical scaling for each lead translates to the same range.
Reliability Considerations

The ECG monitor needs to be very reliable considering its application in the medical field. The transmission frequency of 2.45 GHz is within the ISM band which is the band reserved for non-commercial use of RF electromagnetic fields for industrial, scientific and medical purposes. To avoid interference and loss of data, the nRF24L01 transceiver modules are capable of addressing up to six data pipes per module. In addition, reliability is ensured in the form of error detection and correction. Each data packet includes one byte for a cyclic redundancy check (CRC) to detect the presence of errors. Upon detection of any errors, a retransmission is requested to recover the data that may have been lost. Up to 15 retransmissions will be requested before finally discarding the data packet and carry on. The system can handle up to four packet losses and still maintain the integrity of the displayed signal. Testing was performed to determine the range with which the transceivers could reliable operate within, i.e. 0 packet loss. The methodology used was to observe the number lost packets in software at various distances. A radius of up to 5m found to be reliable. This was the target radius since this is roughly the upper limit on the distance between transmitter and receiver in an operating room.
Discussions & Recommendations

The Wireless ECG/EKG Monitoring System was designed and built, and was very successful. A few modifications would be implemented if time permitted. The first and most obvious change involves the circuit board. It was very big and awkward. It served its purpose as a prototype board. However, if this product were to got to production, the board would need to be re-designed into a smaller package using surface mount components. Next time, the filtering would be done digitally using a DSP chip. This would allow for much more accurate filtering using an FIR or Wavelets. The final change that would be considered would be to allow for some sort of automatic adjustments of the gain. Every individual has a unique heartbeat. The amplitudes will vary from person to person. The current configuration allows the gain to be adjusted

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manually, but this is a slow and tedious task. Next time the gain would be adjusted in firmware. This would be much faster and more accurate. The overall performance of this project was excellent. There was positive feedback from the judges, and we were awarded 3rd prize for our efforts. Below are a series of photos from the demonstration.

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References

Robert M. Berne and Matthew N. Levy, Cardiovascular Physiology 2nd Edition The C.V. Mosby Company, St. Louis 1972
National Semiconductor - LM741 Operational Amplifier Datasheet Analog Devices AD620 Instrumentation Amplifier Datasheet Nordic Semiconductor Single chip 433/868/915 MHz Transceiver nRF905 Dallas Semiconductor - +5V-Powered, Multichannel RS-232 Drivers/Receivers datasheet Microchip - PIC16F87X 28/40-Pin 8-Bit CMOS FLASH Microcontrollers Datasheet

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Appendix A PCB Files

+6V R2 1K R1 1K RA LA Vref (micro)

R3 1K

R15 Res1 10K +6V 7 R18 200K

C13 +6V 100nF 7 U4 8 2 R21 3.9K C4 1uF C5 1uF R24 82K R27 82K C10 10nF 6 3 5 1 4 LM741 -6V C16 100nF R30 45K A Lead I

+6V 7 1 D2 3.3 V Zener -6V 2 6 3 -6V AD620AN R6 2.2K R12 1K 5 4 Cap Pol3 100uF U1 8 2 C1 3 1

U7 8 6 5 4 -6V R9 1K LM741

D1 5.1V Zener -6V A

R16 10K R19 200K 1K +6V 7 JP1 1 2 3 4 5 6 Header 6H +6V -6V LL LA RA RA LL 1 2 6 3 -6V AD620AN R7 2.2K R13 1K 4 5 4 Cap Pol3 100uF 1 LM741 -6V +6V 7 U2 8 C2 3 5 2 6 100nF U8 8 R22 3.9K C6 1uF C7 1uF R25 82K R28 82K C11 10nF 2 6 3 5 1 4 LM741 -6V

R4 1K

C14 +6V 7 U5 8

R31 45K Lead II C17 100nF

R10 1K

R5 1K 7 +6V 7 B LA LL 1 2 6 3 -6V AD620AN R8 2.2K 4 5 4 Cap Pol3 100uF 1 R14 1K U3 8 C3 3 2

R17 10K +6V

R20 200K

C15 +6V 100nF 7 U6 8 2 R23 3.9K C8 1uF C9 1uF R26 82K R29 82K C12 10nF 6 3 5 1 4 LM741 -6V C18 100nF R32 45K Lead III B

U9 8 6 5 LM741

-6V

R11 1K

C23 0.1uF

U11 C25 VDD VDD R33 4.7K OSC1 1 C C20 22pF 2 XTAL1 C19 22pF U10 Vref (micro) Vref (micro) OSC1 MCLR! 13 1 OSC1/CLKI MCLR/VPP VDD VDD OSC2/CLKO Lead I Lead II VDD R34 4.7K MCLR! D3 SW1 SW-PB C27 0.1uF IRQ 33 34 35 36 37 38 39 40 12 31 RB0/INT RB1 RB2 RB3 RB4 RB5 RB6 RB7 VSS VSS PIC16C65-20I/P Lead III 2 3 4 5 6 7 RA0 RA1 RA2 RA3 RA4/T0CKI RA5/SS RC0/T1OSI/T1CKI RC1/T1OSO/CCP2 RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT RD0/PSP0 RD1/PSP1 RD2/PSP2 RD3/PSP3 RD4/PSP4 RD5/PSP5 RD6/PSP6 RD7/PSP7 RE0/RD RE1/WR RE2/CS 11 32 14 15 16 17 18 23 24 25 26 19 20 21 22 27 28 29 30 8 9 10 VDD VDD OSC2 JP2 CSN CE SCK MISO MOSI TX RX 1 2 3 4 5 6 7 8 Header 8 Vref (micro) IRQ MISO MOSI SCK CSN CE VCC OSC2 R36 47 D5 3.3 V Zener VCC Cap 0.1uF TX 1 3 4 5 11 10 RX 12 9 Vref (micro) Vref (micro) 15 GND MAX232 V6 C1+ C1C2+ C2VCC V+ 16 2 VDD C24 VDD 0.1uF 14 7 13 8 C26 Vref (micro) 0.1uF C

Vref (micro) 5 9 4 8 3 7 2 6 1 J3 D Connector 9 10 11

Vref (micro) Vref (micro)

Vref (micro) Vref (micro)

VR1 5 Volt Reg +6V D6 C21 22uF Vin Vout GND VDD R35 470 C22 0.1uF

Vref (micro)

Vref (micro)

1 D4

2 Vref (micro)

Vref (micro) Title Size A2 Date: File: 30/07/2006 Sheet of C:\Documents and Settings\..\ecg.SCHDOCDrawn By: 8 Number Revision

Designator C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 D1 D2 D3 D4 D5 D6 J3 JP1 JP2 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 100u 100u 100u 1u 1u 1u 1u 1u 1u 10n 10n 10n 100n 100n 100n 100n 100n 100n 22p 22p 0.1u 22u 0.1u 0.1u 0.1u 0.1u 0.1u

Description RAD-0.1 RAD-0.1 RAD-0.1 RAD-0.1 RAD-0.1 RAD-0.1 RAD-0.1 RAD-0.1 RAD-0.1 RAD-0.1 RAD-0.1 RAD-0.1 RAD-0.1 RAD-0.1 RAD-0.1 RAD-0.1 RAD-0.1 RAD-0.1 RAD-0.1 RAD-0.1 RAD-0.1 RAD-0.1 RAD-0.1 RAD-0.1 RAD-0.1 RAD-0.1 RAD-0.1 AXIAL-0.3 AXIAL-0.3 AXIAL-0.3 AXIAL-0.3 AXIAL-0.3 AXIAL-0.3

Footprint Cap Pol3 Cap Pol3 Cap Pol3 Cap Pol3 Cap Pol3 Cap Pol3 Cap Pol3 Cap Pol3 Cap Pol3 Cap Cap Cap Cap Cap Cap Cap Cap Cap Cap Cap Cap Pol1 Cap Cap Cap Cap Cap Cap

Comment

5.1V Zener 3.3 V Zener D Zener LED1 3.3 V Zener Diode D Connector 9 Header 6H Header 8 1K 1K 1K 1K 1K 2K2 2K2 2K2 1K 1K 1K 1K 1K 1K

5.1V Zener 3.3 V Zener D Zener LED1 3.3 V Zener Diode D Connector 9 Header 6H Header 8 Res1 Res1 Res1 Res1 Res1 Res1 Res1 Res1 RPot1 RPot1 RPot1 Res1 Res1 Res1

DSUB1.385-2H9 HDR1X6 HDR1X8 AXIAL-0.3 AXIAL-0.3 AXIAL-0.3 AXIAL-0.3 AXIAL-0.3 AXIAL-0.3 AXIAL-0.3 AXIAL-0.3 VR4 VR4 VR4 AXIAL-0.3 AXIAL-0.3 AXIAL-0.3

R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 R30 R31 R32 R33 R34 R35 R36 SW1 U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 VR1 XTAL1

10K 10K 10K 200K 200K 200K 3K9 3K9 3K9 82K 82K 82K 82K 82K 82K 45K 45K 45K 4K7 4K7 470R 47R Push Button Switch AD620AN AD620AN AD620AN LM741 LM741 LM741 LM741 LM741 LM741 PIC16C65-20I/P MAX232 5 Volt Reg XTAL

AXIAL-0.3 AXIAL-0.3 AXIAL-0.3 VR4 VR4 VR4 AXIAL-0.3 AXIAL-0.3 AXIAL-0.3 AXIAL-0.3 AXIAL-0.3 AXIAL-0.3 AXIAL-0.3 AXIAL-0.3 AXIAL-0.3 AXIAL-0.3 AXIAL-0.3 AXIAL-0.3 AXIAL-0.3 AXIAL-0.3 AXIAL-0.3 AXIAL-0.3 SPST-2 DIP-8 DIP-8 DIP-8 DIP-8 DIP-8 DIP-8 DIP-8 DIP-8 DIP-8 DIP-P40/X.85 DIP-16/X1.5 SPDT-3 RAD-0.1

Res1 Res1 Res1 RPot1 RPot1 RPot1 Res1 Res1 Res1 Res1 Res1 Res1 Res1 Res1 Res1 Res1 Res1 Res1 Res1 Res1 Res1 Res1 SW-PB AD620AN AD620AN AD620AN LM741 LM741 LM741 LM741 LM741 LM741 PIC16C65-20I/P MAX232 5 Volt Reg XTAL

Appendix B Datasheets

a
FEATURES EASY TO USE Gain Set with One External Resistor (Gain Range 1 to 1000) Wide Power Supply Range (2.3 V to 18 V) Higher Performance than Three Op Amp IA Designs Available in 8-Lead DIP and SOIC Packaging Low Power, 1.3 mA max Supply Current EXCELLENT DC PERFORMANCE (B GRADE) 50 V max, Input Offset Voltage 0.6 V/ C max, Input Offset Drift 1.0 nA max, Input Bias Current 100 dB min Common-Mode Rejection Ratio (G = 10) LOW NOISE 9 nV/ Hz, @ 1 kHz, Input Voltage Noise 0.28 V p-p Noise (0.1 Hz to 10 Hz) EXCELLENT AC SPECIFICATIONS 120 kHz Bandwidth (G = 100) 15 s Settling Time to 0.01% APPLICATIONS Weigh Scales ECG and Medical Instrumentation Transducer Interface Data Acquisition Systems Industrial Process Controls Battery Powered and Portable Equipment PRODUCT DESCRIPTION

Low Cost, Low Power Instrumentation Amplifier AD620

CONNECTION DIAGRAM 8-Lead Plastic Mini-DIP (N), Cerdip (Q) and SOIC (R) Packages
RG IN +IN VS 1 2 3 4 8 RG

7 +VS 6 OUTPUT

AD620
TOP VIEW

5 REF

1000. Furthermore, the AD620 features 8-lead SOIC and DIP packaging that is smaller than discrete designs, and offers lower power (only 1.3 mA max supply current), making it a good fit for battery powered, portable (or remote) applications. The AD620, with its high accuracy of 40 ppm maximum nonlinearity, low offset voltage of 50 V max and offset drift of 0.6 V/C max, is ideal for use in precision data acquisition systems, such as weigh scales and transducer interfaces. Furthermore, the low noise, low input bias current, and low power of the AD620 make it well suited for medical applications such as ECG and noninvasive blood pressure monitors. The low input bias current of 1.0 nA max is made possible with the use of Supereta processing in the input stage. The AD620 works well as a preamplifier due to its low input voltage noise of 9 nV/Hz at 1 kHz, 0.28 V p-p in the 0.1 Hz to 10 Hz band, 0.1 pA/Hz input current noise. Also, the AD620 is well suited for multiplexed applications with its settling time of 15 s to 0.01% and its cost is low enough to enable designs with one inamp per channel.
10,000

The AD620 is a low cost, high accuracy instrumentation amplifier that requires only one external resistor to set gains of 1 to
30,000

TOTAL ERROR, PPM OF FULL SCALE

25,000

3 OP-AMP IN-AMP (3 OP-07s)

1,000

20,000

RTI VOLTAGE NOISE (0.1 10Hz) V p-p

TYPICAL STANDARD BIPOLAR INPUT IN-AMP 100 G = 100 10 AD620 SUPERETA BIPOLAR INPUT IN-AMP

15,000

AD620A
10,000 RG

5,000

0 0 5 10 SUPPLY CURRENT mA 15 20

0.1 1k

10k

100k 1M SOURCE RESISTANCE

10M

100M

Figure 1. Three Op Amp IA Designs vs. AD620

Figure 2. Total Voltage Noise vs. Source Resistance

REV. E
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 Analog Devices, Inc., 1999

AD620SPECIFICATIONS
Model GAIN Gain Range Gain Error2 G=1 G = 10 G = 100 G = 1000 Nonlinearity, G = 11000 G = 1100 Gain vs. Temperature Conditions G = 1 + (49.4 k/R G) VOUT = 10 V

(Typical @ +25C, VS = 15 V, and RL = 2 k, unless otherwise noted)

Min 1 0.03 0.15 0.15 0.40 AD620A Typ Max 10,000 0.10 0.30 0.30 0.70 40 95 10 50 30 0.3 400 125 185 1.0 1000 1500 2000 15 15 0.1 200 Min 1 0.01 0.10 0.10 0.35 10 10 AD620B Typ Max 10,000 0.02 0.15 0.15 0.50 40 95 10 50 50 85 0.6 500 750 1000 7.0 30 0.3 400 Min 1 0.03 0.15 0.15 0.40 10 10 AD620S1 Typ Max 10,000 0.10 0.30 0.30 0.70 40 95 10 50 125 225 1.0 1000 1500 2000 15 % % % % ppm ppm ppm/C ppm/C V V V/C V V V V/C Units

VOUT = 10 V to +10 V, RL = 10 k RL = 2 k G =1 Gain >1 2

10 10

VOLTAGE OFFSET Input Offset, VOSI Over Temperature Average TC Output Offset, V OSO Over Temperature Average TC Offset Referred to the Input vs. Supply (PSR) G=1 G = 10 G = 100 G = 1000 INPUT CURRENT Input Bias Current Over Temperature Average TC Input Offset Current Over Temperature Average TC INPUT Input Impedance Differential Common-Mode Input Voltage Range 3 Over Temperature Over Temperature Common-Mode Rejection Ratio DC to 60 Hz with I k Source Imbalance G=1 G = 10 G = 100 G = 1000 OUTPUT Output Swing Over Temperature Over Temperature Short Current Circuit

(Total RTI Error = V OSI + VOSO/G) VS = 5 V to 15 V VS = 5 V to 15 V VS = 5 V to 15 V VS = 15 V VS = 5 V VS = 5 V to 15 V VS = 5 V to 15 V VS = 2.3 V to 18 V 80 95 110 110

5.0

2.5

5.0

100 120 140 140 0.5 3.0 0.3 1.5 2.0 2.5 1.0 1.5

80 100 120 120

100 120 140 140 0.5 3.0 0.3 1.5 1.0 1.5 0.5 0.75

80 95 110 110

100 120 140 140 0.5 8.0 0.3 8.0 2 4 1.0 2.0

dB dB dB dB nA nA pA/C nA nA pA/C

VS = 2.3 V to 5 V VS = 5 V to 18 V

102 102 VS + 1.9 VS + 2.1 VS + 1.9 VS + 2.1 +VS 1.2 +VS 1.3 +VS 1.4 +VS 1.4 VS + 1.9 VS + 2.1 VS + 1.9 VS + 2.1

102 102 +VS 1.2 +VS 1.3 +VS 1.4 +VS 1.4 VS + 1.9 VS + 2.1 VS + 1.9 VS + 2.3

102 102 +VS 1.2 +VS 1.3 +VS 1.4 +VS 1.4

GpF GpF V V V V

VCM = 0 V to 10 V 73 93 110 110 RL = 10 k, VS = 2.3 V to 5 V VS = 5 V to 18 V 90 110 130 130 80 100 120 120 90 110 130 130 73 93 110 110 90 110 130 130 dB dB dB dB

VS + 1.1 VS + 1.4 VS + 1.2 VS + 1.6

18

+VS 1.2 +VS 1.3 +VS 1.4 +VS 1.5

VS + 1.1 VS + 1.4 VS + 1.2 VS + 1.6

18

+VS 1.2 +VS 1.3 +VS 1.4 +VS 1.5

VS + 1.1 VS + 1.6 VS + 1.2 VS + 2.3

18

+VS 1.2 +VS 1.3 +VS 1.4 +VS 1.5

V V V V mA

REV. E

AD620
Model Conditions Min AD620A Typ Max Min AD620B Typ Max Min AD620S1 Typ Max Units DYNAMIC RESPONSE Small Signal 3 dB Bandwidth G=1 G = 10 G = 100 G = 1000 Slew Rate Settling Time to 0.01% 10 V Step G = 1100 G = 1000 NOISE Voltage Noise, 1 kHz Input, Voltage Noise, e ni Output, Voltage Noise, e no RTI, 0.1 Hz to 10 Hz G=1 G = 10 G = 1001000 Current Noise 0.1 Hz to 10 Hz REFERENCE INPUT RIN IIN Voltage Range Gain to Output POWER SUPPLY Operating Range 4 Quiescent Current Over Temperature TEMPERATURE RANGE For Specified Performance
NOTES 1 See Analog Devices military data sheet for 883B tested specifications. 2 Does not include effects of external resistor R G. 3 One input grounded. G = 1. 4 This is defined as the same supply range which is used to specify PSR. Specifications subject to change without notice.

0.75

1000 800 120 12 1.2 15 150

0.75

1000 800 120 12 1.2 15 150

0.75

1000 800 120 12 1.2 15 150

kHz kHz kHz kHz V/s s s

Total RTI Noise = ( e2 ni ) + ( eno / G )2 9 72 3.0 0.55 0.28 100 10 20 +50 13 100 9 72 13 100 9 72 13 100 nV/Hz nV/Hz V p-p V p-p V p-p fA/Hz pA p-p k A V

f = 1 kHz

3.0 6.0 0.55 0.8 0.28 0.4 100 10 20 +50

3.0 6.0 0.55 0.8 0.28 0.4 100 10 20 +50

VIN+ , VREF = 0

+60 VS + 1.6 +VS 1.6 1 0.0001 2.3 0.9 1.1 40 to +85 18 1.3 1.6

+60 VS + 1.6 +VS 1.6 1 0.0001 2.3 0.9 1.1 40 to +85 18 1.3 1.6

+60 VS + 1.6 +VS 1.6 1 0.0001 2.3 0.9 1.1 18 1.3 1.6

VS = 2.3 V to 18 V

V mA mA C

55 to +125

REV. E

AD620
ABSOLUTE MAXIMUM RATINGS 1

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V Internal Power Dissipation2 . . . . . . . . . . . . . . . . . . . . . 650 mW Input Voltage (Common Mode) . . . . . . . . . . . . . . . . . . . . VS Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . 25 V Output Short Circuit Duration . . . . . . . . . . . . . . . . . Indefinite Storage Temperature Range (Q) . . . . . . . . . . 65C to +150C Storage Temperature Range (N, R) . . . . . . . . 65C to +125C Operating Temperature Range AD620 (A, B) . . . . . . . . . . . . . . . . . . . . . . 40C to +85C AD620 (S) . . . . . . . . . . . . . . . . . . . . . . . . 55C to +125C Lead Temperature Range (Soldering 10 seconds) . . . . . . . . . . . . . . . . . . . . . . . +300C
NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Specification is for device in free air: 8-Lead Plastic Package: JA = 95C/W 8-Lead Cerdip Package: JA = 110C/W 8-Lead SOIC Package: JA = 155C/W

ORDERING GUIDE

Model AD620AN AD620BN AD620AR AD620AR-REEL AD620AR-REEL7 AD620BR AD620BR-REEL AD620BR-REEL7 AD620ACHIPS AD620SQ/883B

Temperature Ranges Package Options* 40C to +85C 40C to +85C 40C to +85C 40C to +85C 40C to +85C 40C to +85C 40C to +85C 40C to +85C 40C to +85C 55C to +125C N-8 N-8 SO-8 13" REEL 7" REEL SO-8 13" REEL 7" REEL Die Form Q-8

*N = Plastic DIP; Q = Cerdip; SO = Small Outline.

METALIZATION PHOTOGRAPH
Dimensions shown in inches and (mm). Contact factory for latest dimensions.
RG* +VS OUTPUT

6 5 REFERENCE

0.0708 (1.799)

1 1 2 0.125 (3.180) 3 4

RG*

VS +IN

IN

*FOR CHIP APPLICATIONS: THE PADS 1RG AND 8RG MUST BE CONNECTED IN PARALLEL TO THE EXTERNAL GAIN REGISTER RG. DO NOT CONNECT THEM IN SERIES TO RG. FOR UNITY GAIN APPLICATIONS WHERE RG IS NOT REQUIRED, THE PADS 1RG MAY SIMPLY BE BONDED TOGETHER, AS WELL AS THE PADS 8RG.

CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD620 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!
ESD SENSITIVE DEVICE

REV. E

AD620 Typical Characteristics (@ +25C, V = 15 V, R = 2 k, unless otherwise noted)

S L
50 SAMPLE SIZE = 360 1.5 40 INPUT BIAS CURRENT nA
PERCENTAGE OF UNITS

2.0

1.0 0.5 0 0.5 1.0 1.5 I B

+IB

30

20

10

0 80 40 0 +40 +80 INPUT OFFSET VOLTAGE V

2.0 75 25 25 75 TEMPERATURE C 125 175

Figure 3. Typical Distribution of Input Offset Voltage

Figure 6. Input Bias Current vs. Temperature

50 SAMPLE SIZE = 850 40

PERCENTAGE OF UNITS

CHANGE IN OFFSET VOLTAGE V

1.5

30

20

10

0.5

0 1200 600 0 +600 +1200 INPUT BIAS CURRENT pA

2 3 WARM-UP TIME Minutes

Figure 4. Typical Distribution of Input Bias Current

Figure 7. Change in Input Offset Voltage vs. Warm-Up Time

50 SAMPLE SIZE = 850 40

PERCENTAGE OF UNITS

1000

GAIN = 1

VOLTAGE NOISE nV/Hz

100 GAIN = 10

30

20

10

10

GAIN = 100, 1,000 GAIN = 1000 BW LIMIT

400

200

+200

+400

1 1 10 100 1k FREQUENCY Hz 10k 100k

INPUT OFFSET CURRENT pA

Figure 5. Typical Distribution of Input Offset Current

Figure 8. Voltage Noise Spectral Density vs. Frequency, (G = 11000)

REV. E

AD620Typical Characteristics
1000

CURRENT NOISE fA/Hz

100

10

10

100 FREQUENCY Hz

1000

Figure 9. Current Noise Spectral Density vs. Frequency

Figure 11. 0.1 Hz to 10 Hz Current Noise, 5 pA/Div

100,000
TOTAL DRIFT FROM 25C TO 85C, RTI V

RTI NOISE 2.0 V/DIV

10,000

FET INPUT IN-AMP 1000

AD620A 100

TIME 1 SEC/DIV

10

1k

10k

100k 1M SOURCE RESISTANCE

10M

Figure 10a. 0.1 Hz to 10 Hz RTI Voltage Noise (G = 1)

Figure 12. Total Drift vs. Source Resistance

+160 +140 +120 G = 1000 G = 100 G = 10 +100

RTI NOISE 0.1V/DIV

CMR dB

G=1 +80 +60 +40 +20 0 0.1

TIME 1 SEC/DIV

10

100 1k FREQUENCY Hz

10k

100k

1M

Figure 10b. 0.1 Hz to 10 Hz RTI Voltage Noise (G = 1000)

Figure 13. CMR vs. Frequency, RTI, Zero to 1 k Source Imbalance

REV. E

AD620
180 160 140 G = 1000 120
PSR dB
35 G = 10, 100, 1000 30

OUTPUT VOLTAGE Volts p-p

25 G=1 20 15

100 80

G = 100

G = 10 60 40 20 0.1 G=1

10 5 G = 1000 0

BW LIMIT

G = 100 10k 100k FREQUENCY Hz 1M

10

100 1k FREQUENCY Hz

10k

100k

1M

1k

Figure 14. Positive PSR vs. Frequency, RTI (G = 11000)

Figure 17. Large Signal Frequency Response

180
INPUT VOLTAGE LIMIT Volts (REFERRED TO SUPPLY VOLTAGES)

+VS 0.0 0.5 1.0 1.5

160 140 120

PSR dB

100 G = 1000 80 G = 100 60 G = 10 40 G=1 20 0.1

+1.5 +1.0 +0.5 VS +0.0

10

100 1k FREQUENCY Hz

10k

100k

1M

10 15 SUPPLY VOLTAGE Volts

20

Figure 15. Negative PSR vs. Frequency, RTI (G = 11000)

Figure 18. Input Voltage Range vs. Supply Voltage, G = 1

1000

+VS 0.0

OUTPUT VOLTAGE SWING Volts (REFERRED TO SUPPLY VOLTAGES)

0.5 1.0 1.5 RL = 2k RL = 10k

100

GAIN V/V

10

+1.5 RL = 2k +1.0 +0.5 RL = 10k

0.1 100

1k

10k 100k FREQUENCY Hz

1M

10M

VS +0.0 0

10 15 SUPPLY VOLTAGE Volts

20

Figure 16. Gain vs. Frequency

Figure 19. Output Voltage Swing vs. Supply Voltage, G = 10

REV. E

AD620
30

OUTPUT VOLTAGE SWING Volts p-p

VS = 15V G = 10 20

.... .... .... ........ ........ .... ........

10

.... .... .... ........ ........ .... ........

0 0 100 1k LOAD RESISTANCE 10k

Figure 20. Output Voltage Swing vs. Load Resistance

Figure 23. Large Signal Response and Settling Time, G = 10 (0.5 mV = 001%)

.... .... .... ........ ........ .... ........

.... .... ........ .... ........ .... ........

.... .... .... ........ ........ .... ........

.... .... ........ .... ........ .... ........

Figure 21. Large Signal Pulse Response and Settling Time G = 1 (0.5 mV = 0.01%)

Figure 24. Small Signal Response, G = 10, RL = 2 k, CL = 100 pF

.... .... .... ........ ........ .... ........

.... .... .... ........ ........ .... ........

.... .... .... ........ ........ .... ........

.... .... .... ........ ........ .... ........

Figure 22. Small Signal Response, G = 1, RL = 2 k, CL = 100 pF

Figure 25. Large Signal Response and Settling Time, G = 100 (0.5 mV = 0.01%)

REV. E

AD620
20

.... .... .... ........ ........ .... ........

15 SETTLING TIME s TO 0.01% TO 0.1%

10

.... .... .... ........ ........ .... ........

10 15 OUTPUT STEP SIZE Volts

20

Figure 26. Small Signal Pulse Response, G = 100, RL = 2 k, CL = 100 pF

Figure 29. Settling Time vs. Step Size (G = 1)

1000

.... .... ........ ........ .... .... ........

SETTLING TIME s
100

10

.... .... ........ ........ .... .... ........

1 1

10 GAIN

100

1000

Figure 27. Large Signal Response and Settling Time, G = 1000 (0.5 mV = 0.01%)

Figure 30. Settling Time to 0.01% vs. Gain, for a 10 V Step

.... .... .... ........ ........ .... ........

.... .... ........ ........ .... .... ........

.... .... .... ........ ........ .... ........

.... .... ........ ........ .... .... ........

Figure 28. Small Signal Pulse Response, G = 1000, RL = 2 k, CL = 100 pF

Figure 31a. Gain Nonlinearity, G = 1, RL = 10 k (10 V = 1 ppm)

REV. E

AD620
I1 20A VB 20A I2

.... .... .... ........ .... .... .... ........

A1 C1 A2 C2 10k A3 R3 400 R1 Q1 RG GAIN SENSE GAIN SENSE R2 Q2 R4 400 10k 10k +IN OUTPUT REF 10k

IN

.... .... .... ........ .... .... .... ........

VS

Figure 31b. Gain Nonlinearity, G = 100, RL = 10 k (100 V = 10 ppm)

Figure 33. Simplified Schematic of AD620

THEORY OF OPERATION

.... .... ........ ........ .... .... ........

The AD620 is a monolithic instrumentation amplifier based on a modification of the classic three op amp approach. Absolute value trimming allows the user to program gain accurately (to 0.15% at G = 100) with only one resistor. Monolithic construction and laser wafer trimming allow the tight matching and tracking of circuit components, thus ensuring the high level of performance inherent in this circuit. The input transistors Q1 and Q2 provide a single differentialpair bipolar input for high precision (Figure 33), yet offer 10 lower Input Bias Current thanks to Supereta processing. Feedback through the Q1-A1-R1 loop and the Q2-A2-R2 loop maintains constant collector current of the input devices Q1, Q2 thereby impressing the input voltage across the external gain setting resistor RG. This creates a differential gain from the inputs to the A1/A2 outputs given by G = (R1 + R2)/RG + 1. The unity-gain subtracter A3 removes any common-mode signal, yielding a single-ended output referred to the REF pin potential. The value of RG also determines the transconductance of the preamp stage. As RG is reduced for larger gains, the transconductance increases asymptotically to that of the input transistors. This has three important advantages: (a) Open-loop gain is boosted for increasing programmed gain, thus reducing gainrelated errors. (b) The gain-bandwidth product (determined by C1, C2 and the preamp transconductance) increases with programmed gain, thus optimizing frequency response. (c) The input voltage noise is reduced to a value of 9 nV/Hz, determined mainly by the collector current and base resistance of the input devices. The internal gain resistors, R1 and R2, are trimmed to an absolute value of 24.7 k, allowing the gain to be programmed accurately with a single external resistor. The gain equation is then

.... .... ........ ........ .... .... ........

Figure 31c. Gain Nonlinearity, G = 1000, RL = 10 k (1 mV = 100 ppm)

10k* INPUT 10V p-p 100k 1k 10T 10k

VOUT

+VS 11k 1k 100 G=1 G=100 G=10 49.9 499 5.49k 8 4 3 VS *ALL RESISTORS 1% TOLERANCE 2 1 G=1000 7

AD620
5

G=

49.4 k +1 RG
so that

Figure 32. Settling Time Test Circuit

RG =

49.4 k G 1

10

REV. E

AD620
Make vs. Buy: A Typical Bridge Application Error Budget

The AD620 offers improved performance over homebrew three op amp IA designs, along with smaller size, fewer components and 10 lower supply current. In the typical application, shown in Figure 34, a gain of 100 is required to amplify a bridge output of 20 mV full scale over the industrial temperature range of 40C to +85C. The error budget table below shows how to calculate the effect various error sources have on circuit accuracy. Regardless of the system in which it is being used, the AD620 provides greater accuracy, and at low power and price. In simple

systems, absolute accuracy and drift errors are by far the most significant contributors to error. In more complex systems with an intelligent processor, an autogain/autozero cycle will remove all absolute accuracy and drift errors leaving only the resolution errors of gain nonlinearity and noise, thus allowing full 14-bit accuracy. Note that for the homebrew circuit, the OP07 specifications for input voltage offset and noise have been multiplied by 2. This is because a three op amp type in-amp has two op amps at its inputs, both contributing to the overall input error.

+10V

OP07D
R = 350 R = 350 RG 499 R = 350 R = 350 REFERENCE 10k**

10k*

10k*

AD620A

100**

10k**

OP07D

OP07D

10k*

10k*

PRECISION BRIDGE TRANSDUCER

AD620A MONOLITHIC INSTRUMENTATION AMPLIFIER, G = 100 SUPPLY CURRENT = 1.3mA MAX

HOMEBREW IN-AMP, G = 100 *0.02% RESISTOR MATCH, 3PPM/C TRACKING **DISCRETE 1% RESISTOR, 100PPM/C TRACKING SUPPLY CURRENT = 15mA MAX

Figure 34. Make vs. Buy

Table I. Make vs. Buy Error Budget

AD620 Circuit Calculation 125 V/20 mV 1000 V/100/20 mV 2 nA 350 /20 mV 110 dB3.16 ppm, 5 V/20 mV Homebrew Circuit Calculation (150 V 2)/20 mV ((150 V 2)/100)/20 mV (6 nA 350 )/20 mV (0.02% Match 5 V)/20 mV/100 Total Absolute Error DRIFT TO +85C Gain Drift, ppm/C Input Offset Voltage Drift, V/C Output Offset Voltage Drift, V/C (50 ppm + 10 ppm) 60C 1 V/C 60C/20 mV 15 V/C 60C/100/20 mV 100 ppm/C Track 60C (2.5 V/C 2 60C)/20 mV (2.5 V/C 2 60C)/100/20 mV Total Drift Error RESOLUTION Gain Nonlinearity, ppm of Full Scale 40 ppm Typ 0.1 Hz10 Hz Voltage Noise, V p-p 0.28 V p-p/20 mV 40 ppm (0.38 V p-p 2)/20 mV Total Resolution Error Grand Total Error
G = 100, VS = 15 V. (All errors are min/max and referred to input.)

Error Source ABSOLUTE ACCURACY at TA = +25C Input Offset Voltage, V Output Offset Voltage, V Input Offset Current, nA CMR, dB

Error, ppm of Full Scale AD620 Homebrew 16,250 14,500 14,118 14,791 17,558 13,600 13,000 14,450 17,050 14,140 141,14 14,154 14,662 10,607 10,150 14,153 10,500 11,310 16,000 10,607 10,150 16,757 10,140 13,127 101,67 28,134

REV. E

11

AD620
+5V 20k REF

3k 3k

3k 3k G=100 499

3 8

AD620B
1 2 4 5

6 10k

IN

ADC AD705
0.6mA MAX AGND

DIGITAL DATA OUTPUT

20k 1.7mA 1.3mA MAX 0.10mA

Figure 35. A Pressure Monitor Circuit which Operates on a +5 V Single Supply

Pressure Measurement Medical ECG

Although useful in many bridge applications such as weigh scales, the AD620 is especially suitable for higher resistance pressure sensors powered at lower voltages where small size and low power become more significant. Figure 35 shows a 3 k pressure transducer bridge powered from +5 V. In such a circuit, the bridge consumes only 1.7 mA. Adding the AD620 and a buffered voltage divider allows the signal to be conditioned for only 3.8 mA of total supply current. Small size and low cost make the AD620 especially attractive for voltage output pressure transducers. Since it delivers low noise and drift, it will also serve applications such as diagnostic noninvasive blood pressure measurement.

The low current noise of the AD620 allows its use in ECG monitors (Figure 36) where high source resistances of 1 M or higher are not uncommon. The AD620s low power, low supply voltage requirements, and space-saving 8-lead mini-DIP and SOIC package offerings make it an excellent choice for battery powered data recorders. Furthermore, the low bias currents and low current noise coupled with the low voltage noise of the AD620 improve the dynamic range for better performance. The value of capacitor C1 is chosen to maintain stability of the right leg drive loop. Proper safeguards, such as isolation, must be added to this circuit to protect the patient from possible harm.
+3V

PATIENT/CIRCUIT PROTECTION/ISOLATION

C1

R1 10k R4 1M

R3 24.9k R2 24.9k

RG 8.25k

AD620A
G=7

0.03Hz HIGH PASS FILTER

G = 143

OUTPUT 1V/mV

OUTPUT AMPLIFIER

AD705J
3V

Figure 36. A Medical ECG Monitor Circuit

12

REV. E

AD620
Precision V-I Converter INPUT AND OUTPUT OFFSET VOLTAGE

The AD620, along with another op amp and two resistors, makes a precision current source (Figure 37). The op amp buffers the reference terminal to maintain good CMR. The output voltage VX of the AD620 appears across R1, which converts it to a current. This current less only, the input bias current of the op amp, then flows out to the load.
+VS VIN+ 7 + VX

The low errors of the AD620 are attributed to two sources, input and output errors. The output error is divided by G when referred to the input. In practice, the input errors dominate at high gains and the output errors dominate at low gains. The total VOS for a given gain is calculated as: Total Error RTI = input error + (output error/G) Total Error RTO = (input error G) + output error
REFERENCE TERMINAL

3 8 RG 1

AD620
5 4 VS Vx R1 [(V IN+) (V IN )] G R1 2

6 R1

VIN

The reference terminal potential defines the zero output voltage, and is especially useful when the load does not share a precise ground with the rest of the system. It provides a direct means of injecting a precise offset to the output, with an allowable range of 2 V within the supply voltages. Parasitic resistance should be kept to a minimum for optimum CMR. The AD620 features 400 of series thin film resistance at its inputs, and will safely withstand input overloads of up to 15 V or 60 mA for several hours. This is true for all gains, and power on and off, which is particularly important since the signal source and amplifier may be powered separately. For longer time periods, the current should not exceed 6 mA (IIN VIN/400 ). For input overloads beyond the supplies, clamping the inputs to the supplies (using a low leakage diode such as an FD333) will reduce the required resistance, yielding lower noise.
RF INTERFERENCE INPUT PROTECTION

AD705

I L=

LOAD

Figure 37. Precision Voltage-to-Current Converter (Operates on 1.8 mA, 3 V)

GAIN SELECTION

The AD620s gain is resistor programmed by RG, or more precisely, by whatever impedance appears between Pins 1 and 8. The AD620 is designed to offer accurate gains using 0.1%1% resistors. Table II shows required values of RG for various gains. Note that for G = 1, the RG pins are unconnected (RG = ). For any arbitrary gain RG can be calculated by using the formula:

RG =

49.4 k G 1

To minimize gain error, avoid high parasitic resistance in series with RG; to minimize gain drift, RG should have a low TCless than 10 ppm/Cfor the best performance.
Table II. Required Values of Gain Resistors 1% Std Table Value of RG, 49.9 k 12.4 k 5.49 k 2.61 k 1.00 k 499 249 100 49.9 Calculated Gain 1.990 4.984 9.998 19.93 50.40 100.0 199.4 495.0 991.0 0.1% Std Table Value of RG, 49.3 k 12.4 k 5.49 k 2.61 k 1.01 k 499 249 98.8 49.3 Calculated Gain 2.002 4.984 9.998 19.93 49.91 100.0 199.4 501.0 1,003

All instrumentation amplifiers can rectify out of band signals, and when amplifying small signals, these rectified voltages act as small dc offset errors. The AD620 allows direct access to the input transistor bases and emitters enabling the user to apply some first order filtering to unwanted RF signals (Figure 38), where RC 1/(2 f) and where f the bandwidth of the AD620; C 150 pF. Matching the extraneous capacitance at Pins 1 and 8 and Pins 2 and 3 helps to maintain high CMR.
RG

1 C R IN R +IN 3 2

4 C

Figure 38. Circuit to Attenuate RF Interference

REV. E

13

AD620
COMMON-MODE REJECTION GROUNDING

Instrumentation amplifiers like the AD620 offer high CMR, which is a measure of the change in output voltage when both inputs are changed by equal amounts. These specifications are usually given for a full-range input voltage change and a specified source imbalance. For optimal CMR the reference terminal should be tied to a low impedance point, and differences in capacitance and resistance should be kept to a minimum between the two inputs. In many applications shielded cables are used to minimize noise, and for best CMR over frequency the shield should be properly driven. Figures 39 and 40 show active data guards that are configured to improve ac common-mode rejections by bootstrapping the capacitances of input cable shields, thus minimizing the capacitance mismatch between the inputs.
+VS INPUT

Since the AD620 output voltage is developed with respect to the potential on the reference terminal, it can solve many grounding problems by simply tying the REF pin to the appropriate local ground. In order to isolate low level analog signals from a noisy digital environment, many data-acquisition components have separate analog and digital ground pins (Figure 41). It would be convenient to use a single ground line; however, current through ground wires and PC runs of the circuit card can cause hundreds of millivolts of error. Therefore, separate ground returns should be provided to minimize the current flow from the sensitive points to the system ground. These ground returns must be tied together at some point, usually best at the ADC package as shown.
ANALOG P.S. +15V C 15V DIGITAL P.S. C +5V

100

AD648
0.1F 0.1F
1F 1F 1F

RG 100 VS

AD620

VOUT

+
REFERENCE

AD620

AD585
S/H

AD574A
ADC

DIGITAL DATA OUTPUT

+ INPUT VS

Figure 39. Differential Shield Driver

+VS INPUT RG 2

Figure 41. Basic Grounding Practice

100

AD548

RG 2

AD620

VOUT REFERENCE

+ INPUT VS

Figure 40. Common-Mode Shield Driver

14

REV. E

AD620
GROUND RETURNS FOR INPUT BIAS CURRENTS

Input bias currents are those currents necessary to bias the input transistors of an amplifier. There must be a direct return path for these currents; therefore, when amplifying floating input

sources such as transformers, or ac-coupled sources, there must be a dc path from each input to ground as shown in Figure 42. Refer to the Instrumentation Amplifier Application Guide (free from Analog Devices) for more information regarding in amp applications.
+VS INPUT

+VS INPUT

RG

AD620
LOAD

VOUT

RG

AD620
LOAD

VOUT

+ INPUT VS

REFERENCE

+ INPUT VS

REFERENCE

TO POWER SUPPLY GROUND

TO POWER SUPPLY GROUND

Figure 42a. Ground Returns for Bias Currents with Transformer Coupled Inputs
+VS INPUT

Figure 42b. Ground Returns for Bias Currents with Thermocouple Inputs

RG

AD620
LOAD

VOUT

+ INPUT 100k 100k VS

REFERENCE

TO POWER SUPPLY GROUND

Figure 42c. Ground Returns for Bias Currents with AC Coupled Inputs

REV. E

15

AD620
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).

Plastic DIP (N-8) Package

0.430 (10.92) 0.348 (8.84)
8 5

0.280 (7.11) 0.240 (6.10) 0.060 (1.52) 0.015 (0.38) 0.325 (8.25) 0.300 (7.62) 0.195 (4.95) 0.115 (2.93)

PIN 1 0.210 (5.33) MAX

0.130 (3.30) 0.160 (4.06) MIN 0.115 (2.93) 0.022 (0.558) 0.100 0.070 (1.77) SEATING PLANE 0.014 (0.356) (2.54) 0.045 (1.15) BSC

0.015 (0.381) 0.008 (0.204)

Cerdip (Q-8) Package

0.005 (0.13) MIN
8

0.055 (1.4) MAX

5

0.310 (7.87) 0.220 (5.59)

1 4

PIN 1 0.405 (10.29) 0.060 (1.52) MAX 0.015 (0.38)

0.320 (8.13) 0.290 (7.37)

0.200 (5.08) MAX

0.150 (3.81) 0.200 (5.08) MIN 0.125 (3.18) 0.023 (0.58) 0.100 0.070 (1.78) SEATING PLANE 0.014 (0.36) (2.54) 0.030 (0.76) BSC

15 0

0.015 (0.38) 0.008 (0.20)

SOIC (SO-8) Package

0.1968 (5.00) 0.1890 (4.80)
8 1 5 4

0.1574 (4.00) 0.1497 (3.80)

0.2440 (6.20) 0.2284 (5.80)

PIN 1 0.0098 (0.25) 0.0040 (0.10)

0.0688 (1.75) 0.0532 (1.35)

0.0196 (0.50) x 45 0.0099 (0.25)

16

REV. E

PRINTED IN U.S.A.

0.0500 0.0192 (0.49) SEATING (1.27) 0.0098 (0.25) PLANE BSC 0.0138 (0.35) 0.0075 (0.19)

8 0 0.0500 (1.27) 0.0160 (0.41)

C1599c07/99

LM741 Operational Amplifier

August 2000

LM741 Operational Amplifier

General Description
The LM741 series are general purpose operational amplifiers which feature improved performance over industry standards like the LM709. They are direct, plug-in replacements for the 709C, LM201, MC1439 and 748 in most applications. The amplifiers offer many features which make their application nearly foolproof: overload protection on the input and output, no latch-up when the common mode range is exceeded, as well as freedom from oscillations. The LM741C is identical to the LM741/LM741A except that the LM741C has their performance guaranteed over a 0C to +70C temperature range, instead of 55C to +125C.

Features

Connection Diagrams
Metal Can Package Dual-In-Line or S.O. Package

00934102

00934103

Note 1: LM741H is available per JM38510/10101

Order Number LM741H, LM741H/883 (Note 1), LM741AH/883 or LM741CH See NS Package Number H08C Ceramic Flatpak

Order Number LM741J, LM741J/883, LM741CN See NS Package Number J08A, M08A or N08E

00934106

Order Number LM741W/883 See NS Package Number W10A

Typical Application
Offset Nulling Circuit

00934107

2004 National Semiconductor Corporation

DS009341

www.national.com

LM741

Absolute Maximum Ratings (Note 2)

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. (Note 7) LM741A Supply Voltage Power Dissipation (Note 3) Differential Input Voltage Input Voltage (Note 4) Output Short Circuit Duration Operating Temperature Range Storage Temperature Range Junction Temperature Soldering Information N-Package (10 seconds) J- or H-Package (10 seconds) M-Package Vapor Phase (60 seconds) Infrared (15 seconds) 215C 215C 215C 215C 215C 215C 260C 300C 260C 300C 260C 300C LM741 LM741C

22V
500 mW

22V
500 mW

18V
500 mW

30V 15V
Continuous 55C to +125C 65C to +150C 150C

30V 15V
Continuous 55C to +125C 65C to +150C 150C

30V 15V
Continuous 0C to +70C 65C to +150C 100C

See AN-450 Surface Mounting Methods and Their Effect on Product Reliability for other methods of soldering surface mount devices. ESD Tolerance (Note 8) 400V 400V 400V

Electrical Characteristics (Note 5)

Parameter Input Offset Voltage Conditions Min TA = 25C RS 10 k RS 50 TAMIN TA TAMAX RS 50 RS 10 k Average Input Offset Voltage Drift Input Offset Voltage Adjustment Range Input Offset Current Average Input Offset Current Drift Input Bias Current Input Resistance TA = 25C TAMIN TA TAMAX TA = 25C, VS = 20V TAMIN TA TAMAX, VS = 20V Input Voltage Range TA = 25C TAMIN TA TAMAX 1.0 0.5 6.0 30 80 0.210 0.3 2.0 80 500 1.5 0.3 2.0 80 500 0.8 nA A M M TA = 25C TAMIN TA TAMAX 3.0 30 70 0.5 20 85 200 500 20 200 300 nA nA nA/C TA = 25C, VS = 20V 15 4.0 6.0 7.5 mV mV V/C 0.8 3.0 1.0 5.0 2.0 6.0 mV mV LM741A Typ Max Min LM741 Typ Max Min LM741C Typ Max Units

10

15

15

mV

12 12 13

13

V V

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LM741

Electrical Characteristics (Note 5)

Parameter Large Signal Voltage Gain Conditions TA = 25C, RL 2 k VS = 20V, VO = 15V VS = 15V, VO = 10V TAMIN TA TAMAX, RL 2 k, VS = 20V, VO = 15V VS = 15V, VO = 10V VS = 5V, VO = 2V Output Voltage Swing VS = 20V RL 10 k RL 2 k VS = 15V RL 10 k RL 2 k Output Short Circuit Current Common-Mode Rejection Ratio Supply Voltage Rejection Ratio TA = 25C TAMIN TA TAMAX TAMIN TA TAMAX

(Continued) LM741A Min 50 50 200 20 200 Typ Max Min LM741 Typ Max Min LM741C Typ Max V/mV V/mV Units

32 25 10 15

V/mV V/mV V/mV V V

16 15 12 10
10 10 25 35 40 70 80 95 90 70 90

14 13
25

12 10

14 13
25

V V mA mA dB dB

RS 10 k, VCM = 12V RS 50, VCM = 12V TAMIN TA TAMAX, VS = 20V to VS = 5V RS 50 RS 10 k 86 96

dB 77 96 0.3 5 0.5 1.7 2.8 77 96 0.3 5 0.5 1.7 2.8 dB s % MHz V/s mA mW 50 165 135 60 45 100 75 85 50 85 mW mW mW mW mW

Transient Response Rise Time Overshoot Bandwidth (Note 6) Slew Rate Supply Current Power Consumption

TA = 25C, Unity Gain 0.25 6.0 TA = 25C TA = 25C, Unity Gain TA = 25C TA = 25C VS = 20V VS = 15V 80 150 0.437 0.3 1.5 0.7 0.8 20

LM741A

VS = 20V TA = TAMIN TA = TAMAX

LM741

VS = 15V TA = TAMIN TA = TAMAX

Note 2: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits.

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LM741

Electrical Characteristics (Note 5)

(Continued)

Note 3: For operation at elevated temperatures, these devices must be derated based on thermal resistance, and Tj max. (listed under Absolute Maximum Ratings). Tj = TA + (jA PD).

Thermal Resistance jA (Junction to Ambient) jC (Junction to Case)

Cerdip (J) 100C/W N/A

DIP (N) 100C/W N/A

HO8 (H) 170C/W 25C/W

SO-8 (M) 195C/W N/A

Note 4: For supply voltages less than 15V, the absolute maximum input voltage is equal to the supply voltage. Note 5: Unless otherwise specified, these specifications apply for VS = 15V, 55C TA +125C (LM741/LM741A). For the LM741C/LM741E, these specifications are limited to 0C TA +70C. Note 6: Calculated value from: BW (MHz) = 0.35/Rise Time(s). Note 7: For military specifications see RETS741X for LM741 and RETS741AX for LM741A. Note 8: Human body model, 1.5 k in series with 100 pF.

Schematic Diagram

00934101

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LM741

Physical Dimensions
unless otherwise noted

inches (millimeters)

Metal Can Package (H) Order Number LM741H, LM741H/883, LM741AH/883, LM741AH-MIL or LM741CH NS Package Number H08C

www.national.com

LM741

Physical Dimensions

inches (millimeters) unless otherwise noted (Continued)

Ceramic Dual-In-Line Package (J) Order Number LM741J/883 NS Package Number J08A

Dual-In-Line Package (N) Order Number LM741CN NS Package Number N08E

www.national.com

LM741 Operational Amplifier

Physical Dimensions

inches (millimeters) unless otherwise noted (Continued)

10-Lead Ceramic Flatpak (W) Order Number LM741W/883, LM741WG-MPR or LM741WG/883 NS Package Number W10A

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. For the most current product information visit us at www.national.com. LIFE SUPPORT POLICY NATIONALS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. BANNED SUBSTANCE COMPLIANCE National Semiconductor certifies that the products and packing materials meet the provisions of the Customer Products Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification (CSP-9-111S2) and contain no Banned Substances as defined in CSP-9-111S2.
National Semiconductor Americas Customer Support Center Email: new.feedback@nsc.com Tel: 1-800-272-9959 www.national.com National Semiconductor Europe Customer Support Center Fax: +49 (0) 180-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Franais Tel: +33 (0) 1 41 91 8790 National Semiconductor Asia Pacific Customer Support Center Email: ap.support@nsc.com National Semiconductor Japan Customer Support Center Fax: 81-3-5639-7507 Email: jpn.feedback@nsc.com Tel: 81-3-5639-7560

2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

19-4323; Rev 15; 1/06

+5V-Powered, Multichannel RS-232 Drivers/Receivers

General Description
The MAX220MAX249 family of line drivers/receivers is intended for all EIA/TIA-232E and V.28/V.24 communications interfaces, particularly applications where 12V is not available. These parts are especially useful in battery-powered systems, since their low-power shutdown mode reduces power dissipation to less than 5W. The MAX225, MAX233, MAX235, and MAX245/MAX246/MAX247 use no external components and are recommended for applications where printed circuit board space is critical.

Next-Generation Device Features

For Low-Voltage, Integrated ESD Applications MAX3222E/MAX3232E/MAX3237E/MAX3241E/ MAX3246E: +3.0V to +5.5V, Low-Power, Up to 1Mbps, True RS-232 Transceivers Using Four 0.1F External Capacitors (MAX3246E Available in a UCSP Package) For Low-Cost Applications MAX221E: 15kV ESD-Protected, +5V, 1A, Single RS-232 Transceiver with AutoShutdown

MAX220MAX249

________________________Applications
Portable Computers Low-Power Modems Interface Translation Battery-Powered RS-232 Systems Multidrop RS-232 Networks
PART MAX220CPE MAX220CSE MAX220CWE MAX220C/D MAX220EPE MAX220ESE MAX220EWE MAX220EJE MAX220MJE

Ordering Information
TEMP RANGE 0C to +70C 0C to +70C 0C to +70C 0C to +70C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -55C to +125C PIN-PACKAGE 16 Plastic DIP 16 Narrow SO 16 Wide SO Dice* 16 Plastic DIP 16 Narrow SO 16 Wide SO 16 CERDIP 16 CERDIP

AutoShutdown and UCSP are trademarks of Maxim Integrated Products, Inc.

Ordering Information continued at end of data sheet. *Contact factory for dice specifications.

Selection Table
Part Number MAX220 MAX222 MAX223 (MAX213) MAX225 MAX230 (MAX200) MAX231 (MAX201) MAX232 (MAX202) MAX232A MAX233 (MAX203) MAX233A MAX234 (MAX204) MAX235 (MAX205) MAX236 (MAX206) MAX237 (MAX207) MAX238 (MAX208) MAX239 (MAX209) MAX240 MAX241 (MAX211) MAX242 MAX243 MAX244 MAX245 MAX246 MAX247 MAX248 MAX249 Power Supply (V) +5 +5 +5 +5 +5 +5 and +7.5 to +13.2 +5 +5 +5 +5 +5 +5 +5 +5 +5 +5 and +7.5 to +13.2 +5 +5 +5 +5 +5 +5 +5 +5 +5 +5 No. of RS-232 Drivers/Rx 2/2 2/2 4/5 5/5 5/0 2/2 2/2 2/2 2/2 2/2 4/0 5/5 4/3 5/3 4/4 3/5 5/5 4/5 2/2 2/2 8/10 8/10 8/10 8/9 8/8 6/10 No. of Ext. Caps 4 4 4 0 4 2 4 4 0 0 4 0 4 4 4 2 4 4 4 4 4 0 0 0 4 4 Nominal Cap. Value (F) 0.047/0.33 0.1 1.0 (0.1) 1.0 (0.1) 1.0 (0.1) 1.0 (0.1) 0.1 1.0 (0.1) 1.0 (0.1) 1.0 (0.1) 1.0 (0.1) 1.0 (0.1) 1.0 1.0 (0.1) 0.1 0.1 1.0 1.0 1.0 SHDN & ThreeState No Yes Yes Yes Yes No No No No No No Yes Yes No No No Yes Yes Yes No No Yes Yes Yes Yes Yes Rx Active in SHDN Data Rate (kbps) 120 200 120 120 120 120 120 (64) 200 120 200 120 120 120 120 120 120 120 120 200 200 120 120 120 120 120 120 Features Ultra-low-power, industry-standard pinout Low-power shutdown MAX241 and receivers active in shutdown Available in SO 5 drivers with shutdown Standard +5/+12V or battery supplies; same functions as MAX232 Industry standard Higher slew rate, small caps No external caps No external caps, high slew rate Replaces 1488 No external caps Shutdown, three state Complements IBM PC serial port Replaces 1488 and 1489 Standard +5/+12V or battery supplies; single-package solution for IBM PC serial port DIP or flatpack package Complete IBM PC serial port Separate shutdown and enable Open-line detection simplifies cabling High slew rate High slew rate, int. caps, two shutdown modes High slew rate, int. caps, three shutdown modes High slew rate, int. caps, nine operating modes High slew rate, selective half-chip enables Available in quad flatpack package

________________________________________________________________ Maxim Integrated Products

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxims website at www.maxim-ic.com.

+5V-Powered, Multichannel RS-232 Drivers/Receivers MAX220MAX249

ABSOLUTE MAXIMUM RATINGSMAX220/222/232A/233A/242/243
Supply Voltage (VCC) ...............................................-0.3V to +6V V+ (Note 1) ..................................................(VCC - 0.3V) to +14V V- (Note 1) .............................................................+0.3V to +14V Input Voltages TIN..............................................................-0.3V to (VCC - 0.3V) RIN (Except MAX220) ........................................................30V RIN (MAX220).....................................................................25V TOUT (Except MAX220) (Note 2) .......................................15V TOUT (MAX220)...............................................................13.2V Output Voltages TOUT ...................................................................................15V ROUT .........................................................-0.3V to (VCC + 0.3V) Driver/Receiver Output Short Circuited to GND.........Continuous Continuous Power Dissipation (TA = +70C) 16-Pin Plastic DIP (derate 10.53mW/C above +70C)..842mW 18-Pin Plastic DIP (derate 11.11mW/C above +70C)..889mW 20-Pin Plastic DIP (derate 8.00mW/C above +70C) ..440mW 16-Pin Narrow SO (derate 8.70mW/C above +70C) ...696mW 16-Pin Wide SO (derate 9.52mW/C above +70C)......762mW 18-Pin Wide SO (derate 9.52mW/C above +70C)......762mW 20-Pin Wide SO (derate 10.00mW/C above +70C)....800mW 20-Pin SSOP (derate 8.00mW/C above +70C) ..........640mW 16-Pin CERDIP (derate 10.00mW/C above +70C).....800mW 18-Pin CERDIP (derate 10.53mW/C above +70C).....842mW Operating Temperature Ranges MAX2_ _AC_ _, MAX2_ _C_ _ .............................0C to +70C MAX2_ _AE_ _, MAX2_ _E_ _ ..........................-40C to +85C MAX2_ _AM_ _, MAX2_ _M_ _ .......................-55C to +125C Storage Temperature Range .............................-65C to +160C Lead Temperature (soldering, 10s) (Note 3) ...................+300C

Note 1: For the MAX220, V+ and V- can have a maximum magnitude of 7V, but their absolute difference cannot exceed 13V. Note 2: Input voltage measured with TOUT in high-impedance state, SHDN or VCC = 0V. Note 3: Maximum reflow temperature for the MAX223A is +225C.
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICSMAX220/222/232A/233A/242/243
(VCC = +5V 10%, C1C4 = 0.1F MAX220, C1 = 0.047F, C2C4 = 0.33F, TA = TMIN to TMAX unless otherwise noted.)
PARAMETER RS-232 TRANSMITTERS Output Voltage Swing Input Logic Threshold Low Input Logic Threshold High All devices except MAX220 MAX220: VCC = 5.0V All except MAX220, normal operation Logic Pullup/lnput Current SHDN = 0V, MAX222/MAX242, shutdown, MAX220 VCC = 5.5V, SHDN = 0V, VOUT = 15V, MAX222/MAX242 Output Leakage Current VCC = SHDN = 0V Data Rate Transmitter Output Resistance Output Short-Circuit Current RS-232 RECEIVERS RS-232 Input Voltage Operating Range RS-232 Input Threshold Low RS-232 Input Threshold High VCC = 5V VCC = 5V MAX220 All except MAX243 R2IN MAX243 R2 IN (Note 4) All except MAX243 R2IN MAX243 R2 IN (Note 4) 0.8 -3 1.8 -0.5 2.4 -0.1 1.3 30 25 V V V VCC = V+ = V- = 0V, VOUT = 2V VOUT = 0V VOUT = 0V MAX220 300 7 VOUT = 15V MAX220, VOUT = 12V 200 10M 22 60 2 2.4 5 0.01 0.01 0.01 40 1 10 10 25 116 kbps mA A A All transmitter outputs loaded with 3k to GND 5 8 1.4 1.4 0.8 V V V CONDITIONS MIN TYP MAX UNITS

_______________________________________________________________________________________

+5V-Powered, Multichannel RS-232 Drivers/Receivers MAX220MAX249

ELECTRICAL CHARACTERISTICSMAX220/222/232A/233A/242/243 (continued)
(VCC = +5V 10%, C1C4 = 0.1F MAX220, C1 = 0.047F, C2C4 = 0.33F, TA = TMIN to TMAX unless otherwise noted.)
PARAMETER CONDITIONS All except MAX220/MAX243, VCC = 5V, no hysteresis in SHDN RS-232 Input Hysteresis MAX220 MAX243 RS-232 Input Resistance TTL/CMOS Output Voltage Low TTL/CMOS Output Voltage High TTL/CMOS Output Short-Circuit Current TTL/CMOS Output Leakage Current EN Input Threshold Low EN Input Threshold High Operating Supply Voltage MAX220 No load VCC Supply Current (SHDN = VCC), figures 5, 6, 11, 19 MAX222/MAX232A/MAX233A/ MAX242/MAX243 MAX220 TA = +25C (MAX220) IOUT = 3.2mA IOUT = 1.6mA (MAX220) IOUT = -1.0mA Sourcing VOUT = GND Shrinking VOUT = VCC SHDN = VCC or EN = VCC (SHDN = 0V for MAX222), 0V VOUT VCC MAX242 MAX242 3.5 -2 10 VCC - 0.2 -10 30 0.05 1.4 2.0 4.5 0.5 4 12 15 0.1 2 2 35 1.4 2.0 6 1.4 12 30 V/s 1.5 3 30.0 10 50 50 100 1 0.8 A V V A 1.4 5.5 2 10 A 10 0.8 3 3 MIN 0.2 TYP 0.5 0.3 1 5 5 0.2 7 7 0.4 0.4 K V V mA A V V V MAX 1.0 V UNITS

3k load both MAX222/MAX232A/MAX233A/ inputs MAX242/MAX243 TA = +25C TA = 0C to +70C TA = -40C to +85C TA = -55C to +125C

Shutdown Supply Current

MAX222/ MAX242

SHDN Input Leakage Current SHDN Threshold Low SHDN Threshold High

MAX222/MAX242 MAX222/MAX242 MAX222/MAX242 CL = 50pF to MAX222/MAX232A/MAX233/ 2500pF, RL = 3k MAX242/MAX243 to 7k, VCC = 5V, TA = +25C, MAX220 measured from +3V to -3V or -3V tPHLT MAX222/MAX232A/MAX233/ MAX242/MAX243 MAX220 tPLHT MAX222/MAX232A/MAX233/ MAX242/MAX243 MAX220

Transition Slew Rate

1.3 4 1.5 5

3.5 10 3.5 10 s

Transmitter Propagation Delay TLL to RS-232 (Normal Operation), Figure 1

Note 4: MAX243 R2OUT is guaranteed to be low when R2IN is 0V or is floating. _______________________________________________________________________________________ 3

+5V-Powered, Multichannel RS-232 Drivers/Receivers MAX220MAX249

ELECTRICAL CHARACTERISTICSMAX220/222/232A/233A/242/243 (continued)
(VCC = +5V 10%, C1C4 = 0.1F MAX220, C1 = 0.047F, C2C4 = 0.33F, TA = TMIN to TMAX unless otherwise noted.)
PARAMETER tPHLR Receiver Propagation Delay RS-232 to TLL (Normal Operation), Figure 2 tPLHR CONDITIONS MAX222/MAX232A/MAX233/ MAX242/MAX243 MAX220 MAX222/MAX232A/MAX233/ MAX242/MAX243 MAX220 Receiver Propagation Delay RS-232 to TLL (Shutdown), Figure 2 Receiver-Output Enable Time, Figure 3 Receiver-Output Disable Time, Figure 3 Transmitter-Output Enable Time (SHDN Goes High), Figure 4 Transmitter-Output Disable Time (SHDN Goes Low), Figure 4 tPHLS tPHLS tER tDR tET MAX242 MAX242 MAX242 MAX242 MAX222/MAX242, 0.1F caps (includes charge-pump start-up) MAX222/MAX242, 0.1F caps MAX222/MAX232A/MAX233/ MAX242/MAX243 tPHLT - tPLHT MAX220 Receiver + to - Propagation Delay Difference (Normal Operation) MAX222/MAX232A/MAX233/ MAX242/MAX243 MAX220 2000 100 225 MIN TYP 0.5 0.6 0.6 0.8 0.5 2.5 125 160 250 MAX 1 3 1 3 10 s 10 500 500 ns ns s s UNITS

tDT

600 300

ns

Transmitter + to - Propagation Delay Difference (Normal Operation)

ns

tPHLR - tPLHR

ns

__________________________________________Typical Operating Characteristics

MAX220/MAX222/MAX232A/MAX233A/MAX242/MAX243
OUTPUT VOLTAGE vs. LOAD CURRENT
MAX220-01

AVAILABLE OUTPUT CURRENT vs. DATA RATE

MAX220-02

MAX222/MAX242 ON-TIME EXITING SHUTDOWN

1F CAPS V+ V+, V- VOLTAGE (V) +5V +5V 0V 0V 1F CAPS 0.1F CAPS VV500s/div -10V 0.1F CAPS SHDN V+
MAX220-03

10 8 6 OUTPUT VOLTAGE (V) 4 2 0 -2 -4 -6 -8 -10 0 5 EITHER V+ OR V- LOADED VCC = 5V NO LOAD ON TRANSMITTER OUTPUTS (EXCEPT MAX220, MAX233A) V- LOADED, NO LOAD ON V+ 0.1F

1F

11 10 OUTPUT CURRENT (mA) 9 8 7 6 5 ALL CAPS 0.1F ALL CAPS 1F VCC = +5.25V OUTPUT LOAD CURRENT FLOWS FROM V+ TO V-

+10V

0.1F

1F

VCC = +4.75V

V+ LOADED, NO LOAD ON V10 15 20 25 LOAD CURRENT (mA)

4 0 10 20 30 40 50 60 DATA RATE (kbits/sec)

_______________________________________________________________________________________

+5V-Powered, Multichannel RS-232 Drivers/Receivers MAX220MAX249

ABSOLUTE MAXIMUM RATINGSMAX223/MAX230MAX241
VCC ...........................................................................-0.3V to +6V V+ ................................................................(VCC - 0.3V) to +14V V- ............................................................................+0.3V to -14V Input Voltages TIN ............................................................-0.3V to (VCC + 0.3V) RIN......................................................................................30V Output Voltages TOUT ...................................................(V+ + 0.3V) to (V- - 0.3V) ROUT .........................................................-0.3V to (VCC + 0.3V) Short-Circuit Duration, TOUT ......................................Continuous Continuous Power Dissipation (TA = +70C) 14-Pin Plastic DIP (derate 10.00mW/C above +70C)....800mW 16-Pin Plastic DIP (derate 10.53mW/C above +70C)....842mW 20-Pin Plastic DIP (derate 11.11mW/C above +70C)....889mW 24-Pin Narrow Plastic DIP (derate 13.33mW/C above +70C) ..........1.07W 24-Pin Plastic DIP (derate 9.09mW/C above +70C)......500mW 16-Pin Wide SO (derate 9.52mW/C above +70C).........762mW 20-Pin Wide SO (derate 10 00mW/C above +70C).......800mW 24-Pin Wide SO (derate 11.76mW/C above +70C).......941mW 28-Pin Wide SO (derate 12.50mW/C above +70C) .............1W 44-Pin Plastic FP (derate 11.11mW/C above +70C) .....889mW 14-Pin CERDIP (derate 9.09mW/C above +70C) ..........727mW 16-Pin CERDIP (derate 10.00mW/C above +70C) ........800mW 20-Pin CERDIP (derate 11.11mW/C above +70C) ........889mW 24-Pin Narrow CERDIP (derate 12.50mW/C above +70C) ..............1W 24-Pin Sidebraze (derate 20.0mW/C above +70C)..........1.6W 28-Pin SSOP (derate 9.52mW/C above +70C).............762mW Operating Temperature Ranges MAX2 _ _ C _ _......................................................0C to +70C MAX2 _ _ E _ _ ...................................................-40C to +85C MAX2 _ _ M _ _ ...............................................-55C to +125C Storage Temperature Range .............................-65C to +160C Lead Temperature (soldering, 10s) (Note 4) ...................+300C

Note 4: Maximum reflow temperature for the MAX233/MAX235 is +225C.

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICSMAX223/MAX230MAX241
(MAX223/230/232/234/236/237/238/240/241, VCC = +5V 10; MAX233/MAX235, VCC = 5V 5% C1C4 = 1.0F; MAX231/MAX239, VCC = 5V 10%; V+ = 7.5V to 13.2V; TA = TMIN to TMAX; unless otherwise noted.) PARAMETER Output Voltage Swing VCC Power-Supply Current CONDITIONS All transmitter outputs loaded with 3k to ground MAX232/233 No load, TA = +25C MAX223/230/234238/240/241 MAX231/239 MAX231 MAX239 TA = +25C MAX223 MAX230/235/236/240/241 2.0 2.4 1.5 -30 200 +30 V A V MIN 5.0 TYP 7.3 5 7 0.4 1.8 5 15 1 10 15 1 5 15 50 10 0.8 mA A V mA MAX UNITS V

V+ Power-Supply Current Shutdown Supply Current Input Logic Threshold Low Input Logic Threshold High Logic Pull-Up Current Receiver Input Voltage Operating Range

TIN; EN, SHDN (MAX233); EN, SHDN (MAX230/235241) TIN EN, SHDN (MAX223); EN, SHDN (MAX230/235/236/240/241) TIN = 0V

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+5V-Powered, Multichannel RS-232 Drivers/Receivers MAX220MAX249

ELECTRICAL CHARACTERISTICSMAX223/MAX230MAX241 (continued)
(MAX223/230/232/234/236/237/238/240/241, VCC = +5V 10; MAX233/MAX235, VCC = 5V 5% C1C4 = 1.0F; MAX231/MAX239, VCC = 5V 10%; V+ = 7.5V to 13.2V; TA = TMIN to TMAX; unless otherwise noted.) PARAMETER CONDITIONS Normal operation SHDN = 5V (MAX223) SHDN = 0V (MAX235/236/240/241) Shutdown (MAX223) SHDN = 0V, EN = 5V (R4IN, R5IN) Normal operation SHDN = 5V (MAX223) SHDN = 0V (MAX235/236/240/241) Shutdown (MAX223) SHDN = 0V, EN = 5V (R4IN R5IN) 0.2 3 MIN 0.8 TYP 1.2 V 0.6 1.5 MAX UNITS

RS-232 Input Threshold Low

TA = +25C, VCC = 5V

1.7

2.4 V

RS-232 Input Threshold High

TA = +25C, VCC = 5V

1.5 0.5 5

2.4 1.0 7 0.4 V k V V 10 A ns

RS-232 Input Hysteresis RS-232 Input Resistance TTL/CMOS Output Voltage Low TTL/CMOS Output Voltage High TTL/CMOS Output Leakage Current Receiver Output Enable Time

VCC = 5V, no hysteresis in shutdown TA = +25C, VCC = 5V IOUT = 1.6mA (MAX231/232/233, IOUT = 3.2mA) IOUT = -1mA 0V ROUT VCC; EN = 0V (MAX223); EN = VCC (MAX235241 ) Normal operation Normal operation MAX223 MAX235/236/239/240/241 MAX223 MAX235/236/239/240/241

3.5

VCC - 0.4 0.05 600 400 900 250 0.5 10 40 40 30

Receiver Output Disable Time

ns

Propagation Delay

Normal operation RS-232 IN to TTL/CMOS OUT, SHDN = 0V CL = 150pF (MAX223)

tPHLS tPLHS 3

4 6 5.1

Transition Region Slew Rate

MAX223/MAX230/MAX234241, TA = +25C, VCC = 5V, RL = 3k to 7k CL = 50pF to 2500pF, measured from +3V to -3V or -3V to +3V MAX231/MAX232/MAX233, TA = +25C, VCC = 5V, RL = 3k to 7k, CL = 50pF to 2500pF, measured from +3V to -3V or -3V to +3V VCC = V+ = V- = 0V, VOUT = 2V

V/s 4 300 10 30 mA mA

Transmitter Output Resistance Transmitter Output Short-Circuit Current

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+5V-Powered, Multichannel RS-232 Drivers/Receivers MAX220MAX249

__________________________________________Typical Operating Characteristics MAX223/MAX230MAX241
TRANSMITTER OUTPUT VOLTAGE (VOH) vs. VCC
MAX220-04

TRANSMITTER OUTPUT VOLTAGE (VOH) vs. LOAD CAPACITANCE AT DIFFERENT DATA RATES
MAX220-05

TRANSMITTER SLEW RATE vs. LOAD CAPACITANCE

1 TRANSMITTER LOADED 11.0 10.0 SLEW RATE (V/s) 9.0 8.0 7.0 6.0 5.0 4.0 3 TRANSMITTERS LOADED 4 TRANSMITTERS LOADED 0 500 1000 1500 2000 2500 TA = +25C VCC = +5V LOADED, RL = 3k C1C4 = 1F 2 TRANSMITTERS LOADED
MAX220-06 MAX220-09

8.5 2 TRANSMITTERS LOADED 8.0 VOH (V)

7.4 7.2 7.0 VOH (V)

12.0

1 TRANSMITTER LOADED 7.5

6.8 6.6 6.4 6.2 6.0 0

7.0

6.5 4.5

3 TRANSMITTERS LOADED TA = +25C C1C4 = 1F TRANSMITTER 4 TRANSMITTERS LOADS = 3k || 2500pF LOADED 5.0 VCC (V) 5.5

160kbits/sec 80kbits/sec 20kbits/sec TA = +25C VCC = +5V 3 TRANSMITTERS LOADED RL = 3k C1C4 = 1F 500 1000 1500 2000 2500 LOAD CAPACITANCE (pF)

LOAD CAPACITANCE (pF)

TRANSMITTER OUTPUT VOLTAGE (VOL) vs. VCC

4 TRANSMITTERS LOADED TA = +25C C1C4 = 1F TRANSMITTER LOADS = 3k || 2500pF
MAX220-07

TRANSMITTER OUTPUT VOLTAGE (VOL) vs. LOAD CAPACITANCE AT DIFFERENT DATA RATES
-6.2 -6.4 -6.6 VOL (V) -6.8 -7.0 -7.2 TA = +25C VCC = +5V 3 TRANSMITTERS LOADED RL = 3k C1C4 = 1F 160kbits/sec 80kbits/sec 20Kkbits/sec
MAX220-08

TRANSMITTER OUTPUT VOLTAGE (V+, V-) vs. LOAD CURRENT

10 8 6 4 V+, V- (V) 2 0 -2 -4 TA = +25C VCC = +5V C1C4 = 1F V- LOADED, V+ AND VNO LOAD EQUALLY ON V+ LOADED

-6.0 -6.5 -7.0 VOL (V) -7.5 -8.0 -8.5 -9.0 4.5 5.0 VCC (V) 1 TRANSMITTER LOADED 2 TRANSMITTERS LOADED 3 TRANSMITTERS LOADED

-6.0

V+ LOADED, NO LOAD ON V-

-6 -8 -10 0 500 1000 1500 2000 2500 0 5 LOAD CAPACITANCE (pF) ALL TRANSMITTERS UNLOADED 10 15 20 25 30 35 40 45 50 CURRENT (mA)

-7.4 -7.6 5.5

V+, V- WHEN EXITING SHUTDOWN (1F CAPACITORS)

MAX220-13

V+

O V-

SHDN* 500ms/div *SHUTDOWN POLARITY IS REVERSED FOR NON MAX241 PARTS

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+5V-Powered, Multichannel RS-232 Drivers/Receivers MAX220MAX249

ABSOLUTE MAXIMUM RATINGSMAX225/MAX244MAX249
Supply Voltage (VCC) ...............................................-0.3V to +6V Input Voltages TIN ENA, ENB, ENR, ENT, ENRA, ENRB, ENTA, ENTB..................................-0.3V to (VCC + 0.3V) RIN .....................................................................................25V TOUT (Note 5).....................................................................15V ROUT ........................................................-0.3V to (VCC + 0.3V) Short Circuit (one output at a time) TOUT to GND ............................................................Continuous ROUT to GND............................................................Continuous Continuous Power Dissipation (TA = +70C) 28-Pin Wide SO (derate 12.50mW/C above +70C) .............1W 40-Pin Plastic DIP (derate 11.11mW/C above +70C) ...611mW 44-Pin PLCC (derate 13.33mW/C above +70C) ...........1.07W Operating Temperature Ranges MAX225C_ _, MAX24_C_ _ ..................................0C to +70C MAX225E_ _, MAX24_E_ _ ...............................-40C to +85C Storage Temperature Range .............................-65C to +160C Lead Temperature (soldering,10s) (Note 6) ....................+300C

Note 5: Input voltage measured with transmitter output in a high-impedance state, shutdown, or VCC = 0V. Note 6: Maximum reflow temperature for the MAX225/MAX245/MAX246/MAX247 is +225C.
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICSMAX225/MAX244MAX249
(MAX225, VCC = 5.0V 5%; MAX244MAX249, VCC = +5.0V 10%, external capacitors C1C4 = 1F; TA = TMIN to TMAX; unless otherwise noted.) PARAMETER RS-232 TRANSMITTERS Input Logic Threshold Low Input Logic Threshold High Logic Pull-Up/lnput Current Data Rate Output Voltage Swing Tables 1a1d Normal operation Shutdown 5 2 1.4 1.4 10 0.01 120 7.5 0.01 0.01 300 7 10M 30 25 VCC = 5V VCC = 5V VCC = 5V IOUT = 3.2mA IOUT = -1.0mA Sourcing VOUT = GND Shrinking VOUT = VCC Normal operation, outputs disabled, Tables 1a1d, 0V VOUT VCC, ENR_ = VCC 3.5 -2 10 0.2 3 0.8 1.3 1.8 0.5 5 0.2 VCC - 0.2 -10 30 0.05 0.10 2.4 1.0 7 0.4 25 A 25 mA V V V V k V V mA A 50 1 64 0.8 V V A kbps V CONDITIONS MIN TYP MAX UNITS

Tables 1a1d, normal operation All transmitter outputs loaded with 3k to GND ENA, ENB, ENT, ENTA, ENTB = VCC, VOUT = 15V VCC = 0V, VOUT = 15V

Output Leakage Current (Shutdown)

Tables 1a1d

Transmitter Output Resistance Output Short-Circuit Current RS-232 RECEIVERS RS-232 Input Voltage Operating Range RS-232 Input Threshold Low RS-232 Input Threshold High RS-232 Input Hysteresis RS-232 Input Resistance TTL/CMOS Output Voltage Low TTL/CMOS Output Voltage High TTL/CMOS Output Short-Circuit Current TTL/CMOS Output Leakage Current

VCC = V+ = V- = 0V, VOUT = 2V (Note 7) VOUT = 0V

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+5V-Powered, Multichannel RS-232 Drivers/Receivers

ELECTRICAL CHARACTERISTICSMAX225/MAX244MAX249 (continued)
(MAX225, VCC = 5.0V 5%; MAX244MAX249, VCC = +5.0V 10%, external capacitors C1C4 = 1F; TA = TMIN to TMAX; unless otherwise noted.) PARAMETER POWER SUPPLY AND CONTROL LOGIC Operating Supply Voltage No load VCC Supply Current (Normal Operation) 3k loads on all outputs TA = +25C TA = TMIN to TMAX Leakage current Control Input AC CHARACTERISTICS Transition Slew Rate Transmitter Propagation Delay TLL to RS-232 (Normal Operation), Figure 1 Receiver Propagation Delay TLL to RS-232 (Normal Operation), Figure 2 Receiver Propagation Delay TLL to RS-232 (Low-Power Mode), Figure 2 Transmitter + to - Propagation Delay Difference (Normal Operation) Receiver + to - Propagation Delay Difference (Normal Operation) CL = 50pF to 2500pF, RL = 3k to 7k, VCC = 5V, TA = +25C, measured from +3V to -3V or -3V to +3V tPHLT tPLHT tPHLR tPLHR tPHLS tPLHS tPHLT - tPLHT tPHLR - tPLHR 5 10 1.3 1.5 0.6 0.6 0.6 3.0 350 350 100 100 MAX246MAX249 (excludes charge-pump startup) Transmitter Enable Time tET MAX225/MAX245MAX249 (includes charge-pump startup) 5 10 100 500 500 30 3.5 s 3.5 1.5 s 1.5 10 s 10 ns ns ns ns s ms ns V/s Threshold low Threshold high 2.4 1.4 1.4 MAX225 MAX244MAX249 MAX225 MAX244MAX249 MAX225 MAX244MAX249 4.75 4.5 10 11 40 57 8 25 50 1 0.8 A A V 5.25 5.5 20 30 mA V CONDITIONS MIN TYP MAX UNITS

MAX220MAX249

Shutdown Supply Current

Receiver-Output Enable Time, Figure 3 tER Receiver-Output Disable Time, Figure 3 tDR

Transmitter Disable Time, Figure 4

tDT

Note 7: The 300 minimum specification complies with EIA/TIA-232E, but the actual resistance when in shutdown mode or VCC = 0V is 10M as is implied by the leakage specification.

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+5V-Powered, Multichannel RS-232 Drivers/Receivers MAX220MAX249

__________________________________________Typical Operating Characteristics
MAX225/MAX244MAX249
TRANSMITTER SLEW RATE vs. LOAD CAPACITANCE
MAX220-10

OUTPUT VOLTAGE vs. LOAD CURRENT FOR V+ AND VMAX220-11

TRANSMITTER OUTPUT VOLTAGE (V+, V-) vs. LOAD CAPACITANCE AT DIFFERENT DATA RATES
8.5 8.0 V+, V (V) 7.5 7.0 6.5 VCC = 5V WITH ALL TRANSMITTERS DRIVEN LOADED WITH 5k 10kb/sec 20kb/sec 40kb/sec 60kb/sec
MAX220-12

18 TRANSMITTER SLEW RATE (V/s) 16 14 12 10 8 6 4 2 0 1 2 3 4 5 LOAD CAPACITANCE (nF) VCC = 5V

10 8 6 OUTPUT VOLTAGE (V) V+ AND V- LOADED VCC = 5V EXTERNAL CHARGE PUMP 1F CAPACITORS 8 TRANSMITTERS DRIVING 5k AND 2000pF AT 20kbits/sec V+ AND V- LOADED V+ LOADED EITHER V+ OR V- LOADED

9.0

EXTERNAL POWER SUPPLY 1F CAPACITORS 40kb/s DATA RATE 8 TRANSMITTERS LOADED WITH 3k

4 2 0 -2 -4 -6 -8 -10 0

V- LOADED 6.0 5.5 5.0 5 10 15 20 25 30 35 0 LOAD CURRENT (mA) 1 200kb/sec ALL CAPACITIORS 1F 2 3 4 5 LOAD CAPACITANCE (nF) 100kb/sec

10

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+5V-Powered, Multichannel RS-232 Drivers/Receivers MAX220MAX249

+3V +3V INPUT 0V OUTPUT V+ OUTPUT 0V VVCC 50% 50% GND tPHLR tPHLS tPLHR tPLHS 0V* INPUT 50% 50%

tPLHT

tPHLT *EXCEPT FOR R2 ON THE MAX243 WHERE -3V IS USED.

Figure 1. Transmitter Propagation-Delay Timing

Figure 2. Receiver Propagation-Delay Timing

EN RX OUT RX IN a) TEST CIRCUIT 150pF EN INPUT +3V 0V V+ EN OUTPUT ENABLE TIME (tER) +3.5V RECEIVER OUTPUTS +0.8V a) TIMING DIAGRAM b) ENABLE TIMING +3V EN INPUT VOH RECEIVER OUTPUTS VOL c) DISABLE TIMING VOL + 0.5V 0V OUTPUT DISABLE TIME (tDR) VOH - 0.5V VCC - 2V b) TEST CIRCUIT EN 1 OR 0 TX 3k 50pF V+5V 0V -5V OUTPUT DISABLE TIME (tDT) RX 1k VCC - 2V SHDN +3V 0V

Figure 3. Receiver-Output Enable and Disable Timing

Figure 4. Transmitter-Output Disable Timing 11

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+5V-Powered, Multichannel RS-232 Drivers/Receivers MAX220MAX249

Table 1a. MAX245 Control Pin Configurations
ENT 0 0 1 1 ENR 0 1 0 1 OPERATION STATUS Normal Operation Normal Operation Shutdown Shutdown TRANSMITTERS All Active All Active All 3-State All 3-State All Active All 3-State All Low-Power Receive Mode All 3-State RECEIVERS

Table 1b. MAX245 Control Pin Configurations

ENT 0 0 ENR 0 1 OPERATION STATUS Normal Operation Normal Operation TRANSMITTERS TA1TA4 All Active All Active TB1TB4 All Active All Active RECEIVERS RA1RA5 All Active RA1RA4 3-State, RA5 Active All Low-Power Receive Mode RA1RA4 3-State, RA5 Low-Power Receive Mode RB1RB5 All Active RB1RB4 3-State, RB5 Active All Low-Power Receive Mode RB1RB4 3-State, RB5 Low-Power Receive Mode

Shutdown

All 3-State

All 3-State

Shutdown

All 3-State

All 3-State

Table 1c. MAX246 Control Pin Configurations

ENA 0 0 ENB 0 1 OPERATION STATUS Normal Operation Normal Operation TRANSMITTERS TA1TA4 All Active All Active TB1TB4 All Active All 3-State RECEIVERS RA1RA5 All Active All Active RA1RA4 3-State, RA5 Active RA1RA4 3-State, RA5 Low-Power Receive Mode RB1RB5 All Active RB1RB4 3-State, RB5 Active All Active RB1RB4 3-State, RA5 Low-Power Receive Mode

Shutdown

All 3-State

All Active

Shutdown

All 3-State

All 3-State

12

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+5V-Powered, Multichannel RS-232 Drivers/Receivers

Table 1d. MAX247/MAX248/MAX249 Control Pin Configurations
TRANSMITTERS ENTA ENTB ENRA ENRB OPERATION STATUS Normal Operation Normal Operation Normal Operation Normal Operation Normal Operation Normal Operation Normal Operation Normal Operation Normal Operation Normal Operation Normal Operation Normal Operation MAX247 MAX248 MAX249 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 TA1TA4 TA1TA4 TA1TA3 All Active All Active All Active All Active All Active All Active All Active All Active All 3-State All 3-State All 3-State All 3-State TB1TB4 TB1TB4 TB1TB3 All Active All Active All Active All Active All 3-State All 3-State All 3-State All 3-State All Active All Active All Active All Active RECEIVERS RA1RA4 RA1RA4 RA1RA5 All Active All Active All 3-State All 3-State All Active All Active All 3-State All 3-State All Active All Active All 3-State All 3-State RB1RB5 RB1RB4 RB1RB5 All Active All 3-State, except RB5 stays active on MAX247 All Active All 3-State, except RB5 stays active on MAX247 All Active All 3-State, except RB5 stays active on MAX247 All Active All 3-State, except RB5 stays active on MAX247 All Active All 3-State, except RB5 stays active on MAX247 All Active All 3-State, except RB5 stays active on MAX247 Low-Power Receive Mode All 3-State, except RB5 stays active on MAX247 Low-Power Receive Mode All 3-State, except RB5 stays active on MAX247

MAX220MAX249

Shutdown

All 3-State

All 3-State

Low-Power Receive Mode

Shutdown

All 3-State

All 3-State

Low-Power Receive Mode

Shutdown

All 3-State

All 3-State

All 3-State

Shutdown

All 3-State

All 3-State

All 3-State

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13

+5V-Powered, Multichannel RS-232 Drivers/Receivers MAX220MAX249

_______________Detailed Description
The MAX220MAX249 contain four sections: dual charge-pump DC-DC voltage converters, RS-232 drivers, RS-232 receivers, and receiver and transmitter enable control inputs. mode, in three-state mode, or when device power is removed. Outputs can be driven to 15V. The powersupply current typically drops to 8A in shutdown mode. The MAX220 does not have pull-up resistors to force the outputs of the unused drivers low. Connect unused inputs to GND or VCC. The MAX239 has a receiver three-state control line, and the MAX223, MAX225, MAX235, MAX236, MAX240, and MAX241 have both a receiver three-state control line and a low-power shutdown control. Table 2 shows the effects of the shutdown control and receiver threestate control on the receiver outputs. The receiver TTL/CMOS outputs are in a high-impedance, three-state mode whenever the three-state enable line is high (for the MAX225/MAX235/MAX236/MAX239 MAX241), and are also high-impedance whenever the shutdown control line is high. When in low-power shutdown mode, the driver outputs are turned off and their leakage current is less than 1A with the driver output pulled to ground. The driver output leakage remains less than 1A, even if the transmitter output is backdriven between 0V and (VCC + 6V). Below -0.5V, the transmitter is diode clamped to ground with 1k series impedance. The transmitter is also zener clamped to approximately V CC + 6V, with a series impedance of 1k. The driver output slew rate is limited to less than 30V/s as required by the EIA/TIA-232E and V.28 specifications. Typical slew rates are 24V/s unloaded and 10V/s loaded with 3 and 2500pF.

Dual Charge-Pump Voltage Converter

The MAX220MAX249 have two internal charge-pumps that convert +5V to 10V (unloaded) for RS-232 driver operation. The first converter uses capacitor C1 to double the +5V input to +10V on C3 at the V+ output. The second converter uses capacitor C2 to invert +10V to -10V on C4 at the V- output. A small amount of power may be drawn from the +10V (V+) and -10V (V-) outputs to power external circuitry (see the Typical Operating Characteristics section), except on the MAX225 and MAX245MAX247, where these pins are not available. V+ and V- are not regulated, so the output voltage drops with increasing load current. Do not load V+ and V- to a point that violates the minimum 5V EIA/TIA-232E driver output voltage when sourcing current from V+ and V- to external circuitry. When using the shutdown feature in the MAX222, MAX225, MAX230, MAX235, MAX236, MAX240, MAX241, and MAX245MAX249, avoid using V+ and Vto power external circuitry. When these parts are shut down, V- falls to 0V, and V+ falls to +5V. For applications where a +10V external supply is applied to the V+ pin (instead of using the internal charge pump to generate +10V), the C1 capacitor must not be installed and the SHDN pin must be tied to VCC. This is because V+ is internally connected to VCC in shutdown mode.

RS-232 Receivers
EIA/TIA-232E and V.28 specifications define a voltage level greater than 3V as a logic 0, so all receivers invert. Input thresholds are set at 0.8V and 2.4V, so receivers respond to TTL level inputs as well as EIA/TIA-232E and V.28 levels. The receiver inputs withstand an input overvoltage up to 25V and provide input terminating resistors with

RS-232 Drivers
The typical driver output voltage swing is 8V when loaded with a nominal 5k RS-232 receiver and VCC = +5V. Output swing is guaranteed to meet the EIA/TIA232E and V.28 specification, which calls for 5V minimum driver output levels under worst-case conditions. These include a minimum 3k load, VCC = +4.5V, and maximum operating temperature. Unloaded driver output voltage ranges from (V+ -1.3V) to (V- +0.5V). Input thresholds are both TTL and CMOS compatible. The inputs of unused drivers can be left unconnected since 400k input pull-up resistors to VCC are built in (except for the MAX220). The pull-up resistors force the outputs of unused drivers low because all drivers invert. The internal input pull-up resistors typically source 12A, except in shutdown mode where the pull-ups are disabled. Driver outputs turn off and enter a high-impedance statewhere leakage current is typically microamperes (maximum 25A)when in shutdown
14

Table 2. Three-State Control of Receivers

PART MAX223 SHDN SHDN __ Low High High __ EN X Low High __ EN(R) __ Low High Low High X RECEIVERS High Impedance Active High Impedance High Impedance Active High Impedance Active High Impedance

MAX225 MAX235 MAX236 MAX240

__ Low Low High

__

__

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+5V-Powered, Multichannel RS-232 Drivers/Receivers

nominal 5k values. The receivers implement Type 1 interpretation of the fault conditions of V.28 and EIA/TIA-232E. The receiver input hysteresis is typically 0.5V with a guaranteed minimum of 0.2V. This produces clear output transitions with slow-moving input signals, even with moderate amounts of noise and ringing. The receiver propagation delay is typically 600ns and is independent of input swing direction.

ShutdownMAX222MAX242
On the MAX222 MAX235 MAX236 MAX240 and MAX241 all receivers are disabled during shutdown. On the MAX223 and MAX242 two receivers continue to operate in a reduced power mode when the chip is in shutdown. Under these conditions the propagation delay increases to about 2.5s for a high-to-low input transition. When in shutdown, the receiver acts as a CMOS inverter with no hysteresis. The MAX223 and MAX242 also have a receiver output enable input (EN for the MAX242 and EN for the MAX223) that allows receiver output control independent of SHDN (SHDN for MAX241). With all other devices SHDN (SHDN for MAX241) also disables the receiver outputs. The MAX225 provides five transmitters and five receivers while the MAX245 provides ten receivers and eight transmitters. Both devices have separate receiver and transmitter-enable controls. The charge pumps turn off and the devices shut down when a logic high is applied to the ENT input. In this state, the supply current drops to less than 25A and the receivers continue to operate in a low-power receive mode. Driver outputs enter a high-impedance state (three-state mode). On the MAX225 all five receivers are controlled by the ENR input. On the MAX245 eight of the receiver outputs are controlled by the ENR input while the remaining two receivers (RA5 and RB5) are always active. RA1RA4 and RB1RB4 are put in a three-state mode when ENR is a logic high.

MAX220MAX249

Low-Power Receive Mode

The low-power receive-mode feature of the MAX223, MAX242, and MAX245MAX249 puts the IC into shutdown mode but still allows it to receive information. This is important for applications where systems are periodically awakened to look for activity. Using low-power receive mode, the system can still receive a signal that will activate it on command and prepare it for communication at faster data rates. This operation conserves system power.

Negative ThresholdMAX243
The MAX243 is pin compatible with the MAX232A, differing only in that RS-232 cable fault protection is removed on one of the two receiver inputs. This means that control lines such as CTS and RTS can either be driven or left floating without interrupting communication. Different cables are not needed to interface with different pieces of equipment. The input threshold of the receiver without cable fault protection is -0.8V rather than +1.4V. Its output goes positive only if the input is connected to a control line that is actively driven negative. If not driven, it defaults to the 0 or OK to send state. Normally the MAX243s other receiver (+1.4V threshold) is used for the data line (TD or RD) while the negative threshold receiver is connected to the control line (DTR DTS CTS RTS, etc.). Other members of the RS-232 family implement the optional cable fault protection as specified by EIA/TIA232E specifications. This means a receiver output goes high whenever its input is driven negative left floating or shorted to ground. The high output tells the serial communications IC to stop sending data. To avoid this the control lines must either be driven or connected with jumpers to an appropriate positive voltage level.

Receiver and Transmitter Enable Control Inputs

The MAX225 and MAX245MAX249 feature transmitter and receiver enable controls. The receivers have three modes of operation: full-speed receive (normal active) three-state (disabled) and lowpower receive (enabled receivers continue to function at lower data rates). The receiver enable inputs control the full-speed receive and three-state modes. The transmitters have two modes of operation: full-speed transmit (normal active) and three-state (disabled). The transmitter enable inputs also control the shutdown mode. The device enters shutdown mode when all transmitters are disabled. Enabled receivers function in the low-power receive mode when in shutdown.

______________________________________________________________________________________

15

+5V-Powered, Multichannel RS-232 Drivers/Receivers MAX220MAX249

Tables 1a1d define the control states. The MAX244 has no control pins and is not included in these tables. The MAX246 has ten receivers and eight drivers with two control pins, each controlling one side of the device. A logic high at the A-side control input (ENA) causes the four A-side receivers and drivers to go into a three-state mode. Similarly, the B-side control input (ENB) causes the four B-side drivers and receivers to go into a three-state mode. As in the MAX245, one Aside and one B-side receiver (RA5 and RB5) remain active at all times. The entire device is put into shutdown mode when both the A and B sides are disabled (ENA = ENB = +5V). The MAX247 provides nine receivers and eight drivers with four control pins. The ENRA and ENRB receiver enable inputs each control four receiver outputs. The ENTA and ENTB transmitter enable inputs each control four drivers. The ninth receiver (RB5) is always active. The device enters shutdown mode with a logic high on both ENTA and ENTB. The MAX248 provides eight receivers and eight drivers with four control pins. The ENRA and ENRB receiver enable inputs each control four receiver outputs. The ENTA and ENTB transmitter enable inputs control four drivers each. This part does not have an always-active receiver. The device enters shutdown mode and transmitters go into a three-state mode with a logic high on both ENTA and ENTB. The MAX249 provides ten receivers and six drivers with four control pins. The ENRA and ENRB receiver enable inputs each control five receiver outputs. The ENTA and ENTB transmitter enable inputs control three drivers each. There is no always-active receiver. The device enters shutdown mode and transmitters go into a three-state mode with a logic high on both ENTA and ENTB. In shutdown mode, active receivers operate in a low-power receive mode at data rates up to 20kb/s.

__________Applications Information
Figures 5 through 25 show pin configurations and typical operating circuits. In applications that are sensitive to power-supply noise, VCC should be decoupled to ground with a capacitor of the same value as C1 and C2 connected as close as possible to the device.

16

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+5V-Powered, Multichannel RS-232 Drivers/Receivers MAX220MAX249

+5V INPUT C3

TOP VIEW
C5 C1+ 1 V+ 2 C1- 3 C2+ 4 C2- 5 V- 6 T2OUT 7 R2IN 8 16 VCC 15 GND 14 T1OUT C2 1 C1 C1+ 16 VCC +5V TO +10V VOLTAGE DOUBLER V+ 2 +10V 6 -10V C4

3 C14 C2+ +10V TO -10V 5 C2- VOLTAGE INVERTER +5V 400k 11 T1IN

V-

MAX220 MAX232 MAX232A

13 R1IN 12 R1OUT 11 T1IN 10 T2IN 9 R2OUT TTL/CMOS INPUTS

T1OUT 14 RS-232 OUTPUTS T2OUT 7 R1IN 13 5k RS-232 INPUTS

+5V 400k 10 T2IN 12 R1OUT

DIP/SO
CAPACITANCE (F) DEVICE C1 C2 C3 C4 C5 MAX220 0.047 0.33 0.33 0.33 0.33 MAX232 1.0 1.0 1.0 1.0 1.0 MAX232A 0.1 0.1 0.1 0.1 0.1 TTL/CMOS OUTPUTS

9 R2OUT

R2IN 8 5k GND 15

Figure 5. MAX220/MAX232/MAX232A Pin Configuration and Typical Operating Circuit

+5V INPUT C3 ALL CAPACITORS = 0.1F C5 17 VCC 3 +10V C1+ +5V TO +10V V+ 4 C1- VOLTAGE DOUBLER 5 C2+ 7 -10V +10V TO -10V V6 C2C4 VOLTAGE INVERTER 2 +5V 400k 12 T1IN TTL/CMOS INPUTS +5V 400k 11 T2IN 13 R1OUT TTL/CMOS OUTPUTS 10 R2OUT 1 (N.C.) EN ( ) ARE FOR MAX222 ONLY. PIN NUMBERS IN TYPICAL OPERATING CIRCUIT ARE FOR DIP/SO PACKAGES ONLY. GND 16 (EXCEPT MAX220) T2OUT 8 R1IN 14 5k R2IN 9 5k SHDN 18 RS-232 INPUTS (EXCEPT MAX220) T1OUT 15 RS-232 OUTPUTS

TOP VIEW

(N.C.) EN 1 (N.C.) EN 1 C1+ 2 V+ 3 C1- 4 C2+ 5 C2- 6 V- 7 T2OUT 8 R2IN 9 18 SHDN 17 VCC 16 GND 15 T1OUT C1+ 2 V+ 3 C1- 4 C2+ 5 C2- 6 V- 7 T2OUT 8 R2IN 9 R2OUT 10

20 SHDN 19 VCC 18 GND 17 T1OUT

C1

C2

MAX222 MAX242

MAX222 MAX242

16 N.C. 15 R1IN 14 R1OUT 13 N.C. 12 T1IN 11 T2IN

14 R1IN 13 R1OUT 12 T1IN 11 T2IN 10 R2OUT

DIP/SO

SSOP

Figure 6. MAX222/MAX242 Pin Configurations and Typical Operating Circuit ______________________________________________________________________________________ 17

+5V-Powered, Multichannel RS-232 Drivers/Receivers MAX220MAX249

+5V

TOP VIEW

0.1 +5V T1IN +5V 400k 4 T2IN +5V 400k 25 T3IN +5V 400k 24 T4IN +5V 400k 23 26 5 T5IN ENT T5OUT R1OUT R1IN 5k 6 R2OUT R2IN 5k 7 R3OUT R3IN 5k 22 R4OUT R4IN 5k 21 R5OUT R5IN 5k 1 2 ENR ENR 20 19 8 9 T5OUT 16 15 10 T4OUT 17 T3OUT 18 T2OUT 12 T1OUT 28 VCC 400k 3 ENR 1 ENR 2 T1IN 3 T2IN 4 R1OUT 5 R2OUT 6 R3OUT 7 R3IN 8 R2IN 9 R1IN 10 T1OUT 11 T2OUT 12 GND 13 GND 14 28 VCC 27 VCC 26 ENT 25 T3IN 11 27 VCC

MAX225

24 T4IN 23 T5IN 22 R4OUT 21 R5OUT 20 R5IN 19 R4IN 18 T3OUT 17 T4OUT 16 T5OUT 15 T5OUT

SO

MAX225 FUNCTIONAL DESCRIPTION 5 RECEIVERS 5 TRANSMITTERS 2 CONTROL PINS 1 RECEIVER ENABLE (ENR) 1 TRANSMITTER ENABLE (ENT)

PINS (ENR, GND, VCC, T5OUT) ARE INTERNALLY CONNECTED. CONNECT EITHER OR BOTH EXTERNALLY. T5OUT IS A SINGLE DRIVER.

GND 13

GND 14

Figure 7. MAX225 Pin Configuration and Typical Operating Circuit

18

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+5V-Powered, Multichannel RS-232 Drivers/Receivers MAX220MAX249

TOP VIEW
+5V INPUT 1.0F 11 VCC +5V TO +10V VOLTAGE DOUBLER +10V TO -10V VOLTAGE INVERTER +5V 400k 7 T1IN T3OUT 1 T1OUT 2 T2OUT 3 R2IN 4 R2OUT 5 T2IN 6 T1IN 7 R1OUT 8 R1IN 9 GND 10 VCC 11 C1+ 12 V+ 13 C1- 14 28 T4OUT 27 R3IN 26 R3OUT 25 SHDN (SHDN) 24 EN (EN) TTL/CMOS INPUTS 20 T3IN +5V 400k 21 T4IN T4 T4OUT 28 6 T2IN +5V 400k T3 T3OUT 1 RS-232 OUTPUTS +5V 400k T2 T2OUT 3 T1 T1OUT 2

12 1.0F 1.0F

C1+

1.0F V+ 13

14 C115 C2+ 16 C2-

V-

17 1.0F

MAX223 MAX241

23 R4IN* 22 R4OUT* 21 T4IN 20 T3IN 19 R5OUT* 18 R5IN* 17 V16 C215 C2+

8 R1OUT

R1

R1IN 9 5k

5 R2OUT

R2

R2IN 4 5k

Wide SO/ SSOP

LOGIC OUTPUTS

26 R3OUT

R3

R3IN 5k

27

RS-232 INPUTS

22 R4OUT

R4

R4IN 5k

23

19 R5OUT *R4 AND R5 IN MAX223 REMAIN ACTIVE IN SHUTDOWN NOTE: PIN LABELS IN ( ) ARE FOR MAX241 24 EN (EN)

R5

R5IN

18

GND 10

5k SHDN 25 (SHDN)

Figure 8. MAX223/MAX241 Pin Configuration and Typical Operating Circuit

______________________________________________________________________________________

19

+5V-Powered, Multichannel RS-232 Drivers/Receivers MAX220MAX249

TOP VIEW
8 C1+ 10 C11.0F +5V INPUT 1.0F

1.0F T3OUT 1 20 T4OUT 19 T5IN 18 N.C. 17 SHDN 1.0F

7 VCC V+ 9 +5V TO +10V VOLTAGE DOUBLER V13

T1OUT 2 T2OUT 3 T2IN 4 T1IN 5 GND 6 VCC 7 C1+ 8 V+ 9 C1- 10

11 +10V TO -10V C2+ 12 C2- VOLTAGE INVERTER +5V 5 T1IN +5V 4 T2IN +5V 400k 400k T1 400k T2

1.0F

T1OUT 2

MAX230

16 T5OUT 15 T4IN 14 T3IN 13 V12 C211 C2+ TTL/CMOS INPUTS 14 T3IN

T2OUT 3

T3 +5V 400k T4 400k

T3OUT 1

RS-232 OUTPUTS

15 T4IN +5V

T4OUT 20

DIP/SO

19 T5IN N.C. x 18

T5 GND 6

T5OUT 16 17 SHDN

Figure 9. MAX230 Pin Configuration and Typical Operating Circuit

+5V INPUT

TOP VIEW
1 1.0F C+ 1 CV2 3 14 V+ 13 VCC 12 GND C+ 1 C- 2 V- 3 T2OUT 4 R2IN 5 R2OUT 6 T2IN 7 N.C. 8 16 V+ 15 VCC 14 GND TTL/CMOS INPUTS 7 (11) TTL/CMOS OUTPUTS 9 (10) 8 T1IN 2

1.0F 13 (15) C1+ C1+5V 400k T1 400k T2IN R1OUT T2 R1 5k 6 R2OUT VCC +12V TO -12V VOLTAGE CONVERTER

+7.5V TO +12V

V+ V-

14 3

(16) C2 1.0F (13)

T1OUT 11

+5V RS-232 OUTPUTS T2OUT 4 R1IN 10 (12)

T2OUT 4 R2IN 5 R2OUT 6 T2IN 7

MAX231

11 T1OUT 10 R1IN 9 8 R1OUT T1IN

MAX231

13 T1OUT 12 R1IN 11 R1OUT 10 T1IN 9 N.C.

DIP SO

RS-232 INPUTS R2IN 5

R2

5k GND PIN NUMBERS IN ( ) ARE FOR SO PACKAGE 12 (14)

Figure 10. MAX231 Pin Configurations and Typical Operating Circuit 20 ______________________________________________________________________________________

+5V-Powered, Multichannel RS-232 Drivers/Receivers MAX220MAX249

+5V INPUT 1.0F

TOP VIEW
+5V 400k T2IN 1 20 R2OUT 19 R2IN 18 T2OUT 17 VTTL/CMOS INPUTS 1 3 TTL/CMOS OUTPUTS 20 R2OUT 8 (13) DO NOT MAKE CONNECTIONS TO 13 (14) THESE PINS 12 (10) INTERNAL -10 17 POWER SUPPLY INTERNAL +10V POWER SUPPLY ( ) ARE FOR SO PACKAGE ONLY. C1+ C1VT2IN R1OUT 2 T1IN +5V 400k VCC

T1OUT 5 RS-232 OUTPUTS T2OUT 18 R1IN 4 5k RS-232 INPUTS R2IN 19 5k C2+ 11 (12) C2+ C2C2GND 6 GND 9 10 (11) 15 16

T1IN 2 R1OUT 3 R1IN 4 T1OUT 5 GND 6 VCC 7 (V+) C1+ 8 GND 9 (V-) CS- 10

MAX233 MAX233A

16 C215 C2+ 14 V+ (C1-) 13 C1- (C1+) 12 V- (C2+) 11 C2+ (C2-)

DIP/SO

V14 (8) V+

Figure 11. MAX233/MAX233A Pin Configuration and Typical Operating Circuit

+5V INPUT

TOP VIEW
7 1.0F 9 10 T1OUT 1 T2OUT 2 T2IN 3 T1IN 4 GND 5 VCC 6 C1+ 7 V+ 8 16 T3OUT 15 T4OUT 14 T4IN 4 T1IN 1.0F C1+ C1C2+

1.0F 6 VCC +5V TO +10V VOLTAGE DOUBLER +10V TO -10V VOLTAGE INVERTER +5V 400k
T1

1.0F 8 V+ 12 1.0F

11 C2-

V-

T1OUT 1

MAX234

13 T3IN 12 V11 C210 C2+ 9 C1TTL/CMOS INPUTS 13 T3IN 3 T2IN

+5V 400k
T2

T2OUT 3 RS-232 OUTPUTS

+5V 400k
T3

T3OUT 16

DIP/SO
14 T4IN

+5V 400k
T4

T4OUT 15

GND 5

Figure 12. MAX234 Pin Configuration and Typical Operating Circuit ______________________________________________________________________________________ 21

+5V-Powered, Multichannel RS-232 Drivers/Receivers MAX220MAX249

+5V INPUT

TOP VIEW

1.0F 12 +5V 8 T1IN +5V 7 T2IN +5V TTL/CMOS INPUTS 15 T3IN +5V 16 T4IN +5V 22 T5IN 400k T5 T5OUT 19 VCC 400k T1 T1OUT 3

400k T2 400k T3 400k T4 T4OUT 1 T3OUT 2 RS-232 OUTPUTS T2OUT 4

T4OUT 1 T3OUT 2 T1OUT 3 T2OUT 4 R2IN 5 R2OUT 6 T2IN 7 T1IN 8 R1OUT 9 R1IN 10 GND 11 VCC 12

24 R3IN 23 R3OUT 22 T5IN 21 SHDN

MAX235

20 EN 19 T5OUT 18 R4IN 17 R4OUT 16 T4IN 15 T3IN 14 R5OUT 13 R5IN

9 R1OUT

T1

R1IN 10 5k

6 R2OUT

R2

R2IN 5 5k

DIP

TTL/CMOS OUTPUTS

23 R3OUT

R3

R3IN 24 5k

RS-232 INPUTS

17 R4OUT

R4

R4IN 18 5k

14 R5OUT

R5

R5IN 13 5k SHDN 21

20 EN GND 11

Figure 13. MAX235 Pin Configuration and Typical Operating Circuit

22

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+5V-Powered, Multichannel RS-232 Drivers/Receivers MAX220MAX249

TOP VIEW
1.0F

+5V INPUT

9 10 1.0F 12 13 1.0F C1+ C1C2+ +10V TO -10V VOLTAGE INVERTER +5V 400k 7 T1IN T3OUT 1 T1OUT 2 T2OUT 3 R1IN 4 R1OUT 5 T2IN 6 T1IN 7 GND 8 VCC 9 C1+ 10 V+ 11 C1- 12 24 T4OUT 23 R2IN 22 R2OUT 21 SHDN TTL/CMOS INPUTS 18 T3IN +5V 400k 19 T4IN T4 T4OUT 24 6 T2IN +5V 400k T3 T3OUT 1 +5V 400k T2 T2OUT 3 T1 T1OUT 2 VCC +5V TO +10V VOLTAGE DOUBLER V+ 11

1.0F

V-

15 1.0F

14 C2-

MAX236

20 EN 19 T4IN 18 T3IN 17 R3OUT 16 R3IN 15 V14 C213 C2+ 5 R1OUT

RS-232 OUTPUTS

R1

R1IN 4 5k

DIP/SO
TTL/CMOS OUTPUTS 22 R2OUT R2 R2IN 5k 17 R3OUT R3IN 5k 20 EN GND 8 SHDN 21 16 23 RS-232 INPUTS

R3

Figure 14. MAX236 Pin Configuration and Typical Operating Circuit

______________________________________________________________________________________

23

+5V-Powered, Multichannel RS-232 Drivers/Receivers MAX220MAX249

TOP VIEW
+5V INPUT 1.0F 9 VCC +5V TO +10V VOLTAGE DOUBLER +10V TO -10V VOLTAGE INVERTER +5V 400k T3OUT 1 T1OUT 2 T2OUT 3 R1IN 4 R1OUT 5 T2IN 6 T1IN 7 GND 8 VCC 9 C1+ 10 V+ 11 C1- 12 24 T4OUT 23 R2IN 22 R2OUT 21 T5IN 6 T2IN +5V 7 T1IN +5V 400k T2 400k TTL/CMOS INPUTS 18 T3IN +5V T3 400k 19 T4IN +5V T4 400k 21 T5IN T5 T5OUT 20 T4OUT 24 T3OUT 1 RS-232 OUTPUTS T2OUT 3 T1 T1OUT 2 1.0F V+ 11

10 1.0F 12 13 1.0F 14

C1+ C1C2+ C2-

V-

15 1.0F

MAX237

20 T5OUT 19 T4IN 18 T3IN 17 R3OUT 16 R3IN 15 V14 C213 C2+

DIP/SO

5 R1OUT

R1

R1IN 4 5k

TTL/CMOS OUTPUTS

22 R2OUT

R2

R2IN 5k

23

RS-232 INPUTS

17 R3OUT

R3

R3IN 5k

16

GND 8

Figure 15. MAX237 Pin Configuration and Typical Operating Circuit

24

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+5V-Powered, Multichannel RS-232 Drivers/Receivers MAX220MAX249

TOP VIEW
+5V INPUT 1.0F 9 10 1.0F 12 13 1.0F 14 C1+ C1C2+ C2+5V 400k T2OUT 1 T1OUT 2 R2IN 3 R2OUT 4 T1IN 5 R1OUT 6 R1IN 7 GND 8 VCC 9 C1+ 10 V+ 11 C1- 12 24 T3OUT 23 R3IN 22 R3OUT 21 T4IN 18 T2IN TTL/CMOS INPUTS 19 T3IN +5V 400k 21 T4IN T4 T4OUT 20 +5V 400k T3 T3OUT 24 5 T1IN +5V T1 400k T2 T2OUT 1 RS-232 OUTPUTS T1OUT 2 +10V TO -10V VOLTAGE INVERTER VVCC +5V TO +10V VOLTAGE DOUBLER V+ 11 1.0F

15 1.0F

MAX238

20 T4OUT 19 T3IN 18 T2IN 17 R4OUT 16 R4IN 15 V14 C213 C2+

6 R1OUT

R1

R1IN 7 5k

DIP/SO
4 R2OUT TTL/CMOS OUTPUTS 22 R3OUT R3 R2

R2IN 5k R3IN 5k

3 RS-232 INPUTS 23

17 R4OUT

R4

R4IN 5k

16

GND 8

Figure 16. MAX238 Pin Configuration and Typical Operating Circuit

______________________________________________________________________________________

25

+5V-Powered, Multichannel RS-232 Drivers/Receivers MAX220MAX249

TOP VIEW
+5V INPUT 1.0F 4 6 1.0F 7 C1+ C1+5V 400k 24 T1IN R1OUT 1 R1IN 2 GND 3 VCC 4 V+ 5 C+ 6 C- 7 V- 8 R5IN 9 R5OUT 10 R4OUT 11 R4IN 12 24 T1IN 23 T2IN 22 R2OUT 21 R2IN TTL/CMOS INPUTS 23 T2IN +5V 400k 16 T3IN T3 T3OUT 13 +5V 400k T2 T2OUT 20 RS-232 OUTPUTS T1 T1OUT 19 VCC +10V TO -10V VOLTAGE INVERTER 5 V+ V8 1.0F 7.5V TO 13.2V INPUT

MAX239

20 T2OUT 19 T1OUT 18 R3IN 17 R3OUT 16 T3IN 15 N.C. 14 EN 13 T3OUT

1 R1OUT

R1

R1IN 2 5k

22 R2OUT

R2

R2IN 21 5k

DIP/SO
TTL/CMOS OUTPUTS

17 R3OUT

R3

R3IN 5k

18

RS-232 INPUTS

11 R4OUT

R4

R4IN 5k

12

10 R5OUT

R5

R5IN 5k N.C.

14 EN GND 3

15

Figure 17. MAX239 Pin Configuration and Typical Operating Circuit

26

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+5V-Powered, Multichannel RS-232 Drivers/Receivers MAX220MAX249

+5V INPUT

TOP VIEW
25 1.0F 1.0F

1.0F 19 VCC +5V TO +10V VOLTAGE DOUBLER +5V TO -10V VOLTAGE INVERTER +5V 15 T1IN +5V 14 T2IN N.C. R2IN N.C. T2OUT T1OUT T3OUT T4OUT R3IN R3OUT T5IN N.C. +5V TTL/CMOS INPUTS 37 T3IN +5V 400k T4 400k T5 R1 T5OUT 41 T4OUT 5 400k T3 T3OUT 6 RS-232 OUTPUTS 400k T2 T2OUT 8 1.0F V+ 26

C1+

27 C128 C2+ 29 C2-

V-

30 1.0F

400k T1 T1OUT 7

11 10 9 8 7 6 5 4 3 2 1 44 43 42 41 40 39 38 37 36 35 34

N.C. R2OUT T2IN T1IN R1OUT R1IN GND VCC N.C. N.C. N.C.

12 13 14 15 16 17 18 19 20 21 22

MAX240

N.C. SHDN EN T5OUT R4IN R4OUT T4IN T3IN R5OUT R5IN N.C.

38 T4IN +5V 2 T5IN 16 R1OUT

R1IN 17 5k

13 R2OUT

R2

R2IN 10 5k

23 24 25 26 27 28 29 30 31 32 33

N.C. N.C. C1+ V+ C1C2+ C2 VN.C. N.C. N.C.

TTL/CMOS OUTPUTS

3 R3OUT

R3

R3IN 5k

RS-232 INPUTS

Plastic FP
39 R4OUT R4 R4IN 5k 36 R5OUT R5 R5IN 5k 42 EN GND 18 SHDN 43 35 40

Figure 18. MAX240 Pin Configuration and Typical Operating Circuit

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27

+5V-Powered, Multichannel RS-232 Drivers/Receivers MAX220MAX249

TOP VIEW
0.1F +5V INPUT ALL CAPACITORS = 0.1F 0.1F

1 0.1F C1+ 1 V+ 2 C1- 3 C2+ 4 C2- 5 V- 6 T2OUT 7 R2IN 8 16 VCC 15 GND 14 T1OUT

C1+

3 C14 C2+ 5 C2-

16 VCC +5V TO +10V VOLTAGE DOUBLER +10V TO -10V VOLTAGE INVERTER +5V 400k

V+

+10V

0.1F

V-

-10V 0.1F

MAX243

13 R1IN 12 R1OUT 11 T1IN 10 T2IN 9 R2OUT TTL/CMOS INPUTS 10 T2IN 11 T1IN +5V

T1OUT 14 RS-232 OUTPUTS T2OUT 7

400k

DIP/SO
12 R1OUT TTL/CMOS OUTPUTS 9 R2OUT RECEIVER INPUT -3 V OPEN +3V R1 OUTPUT HIGH HIGH LOW R2 OUTPUT HIGH LOW LOW 5k GND 15 5k R2IN 8 R1IN 13 RS-232 INPUTS

Figure 19. MAX243 Pin Configuration and Typical Operating Circuit

28

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+5V-Powered, Multichannel RS-232 Drivers/Receivers MAX220MAX249

+5V

TOP VIEW
1F 21 TA4OUT TB4OUT TA3OUT TA2OUT TA1OUT TB1OUT TB2OUT TB3OUT RA4IN RA5IN RB5IN 1F 1F C1+ 23 C124 C2+ 25 C22 TA1OUT 15 TA1IN 2 TA2OUT 16 TA2IN 3 TA3OUT 17 TA3IN 4 TA4OUT 18 TA4IN 9 RA1IN 5k 10 RA1OUT 8 RA2IN 5k 11 RA2OUT 7 RA3IN 5k 12 RA3OUT 6 RA4IN 5k 13 RA4OUT 5 RA5IN 5k 14 RA5OUT +5V 400k +5V +5V 400k +5V +5V 400k +5V 20 VCC +5V TO +10V VOLTAGE DOUBLER

1F

22 V+ 26 V- 1F

44 43 42 41 40

+10V TO -10V VOLTAGE INVERTER +5V 400k +5V

TB1OUT 44 TB1IN 30 TB2OUT 43 TB2IN 29 TB3OUT 42 TB3IN 28 TB4OUT 41 TB4IN 27 RB1IN 36 5k RB1OUT 35 RB2IN 37 5k RB2OUT 34 RB3IN 38 5k RB3OUT 33 RB4IN 39 5k RB4OUT 32 RB5IN 40 5k RB5OUT 31

RA3IN RA2IN RA1IN RA1OUT RA2OUT RA3OUT RA4OUT RA5OUT TA1IN TA2IN TA3IN

7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

39 RB4IN 38 RB3IN 37 RB2IN 36 RB1IN 35 RB1OUT 34 RB2OUT 33 RB3OUT 32 RB4OUT 31 RB5OUT 30 TB1IN 29 TB2IN

MAX244

GND

C1+

C1-

C2+

C2-

V+

TA4IN

V-

TB4IN

PLCC

MAX249 FUNCTIONAL DESCRIPTION 10 RECEIVERS 5 A-SIDE RECEIVER 5 B-SIDE RECEIVER 8 TRANSMITTERS 4 A-SIDE TRANSMITTERS 4 B-SIDE TRANSMITTERS NO CONTROL PINS

TB3IN

VCC

GND 19

Figure 20. MAX244 Pin Configuration and Typical Operating Circuit ______________________________________________________________________________________ 29

+5V-Powered, Multichannel RS-232 Drivers/Receivers MAX220MAX249

+5V

TOP VIEW

1F 40 VCC ENR TA1IN TA2IN TA3IN TA4IN RA5OUT RA4OUT RA3OUT RA2OUT RA1OUT RA1IN RA2IN RA3IN RA4IN RA5IN TA1OUT TA2OUT TA3OUT TA4OUT GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 VCC ENT TB1IN TB2IN TB3IN TB4IN RB5OUT RB4OUT RB3OUT RB2OUT RB1OUT RB1IN RB2IN RB3IN RB4IN RB5IN TB1OUT TB2OUT TB3OUT TB4OUT 9 RA2OUT RB2OUT 31 RB3IN 27 5k RB3OUT 32 RB4IN 26 5k RB4OUT 33 RB5IN 25 5k RB5OUT 34 GND 20 13 RA3IN 5k 10 RA1OUT 12 RA2IN 5k RB1OUT 30 RB2IN 28 5k 11 RA1IN 5k RB1IN 29 5k 18 TA3OUT 4 TA3IN 19 TA4OUT 5 TA4IN 1 ENR +5V 400k TB4IN 35 ENT 39 +5V +5V 400k TB3IN 36 TB4OUT 21 +5V TB3OUT 22 17 TA2OUT 3 TA2IN +5V 400k TB2IN 37 +5V TB2OUT 23 16 TA1OUT 2 TA1IN +5V 400k TB1IN 38 +5V TB1OUT 24

MAX245

34 33 32 31 30 29 28 27 26 25 24 23 22 21

DIP

MAX245 FUNCTIONAL DESCRIPTION 10 RECEIVERS 5 A-SIDE RECEIVERS (RA5 ALWAYS ACTIVE) 5 B-SIDE RECEIVERS (RB5 ALWAYS ACTIVE) 8 TRANSMITTTERS 4 A-SIDE TRANSMITTERS 2 CONTROL PINS 1 RECEIVER ENABLE (ENR) 1 TRANSMITTER ENABLE (ENT)

8 RA3OUT 14 RA4IN 5k 7 RA4OUT 15 RA5IN 5k 6 RA5OUT

Figure 21. MAX245 Pin Configuration and Typical Operating Circuit 30 ______________________________________________________________________________________

+5V-Powered, Multichannel RS-232 Drivers/Receivers MAX220MAX249

+5V

TOP VIEW
1F 40 VCC +5V +5V 16 TA1OUT 400k 2 TA1IN +5V 17 TA2OUT 400k 3 TA2IN +5V 18 TA3OUT 400k 4 TA3IN +5V 19 TA4OUT 400k 5 TA4IN 1 ENA 11 RA1IN 5k 10 RA1OUT 12 RA2IN 5k 9 RA2OUT 13 RA3IN 5k 8 RA3OUT 14 RA4IN 5k 7 RA4OUT 15 RA5IN 5k 6 RA5OUT GND 20 TB4IN 35 ENB 39 RB1IN 29 5k RB1OUT 30 RB2IN 28 5k RB2OUT 31 RB3IN 27 5k RB3OUT 32 RB4IN 26 5k RB4OUT 33 RB5IN 25 5k RB5OUT 34 +5V TB4OUT 21 TB3IN 36 +5V TB3OUT 22 TB2IN 37 +5V TB2OUT 23 TB1IN 38 TB1OUT 24

ENA TA1IN TA2IN TA3IN TA4IN RA5OUT RA4OUT RA3OUT RA2OUT RA1OUT RA1IN RA2IN RA3IN RA4IN RA5IN TA1OUT TA2OUT TA3OUT TA4OUT GND

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

40 39 38 37 36 35

VCC ENB TB1IN TB2IN TB3IN TB4IN RB5OUT RB4OUT RB3OUT RB2OUT RB1OUT RB1IN RB2IN RB3IN RB4IN RB5IN TB1OUT TB2OUT TB3OUT TB4OUT

MAX246

34 33 32 31 30 29 28 27 26 25 24 23 22 21

DIP

MAX246 FUNCTIONAL DESCRIPTION 10 RECEIVERS 5 A-SIDE RECEIVERS (RA5 ALWAYS ACTIVE) 5 B-SIDE RECEIVERS (RB5 ALWAYS ACTIVE) 8 TRANSMITTERS 4 A-SIDE TRANSMITTERS 4 B-SIDE TRANSMITTERS 2 CONTROL PINS ENABLE A-SIDE (ENA) ENABLE B-SIDE (ENB)

Figure 22. MAX246 Pin Configuration and Typical Operating Circuit ______________________________________________________________________________________ 31

+5V-Powered, Multichannel RS-232 Drivers/Receivers MAX220MAX249

+5V

TOP VIEW

1F 1 ENTA ENTA TA1IN TA2IN TA3IN TA4IN RB5OUT RA4OUT RA3OUT RA2OUT RA1OUT ENRA RA1IN RA2IN RA3IN RA4IN TA1OUT TA2OUT TA3OUT TA4OUT GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 VCC ENTB TB1IN TB2IN TB3IN TB4IN RB4OUT RB3OUT RB2OUT RB1OUT ENRB RB1IN RB2IN RB3IN RB4IN RB5IN TB1OUT TB2OUT TB3OUT TB4OUT 12 RA1IN 5k 10 RA1OUT 13 RA2IN RB1IN 29 5k RB1OUT 31 RB2IN 28 5k RB2OUT 32 RB3IN 27 5k RB3OUT 33 RB4IN 26 5k RB4OUT 34 ENRB 30 GND 20 5k 19 TA4OUT 400k 5 TA4IN 6 RB5OUT TB4IN 35 RB5IN 25 18 TA3OUT 400k 4 TA3IN +5V +5V TB4OUT 21 TB3IN 36 2 TA1IN +5V 17 TA2OUT 400k 3 TA2IN +5V +5V TB3OUT 22 TB2IN 37 +5V TB2OUT 23 16 TA1OUT 400k TB1IN 38 40 VCC +5V +5V ENTB 39 TB1OUT 24

MAX247

34 33 32 31 30 29 28 27 26 25 24 23 22 21

DIP
5k

MAX247 FUNCTIONAL DESCRIPTION 9 RECEIVERS 4 A-SIDE RECEIVERS 5 B-SIDE RECEIVERS (RB5 ALWAYS ACTIVE) 8 TRANSMITTERS 4 A-SIDE TRANSMITTERS 4 B-SIDE TRANSMITTERS 4 CONTROL PINS ENABLE RECEIVER A-SIDE (ENRA) ENABLE RECEIVER B-SIDE (ENRB) ENABLE RECEIVER A-SIDE (ENTA) ENABLE RECEIVERr B-SIDE (ENTB)

9 RA2OUT 14 RA3IN 5k 8 RA3OUT 15 RA4IN 5k 7 RA4OUT 11 ENRA

Figure 23. MAX247 Pin Configuration and Typical Operating Circuit 32 ______________________________________________________________________________________

+5V-Powered, Multichannel RS-232 Drivers/Receivers MAX220MAX249

TOP VIEW
1F 21 TA4OUT TA3OUT TA2OUT TA1OUT TB1OUT TB2OUT TB3OUT TA4OUT RA3IN RA4IN RB4IN 1F 1F 20 VCC +5V TO +10V VOLTAGE DOUBLER +10V TO -10V VOLTAGE INVERTER ENTB 27 +5V 1 TA1OUT RA2IN RA1IN ENRA RA1OUT RA2OUT RA3OUT RA4OUT TA1IN TA2IN TA3IN TA4IN
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 39 RB3IN 38 RB2IN 37 RB1IN 36 ENRB

+5V 1F

44 43 42 41 40

C1+ 23 C124 C2+ 25 C218 ENTA

V+ V-

22 26 1F

+5V TB1OUT 44

400k 14 TA1IN +5V 2 TA2OUT 400k 15 TA2IN +5V 3 TA3OUT 400k 16 TA3IN +5V 4 TA4OUT 400k 17 TA4IN 8 RA1IN 5k TB4IN 28 RB1IN 37 5k RB1OUT 35 RB2IN 38 5k RB2OUT 34 RB3IN 39 5k RB3OUT 33 RB4IN 40 5k RB4OUT 32 ENRB 36 GND 19 +5V TB4OUT 41 TB3IN 29 +5V TB3OUT 42 TB2IN 30 +5V TB2OUT 43 TB1IN 31

MAX248

35 RB1OUT 34 RB2OUT 33 RB3OUT 32 RB4OUT 31 TB1IN 30 TB2IN 29 TB3IN

GND

C1+

C1-

C2+

ENTA

C2-

ENTB

V+

V-

PLCC

MAX248 FUNCTIONAL DESCRIPTION

8 RECEIVERS 4 A-SIDE RECEIVERS 4 B-SIDE RECEIVERS 8 TRANSMITTERS 4 A-SIDE TRANSMITTERS 4 B-SIDE TRANSMITTERS 4 CONTROL PINS ENABLE RECEIVER A-SIDE (ENRA) ENABLE RECEIVER B-SIDE (ENRB) ENABLE RECEIVER A-SIDE (ENTA) ENABLE RECEIVER B-SIDE (ENTB)

TB4IN

VCC

10 RA1OUT 7 RA2IN 5k 11 RA2OUT 6 RA3IN 5k 12 RA3OUT 5 RA4IN 5k 13 RA4OUT 9 ENRA

Figure 24. MAX248 Pin Configuration and Typical Operating Circuit ______________________________________________________________________________________ 33

+5V-Powered, Multichannel RS-232 Drivers/Receivers MAX220MAX249

TOP VIEW
1F 21 TA3OUT TA2OUT TA1OUT TB1OUT TB2OUT TB3OUT RA3IN RA4IN RA5IN RB5IN RB4IN 1F 1F 20 VCC +5V TO +10V VOLTAGE DOUBLER +10V TO -10V VOLTAGE INVERTER ENTB 27 +5V 1 TA1OUT RA2IN RA1IN ENRA RA1OUT RA2OUT RA3OUT RA4OUT RA5OUT TA1IN TA2IN TA3IN
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 39 RB3IN 38 RB2IN 37 RB1IN 36 ENRB

+5V

1F

44 43 42 41 40

C1+ 23 C124 C2+ 25 C218 ENTA

V+ V-

22 26 1F

+5V TB1OUT 44

400k 15 TA1IN +5V 2 TA2OUT 400k 16 TA2IN +5V 3 TA3OUT 400k 17 TA3IN 8 RA1IN 5k 10 RA1OUT 7 RA2IN 5k TB3IN 28 RB1IN 37 5k RB1OUT 35 RB2IN 38 5k RB2OUT 34 RB3IN 39 5k RB3OUT 33 RB4IN 40 5k RB4OUT 32 RB5IN 41 5k RB5OUT 31 ENRB 36 GND 19 +5V TB3OUT 42 TB2IN 29 +5V TB2OUT 43 TB1IN 30

MAX249

35 RB1OUT 34 RB2OUT 33 RB3OUT 32 RB4OUT 31 RB5OUT 30 TB1IN 29 TB2IN

GND

C1+

C1-

C2+

C2-

V+

V-

PLCC

TB3IN

ENTA

ENTB

VCC

MAX249 FUNCTIONAL DESCRIPTION 10 RECEIVERS 5 A-SIDE RECEIVERS 5 B-SIDE RECEIVERS 6 TRANSMITTERS 3 A-SIDE TRANSMITTERS 3 B-SIDE TRANSMITTERS 4 CONTROL PINS ENABLE RECEIVER A-SIDE (ENRA) ENABLE RECEIVER B-SIDE (ENRB) ENABLE RECEIVER A-SIDE (ENTA) ENABLE RECEIVER B-SIDE (ENTB)

11 RA2OUT 6 RA3IN 5k 12 RA3OUT 5 RA4IN 5k 13 RA4OUT 4 RA5IN 5k 14 RA5OUT 9 ENRA

Figure 25. MAX249 Pin Configuration and Typical Operating Circuit 34 ______________________________________________________________________________________

+5V-Powered, Multichannel RS-232 Drivers/Receivers

___________________________________________Ordering Information (continued)
PART MAX222CPN MAX222CWN MAX222C/D MAX222EPN MAX222EWN MAX222EJN MAX222MJN MAX223CAI MAX223CWI MAX223C/D MAX223EAI MAX223EWI MAX225CWI MAX225EWI MAX230CPP MAX230CWP MAX230C/D MAX230EPP MAX230EWP MAX230EJP MAX230MJP MAX231CPD MAX231CWE MAX231CJD MAX231C/D MAX231EPD MAX231EWE MAX231EJD MAX231MJD MAX232CPE MAX232CSE MAX232CWE MAX232C/D MAX232EPE MAX232ESE MAX232EWE MAX232EJE MAX232MJE MAX232MLP MAX232ACPE MAX232ACSE MAX232ACWE TEMP RANGE 0C to +70C 0C to +70C 0C to +70C -40C to +85C -40C to +85C -40C to +85C -55C to +125C 0C to +70C 0C to +70C 0C to +70C -40C to +85C -40C to +85C 0C to +70C -40C to +85C 0C to +70C 0C to +70C 0C to +70C -40C to +85C -40C to +85C -40C to +85C -55C to +125C 0C to +70C 0C to +70C 0C to +70C 0C to +70C -40C to +85C -40C to +85C -40C to +85C -55C to +125C 0C to +70C 0C to +70C 0C to +70C 0C to +70C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -55C to +125C -55C to +125C 0C to +70C 0C to +70C 0C to +70C PIN-PACKAGE 18 Plastic DIP 18 Wide SO Dice* 18 Plastic DIP 18 Wide SO 18 CERDIP 18 CERDIP 28 SSOP 28 Wide SO Dice* 28 SSOP 28 Wide SO 28 Wide SO 28 Wide SO 20 Plastic DIP 20 Wide SO Dice* 20 Plastic DIP 20 Wide SO 20 CERDIP 20 CERDIP 14 Plastic DIP 16 Wide SO 14 CERDIP Dice* 14 Plastic DIP 16 Wide SO 14 CERDIP 14 CERDIP 16 Plastic DIP 16 Narrow SO 16 Wide SO Dice* 16 Plastic DIP 16 Narrow SO 16 Wide SO 16 CERDIP 16 CERDIP 20 LCC 16 Plastic DIP 16 Narrow SO 16 Wide SO PART MAX232AC/D MAX232AEPE MAX232AESE MAX232AEWE MAX232AEJE MAX232AMJE MAX232AMLP MAX233CPP MAX233EPP MAX233ACPP MAX233ACWP MAX233AEPP MAX233AEWP MAX234CPE MAX234CWE MAX234C/D MAX234EPE MAX234EWE MAX234EJE MAX234MJE MAX235CPG MAX235EPG MAX235EDG MAX235MDG MAX236CNG MAX236CWG MAX236C/D MAX236ENG MAX236EWG MAX236ERG MAX236MRG MAX237CNG MAX237CWG MAX237C/D MAX237ENG MAX237EWG MAX237ERG MAX237MRG MAX238CNG MAX238CWG MAX238C/D MAX238ENG TEMP RANGE 0C to +70C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -55C to +125C -55C to +125C 0C to +70C -40C to +85C 0C to +70C 0C to +70C -40C to +85C -40C to +85C 0C to +70C 0C to +70C 0C to +70C -40C to +85C -40C to +85C -40C to +85C -55C to +125C 0C to +70C -40C to +85C -40C to +85C -55C to +125C 0C to +70C 0C to +70C 0C to +70C -40C to +85C -40C to +85C -40C to +85C -55C to +125C 0C to +70C 0C to +70C 0C to +70C -40C to +85C -40C to +85C -40C to +85C -55C to +125C 0C to +70C 0C to +70C 0C to +70C -40C to +85C PIN-PACKAGE Dice* 16 Plastic DIP 16 Narrow SO 16 Wide SO 16 CERDIP 16 CERDIP 20 LCC 20 Plastic DIP 20 Plastic DIP 20 Plastic DIP 20 Wide SO 20 Plastic DIP 20 Wide SO 16 Plastic DIP 16 Wide SO Dice* 16 Plastic DIP 16 Wide SO 16 CERDIP 16 CERDIP 24 Wide Plastic DIP 24 Wide Plastic DIP 24 Ceramic SB 24 Ceramic SB 24 Narrow Plastic DIP 24 Wide SO Dice* 24 Narrow Plastic DIP 24 Wide SO 24 Narrow CERDIP 24 Narrow CERDIP 24 Narrow Plastic DIP 24 Wide SO Dice* 24 Narrow Plastic DIP 24 Wide SO 24 Narrow CERDIP 24 Narrow CERDIP 24 Narrow Plastic DIP 24 Wide SO Dice* 24 Narrow Plastic DIP 35

MAX220MAX249

* Contact factory for dice specifications. ______________________________________________________________________________________

+5V-Powered, Multichannel RS-232 Drivers/Receivers MAX220MAX249

___________________________________________Ordering Information (continued)
PART MAX238EWG MAX238ERG MAX238MRG MAX239CNG MAX239CWG MAX239C/D MAX239ENG MAX239EWG MAX239ERG MAX239MRG MAX240CMH MAX240C/D MAX241CAI MAX241CWI MAX241C/D MAX241EAI MAX241EWI MAX242CAP MAX242CPN MAX242CWN MAX242C/D MAX242EPN MAX242EWN MAX242EJN MAX242MJN TEMP RANGE -40C to +85C -40C to +85C -55C to +125C 0C to +70C 0C to +70C 0C to +70C -40C to +85C -40C to +85C -40C to +85C -55C to +125C 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C -40C to +85C -40C to +85C 0C to +70C 0C to +70C 0C to +70C 0C to +70C -40C to +85C -40C to +85C -40C to +85C -55C to +125C PIN-PACKAGE 24 Wide SO 24 Narrow CERDIP 24 Narrow CERDIP 24 Narrow Plastic DIP 24 Wide SO Dice* 24 Narrow Plastic DIP 24 Wide SO 24 Narrow CERDIP 24 Narrow CERDIP 44 Plastic FP Dice* 28 SSOP 28 Wide SO Dice* 28 SSOP 28 Wide SO 20 SSOP 18 Plastic DIP 18 Wide SO Dice* 18 Plastic DIP 18 Wide SO 18 CERDIP 18 CERDIP PART MAX243CPE MAX243CSE MAX243CWE MAX243C/D MAX243EPE MAX243ESE MAX243EWE MAX243EJE MAX243MJE MAX244CQH MAX244C/D MAX244EQH MAX245CPL MAX245C/D MAX245EPL MAX246CPL MAX246C/D MAX246EPL MAX247CPL MAX247C/D MAX247EPL MAX248CQH MAX248C/D MAX248EQH MAX249CQH MAX249EQH TEMP RANGE 0C to +70C 0C to +70C 0C to +70C 0C to +70C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -55C to +125C 0C to +70C 0C to +70C -40C to +85C 0C to +70C 0C to +70C -40C to +85C 0C to +70C 0C to +70C -40C to +85C 0C to +70C 0C to +70C -40C to +85C 0C to +70C 0C to +70C -40C to +85C 0C to +70C -40C to +85C PIN-PACKAGE 16 Plastic DIP 16 Narrow SO 16 Wide SO Dice* 16 Plastic DIP 16 Narrow SO 16 Wide SO 16 CERDIP 16 CERDIP 44 PLCC Dice* 44 PLCC 40 Plastic DIP Dice* 40 Plastic DIP 40 Plastic DIP Dice* 40 Plastic DIP 40 Plastic DIP Dice* 40 Plastic DIP 44 PLCC Dice* 44 PLCC 44 PLCC 44 PLCC

* Contact factory for dice specifications.

Package Information
For the latest package outline information, go to www.maxim-ic.com/packages.

Revision History
Pages changed at Rev 15: 25, 8, 9, 36

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

36 __________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600 2006 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.

PRODUCT SPECIFICATION

Single chip 433/868/915 MHz Transceiver nRF905

FEATURES
True single chip GFSK transceiver in a small 32-pin package (32L QFN 5x5mm) ShockBurst mode for low power operation Power supply range 1.9 to 3.6 V Multi channel operation ETSI/FCC Compatible Channel switching time <650s Extremely low cost Bill of Material (BOM) No external SAW filter Adjustable output power up to 10dBm Carrier detect for "listen before transmit" protocols Data Ready signal when a valid data packet is received or transmitted Address Match for detection of incoming packet Automatic retransmission of data packet Automatic CRC and preamble generation Low supply current (TX), typical 9mA @ -10dBm output power Low supply current (RX), typical 12.5mA

APPLICATIONS
Wireless data communication Alarm and security systems Home Automation Remote control Surveillance Automotive Telemetry Industrial sensors Keyless entry Toys

GENERAL DESCRIPTION
nRF905 is a single-chip radio transceiver for the 433/868/915 MHz ISM band. The transceiver consists of a fully integrated frequency synthesiser, receiver chain with demodulator, a power amplifier, a crystal oscillator and a modulator. The ShockBurstTM feature automatically handles preamble and CRC. Configuration is easily programmable by use of the SPI interface. Current consumption is very low, in transmit only 9mA at an output power of -10dBm, and in receive mode 12.5mA. Built in power down modes makes power saving easily realizable.

QUICK REFERENCE DATA

Parameter Minimum supply voltage Maximum transmit output power Data rate Supply current in transmit @ -10dBm output power Supply current in receive mode Temperature range Typical Sensitivity Supply current in power down mode Value 1.9 10 50 9 12.5 -40 to +85 -100 2.5 Unit V dBm kbps mA mA C dBm

Table 1 nRF905 quick reference data.

Main office: Nordic Semiconductor ASA Revision: 1.3 - Vestre Rosten 81, N-7075 Tiller, Norway Page 1 of 41 - Phone +4772898900 -Fax +4772898989 December 2005

PRODUCT SPECIFICATION
nRF905 Single Chip 433/868/915 MHz Radio Transceiver

ORDERING INFORMATION
Type Number nRF905 IC nRF905-EVKIT 433 nRF905-EVKIT 868/915 Description 32L QFN 5x5mm Evaluation kit 433MHz Evaluation kit 868/915MHz Version 1.0 1.0

Table 2 nRF905 ordering information.

BLOCK DIAGRAM
DVDD_1V2 (31) VDD (17) VDD (25) VSS (16) VSS (18) VSS (22) VSS (24) VSS (26) VSS (27) VSS (28) VSS (29) VSS (30) VDD (4) VSS (5) VSS (9)

MISO (10) MOSI (11) SCK (12) CSN (13)

XC1 (14)

IF BBF

TRX_CE (1) PWR_UP (2) TX_EN (32)

SPI interface TX - addr. TX - reg. RX - reg. Config-reg. ShockBurst Demod Dataslicer CRC code/ decode Address decode GFSK filter Manchester encoder/ decoder

Voltage regulators

Crystal oscillator

XC2 (15)

LNA

Frequency Synthesiser

VDD_PA (19)

CD (6) AM (7) DR (8)

ANT1 (20)

PA
uPCLK (3)

ANT2 (21)

IREF (23)

Figure 1 nRF905 with external components.

Main office: Nordic Semiconductor ASA Revision: 1.3

- Vestre Rosten 81, N-7075 Tiller, Norway Page 2 of 41

- Phone +4772898900

-Fax +4772898989 December 2005

PRODUCT SPECIFICATION
nRF905 Single Chip 433/868/915 MHz Radio Transceiver

TABLE OF CONTENTS
Pin Functions..................................................................................................................... 4 Pin Assignment ................................................................................................................. 5 Electrical Specifications.................................................................................................... 6 Current Consumption........................................................................................................ 8 Modes of Operation .......................................................................................................... 9 5.1 Active Modes ........................................................................................................... 9 5.2 Power Saving Modes................................................................................................ 9 5.3 nRF ShockBurst Mode ......................................................................................... 9 5.4 Typical ShockBurstTM TX ...................................................................................... 10 5.5 Typical ShockBurstTM RX...................................................................................... 12 5.6 Power Down Mode................................................................................................. 14 5.7 Standby Mode......................................................................................................... 14 6 Device Configuration...................................................................................................... 15 6.1 SPI Register Configuration .................................................................................... 15 6.2 SPI Instruction Set.................................................................................................. 16 6.3 SPI Timing ............................................................................................................. 17 6.4 RF Configuration Register Description............................................................... 19 6.5 Register Contents ................................................................................................... 20 7 Important Timing Data.................................................................................................... 21 7.1 Device Switching Times ........................................................................................ 21 7.2 ShockBurstTM TX timing........................................................................................ 21 7.3 ShockBurstTM RX timing........................................................................................ 22 7.4 Preamble................................................................................................................. 22 7.5 Time On Air ........................................................................................................... 23 8 Peripheral RF Information .............................................................................................. 24 8.1 Crystal Specification .............................................................................................. 24 8.2 External Clock Reference....................................................................................... 24 8.3 Microprocessor Output Clock ................................................................................ 24 8.4 Antenna Output ...................................................................................................... 25 8.5 Output Power Adjustment ...................................................................................... 25 8.6 Modulation ............................................................................................................. 25 8.7 Output Frequency................................................................................................... 26 8.8 PCB Layout and Decoupling Guidelines ............................................................... 27 9 nRF905 features .............................................................................................................. 28 9.1 Carrier Detect. ........................................................................................................ 28 9.2 Address Match........................................................................................................ 28 9.3 Data Ready ............................................................................................................. 28 9.4 Auto Retransmit ..................................................................................................... 29 9.5 RX Reduced Power Mode...................................................................................... 29 10 Package Outline .......................................................................................................... 30 10.1 Package marking .................................................................................................... 31 11 Application Examples................................................................................................. 32 11.1 Differential Connection to a Loop Antenna ........................................................... 32 11.2 PCB Layout Example; Differential Connection to a Loop Antenna ...................... 33 11.3 Single ended connection to 50 antenna ............................................................... 34 11.4 PCB Layout Example; Single Ended Connection to 50 Antenna ....................... 36 12 Absolute Maximum Ratings ....................................................................................... 37 13 Glossary of Terms....................................................................................................... 38 14 Definitions .................................................................................................................. 39 1 2 3 4 5

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- Vestre Rosten 81, N-7075 Tiller, Norway Page 3 of 41

- Phone +4772898900

-Fax +4772898989 December 2005

PRODUCT SPECIFICATION
nRF905 Single Chip 433/868/915 MHz Radio Transceiver

1
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

PIN FUNCTIONS
Name TRX_CE PWR_UP uPCLK VDD VSS CD AM DR VSS MISO MOSI SCK CSN XC1 XC2 VSS VDD VSS VDD_PA ANT1 ANT2 VSS IREF VSS VDD VSS VSS VSS VSS VSS DVDD_1V2 TX_EN Pin function Digital input Digital input Clock output Power Power Digital output Digital output Digital output Power SPI - interface SPI - interface SPI - Clock SPI - enable Analog Input Analog Output Power Power Power Power output RF RF Power Analog Input Power Power Power Power Power Power Power Power Digital input Description Enables chip for receive and transmit Power up chip Output clock, divided crystal oscillator full-swing clock Power supply (+3V DC) Ground (0V) Carrier Detect Address Match Receive and transmit Data Ready Ground (0V) SPI output SPI input SPI clock SPI enable, active low Crystal pin 1/ External clock reference pin Crystal pin 2 Ground (0V) Power supply (+3V DC) Ground Positive supply (1.8V) to nRF905 power amplifier Antenna interface 1 Antenna interface 2 Ground (0V) Reference current Ground (0V) Power supply (+3V DC) Ground (0V) Ground (0V) Ground (0V) Ground (0V) Ground (0V) Low voltage positive digital supply output for de-coupling TX_EN=1TX mode, TX_EN=0RX mode

Table 3 nRF905 pin function.

Main office: Nordic Semiconductor ASA Revision: 1.3

- Vestre Rosten 81, N-7075 Tiller, Norway Page 4 of 41

- Phone +4772898900

-Fax +4772898989 December 2005

PRODUCT SPECIFICATION
nRF905 Single Chip 433/868/915 MHz Radio Transceiver

PIN ASSIGNMENT
TX_EN DVDD_1V2 VSS VSS VSS VSS VSS VDD

32
TRX_CE

31

30

29

28

27

26

25 24
VSS

1 2 3 4 5 6 7 8 9
VSS

PWR_UP

nRF905
32L QFN 5x5

23 22 21 20 19 18 17

IREF

uPCLK

VSS

VDD

ANT2

VSS

ANT1

CD

VDD_PA

AM

VSS

DR

VDD

10
MISO

11
MOSI

12
SCK

13
CSN

14
XC1

15
XC2

16
VSS

Figure 2 nRF905 pin assignment (top view) for a 32L QFN 5x5 package.

Main office: Nordic Semiconductor ASA Revision: 1.3

- Vestre Rosten 81, N-7075 Tiller, Norway Page 5 of 41

- Phone +4772898900

-Fax +4772898989 December 2005

PRODUCT SPECIFICATION
nRF905 Single Chip 433/868/915 MHz Radio Transceiver

ELECTRICAL SPECIFICATIONS
Notes Min.
1.9 -40 0.7VDD VSS 1) VDD-0.3 VSS 2) 3) 4) 5) 6) 7) 8) 430 4 42 100 12.5 2.5 20 928 20 58

Conditions: VDD = +3V VSS = 0V, TEMP = -40C to +85C (typical +27C)

Symbol Parameter (condition) Operating conditions

VDD TEMP VIH VIL Ci IiL VOH VOL Istby_eclk Istby_dclk IPD ISPI fOP fXTAL f BR fCH433 fCH868/915 PRF10 PRF6 PRF-2 PRF-10 PBW_-16 PBW_-24 PBW_-32 PBW_-36 PRF1 PRF2 ITX10dBm ITX-10dBm IRX RXSENS RXMAX C/ICO C/I1ST C/I2ND C/I+1M C/I-1M C/I-2M C/I+5M C/I-5M C/I+10M C/I-10M C/IIM Supply voltage Operating temperature

Typ.

Max.
3.6 85 VDD 0.3VDD 5 10 VDD 0.3

Units
V C V V pF nA V V A A A A MHz MHz kHz kbps kHz kHz dBm dBm dBm dBm kHz kHz kHz kHz dBc dBc mA mA mA dBm dBm dB dB dB dB dB dB dB dB dB dB dB

Digital input/output
HIGH level input voltage LOW level input voltage Pin capacitance Pin leakage current HIGH level output voltage (IOH=-0.5mA) LOW level output voltage (IOL=0.5mA)

General electrical specification

Supply current in standby, uCLK enabled Supply current in standby, uCLK disabled Supply current in power down mode Supply current in SPI programming

General RF conditions
Operating frequency Crystal frequency Frequency deviation Data rate Channel spacing for 433MHz band Channel spacing for 868/915MHz band 50 50 100 200 10 6 -2 -10 173 222 238 313 -27 -54 30 9 12.5 -100 0 11) 11) 11) 11) 11) 11) 11) 11) 11) 11) 11) 13 -7 -16 -40 -50 -63 -70 -65 -69 -67 -36

Transmitter operation
Output power 10dBm setting Output power 6dBm setting Output power 2dBm setting Output power -10dBm setting -16dBc bandwidth for modulated carrier -24dBc bandwidth for modulated carrier -32dBc bandwidth for modulated carrier -36dBc bandwidth for modulated carrier 1st adjacent channel transmit power 2nd adjacent channel transmit power Supply current @ 10dBm output power Supply current @ -10dBm output power 9) 9) 9) 9) 8) 8) 8) 8) 10) 10) 7 3 -6 -14 11 9 2 -6

Receiver operation
Supply current in receive mode Sensitivity at 0.1%BER Maximum received signal C/I Co-channel 1st adjacent channel selectivity C/I 200kHz 2nd adjacent channel selectivity C/I 400kHz Blocking at +1MHz Blocking at -1MHz Blocking at -2MHz Blocking at +5MHz Blocking at -5MHz Blocking at +10MHz Blocking at -10MHz Image rejection

Table 4 nRF905 electrical specifications.

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PRODUCT SPECIFICATION
nRF905 Single Chip 433/868/915 MHz Radio Transceiver
1) Max value determined by design and characterization testing. 2) Output frequency is 4MHz load of external clock pin is 5pF, Crystal is 4MHz. 3) Crystal is 4MHz. 4) Pin voltages are VSS or VDD. 5) Chip in power down, SPI_SCK frequency is 1MHz. 6) Operates in the 433, 868 and 915 MHz ISM band. 7) The crystal frequency may be chosen from 5 different values (4, 8, 12, 16, and 20MHz) 8) Data is Manchester-encoded before GFSK modulation. 9) Optimum load impedance, please see peripheral RF information. 10) Channel width and channel spacing is 200kHz. 11) Channel Level +3dB over sensitivity, interfering signal a standard CW, image lies 2MHz above wanted.

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CURRENT CONSUMPTION
TYPICAL OUTPUT CURRENT CLOCK FREQ. [MHZ] Power Down 16 OFF 2.5 uA Standby 4 OFF 12 uA Standby 8 OFF 25 uA Standby 12 OFF 27 uA Standby 16 OFF 32 uA Standby 20 OFF 46 uA Standby 4 0.5 110 uA Standby 8 0.5 125 uA Standby 12 0.5 130 uA Standby 16 0.5 135 uA Standby 20 0.5 150 uA Standby 4 1 130 uA Standby 8 1 145 uA Standby 12 1 150 uA Standby 16 1 155 uA Standby 20 1 170 uA Standby 4 2 170 uA Standby 8 2 185 uA Standby 12 2 190 uA Standby 16 2 195 uA Standby 20 2 210 uA Standby 4 4 260 uA Standby 8 4 275 uA Standby 12 4 280 uA Standby 16 4 285 uA Standby 20 4 300 uA Rx @ 433 16 OFF 12.2 mA Rx @ 868/915 16 OFF 12.8 mA Reduced Rx 16 OFF 10.5 mA Tx @ 10dBm 16 OFF 30 mA Tx @ 6dBm 16 OFF 20 mA Tx @ -2dBm 16 OFF 14 mA Tx @ -10dBm 16 OFF 9 mA Conditions: VDD = 3.0V, VSS = 0V, TA = 27C, Load capacitance of external clock = 13pF, Crystal load capacitance = 12pF MODE CRYSTAL FREQ. [MHZ]

Table 5 nRF905 current consumption.

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MODES OF OPERATION

The nRF905 has two active (RX/TX) modes and two power-saving modes 5.1 Active Modes ShockBurst RX ShockBurst TX Power Saving Modes Power down and SPI - programming Standby and SPI - programming

5.2

The nRF905 mode is decided by the settings of TRX_CE, TX_EN and PWR_UP.
PWR_UP 0 1 1 1 1 TRX_CE X 0 X 1 1 TX_EN X X 0 0 1 Operating Mode Power down and SPI programming Standby and SPI programming Read data from RX register Radio Enabled - ShockBurstTM RX Radio Enabled - ShockBurstTM TX

Table 6 nRF905 operational modes.

5.3

nRF ShockBurst Mode

The nRF905 uses the Nordic Semiconductor ASA ShockBurst feature. ShockBurstTM makes it possible to use the high data rate offered by the nRF905 without the need of a costly, high-speed micro controller (MCU) for data processing/clock recovery. By placing all high speed signal processing related to RF protocol on-chip, the nRF905 offers the application micro controller a simple SPI interface, the data rate is decided by the interface-speed the micro controller itself sets up. By allowing the digital part of the application to run at low speed, while maximizing the data rate on the RF link, the nRF905 ShockBurst mode reduces the average current consumption in applications. In ShockBurstTM RX, Address Match (AM) and Data Ready (DR) notifies the MCU when a valid address and payload is received respectively. In ShockBurstTM TX, the nRF905 automatically generates preamble and CRC. Data Ready (DR) notifies the MCU that the transmission is completed. All together, this means reduced memory demand in the MCU resulting in a low cost MCU, as well as reduced software development time.

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5.4

Typical ShockBurstTM TX 1. When the application MCU has data for a remote node, the address of the receiving node (TX-address) and payload data (TX-payload) are clocked into nRF905 via the SPI interface. The application protocol or MCU sets the speed of the interface. 2. MCU sets TRX_CE and TX_EN high, this activates a nRF905 ShockBurst transmission. 3. nRF905 ShockBurst: Radio is automatically powered up. Data packet is completed (preamble added, CRC calculated). Data packet is transmitted (100kbps, GFSK, Manchester-encoded). Data Ready is set high when transmission is completed. 4. If AUTO_RETRAN is set high, the nRF905 continuously retransmits the packet until TRX_CE is set low. 5. When TRX_CE is set low, the nRF905 finishes transmitting the outgoing packet and then sets itself into standby mode.

If TX_EN is set low while TRX_CE is kept high, the nRF905 finishes transmitting the outgoing packet and then enter RX-mode in the channel already programmed in the RF-CONFIG register. The ShockBurstTM mode ensures that a transmitted packet that has started always finishes regardless of what TRX_EN and TX_EN is set to during transmission. The new mode is activated when the transmission is completed. Please see subsequent chapters for detailed timing For test purposes such as antenna tuning and measuring output power it is possible to set the transmitter so that a constant carrier is produced. To do this TRX_CE must be maintained high instead of being pulsed. In addition Auto Retransmit should be switched off. After the burst of data has been sent then the device will continue to send the unmodulated carrier.

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Radio in Standby TX_EN = HI PWR_UP = HI TRX_CE = LO

Data Package
SPI - programming uController loading ADDR and PAYLOAD data (Configuration register if changes since last TX/RX) ADDR PAYLOAD

TRX_CE = HI ?

NO

YES Transmitter is powered up

nRF ShockBurst TX Generate CRC and preamble Sending package DR is set high when completed DR is set low after preamble Preamble ADDR PAYLOAD CRC

NO AUTO_ RETRAN = HI ? YES Bit in configuration register

NO

TRX_CE = HI ?

YES

Figure 3 Flowchart ShockBurstTM transmit of nRF905. NB: DR is set low under the following conditions after it has been set high: If TX_EN is set low If PWR_UP is set low

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5.5

Typical ShockBurstTM RX 1. ShockBurstTM RX is selected by setting TRX_CE high and TX_EN low. 2. After 650s nRF905 is monitoring the air for incoming communication. 3. When the nRF905 senses a carrier at the receiving frequency, Carrier Detect (CD) pin is set high. 4. When a valid address is received, Address Match (AM) pin is set high. 5. When a valid packet has been received (correct CRC found), nRF905 removes the preamble, address and CRC bits, and the Data Ready (DR) pin is set high. 6. MCU sets the TRX_CE low to enter standby mode (low current mode). 7. MCU can clock out the payload data at a suitable rate via the SPI interface. 8. When all payload data is retrieved, nRF905 sets Data Ready (DR) and Address Match (AM) low again. 9. The chip is now ready for entering ShockBurstTM RX, ShockBurstTM TX or power down mode.

If TX_EN is set high while TRX_CE is kept high, the nRF905 would enter ShockBurstTMTX and start a transmission according to the present contents in the SPIregisters. If TRX_CE or TX_EN is changed during an incoming packet, the nRF905 changes mode immediately and the packet is lost. However, if the MCU is sensing the Address Match (AM) pin, it knows when the chip is receiving an incoming packet and can therefore decide whether to wait for the Data Ready (DR) signal or enter a different mode. To avoid spurious address matches it is recommended that the address length be 24 bits or higher in length. Small addresses such as 8 or 16 bits can often lead to statistical failures due to the address being repeated as part of the data packet. This can be avoided by using a longer address. Each byte within the address should be unique. Repeating bytes within the address reduces the effectiveness of the address and increases its susceptibility to noise hence increasing the packet error rate. The address should also have several level shifts (i.e. 10101100) to reduce the statistical effect of noise and hence reduce the packet error rate.

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Radio in Standby TX_EN = LO PWR_UP = HI

TRX_CE = HI ? YES Receiver is powered up

NO

Receiver Sensing for incomming data CD is set high if carrier

Data Package
NO

Correct ADDR? YES AM is set high

Preamble

ADDR

PAYLOAD

CRC

Receiving data

AM is set low

NO

Correct CRC? YES DR high is set high DR and AM are set low DR and AM are set low

MCU clocks out payload via the SPI interface

MCU clocks out payload via the SPI interface

PAYLOAD

TRX_CE = HI ?

YES

RX Remains On

Radio enters STBY

NO

Figure 4 Flowchart ShockBurstTM receive of nRF905.

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5.6 Power Down Mode In power down the nRF905 is disabled with minimal current consumption, typically less than 2.5A. When entering this mode the device is not active which will minimize average current consumption and maximizing battery lifetime. The configuration word content is maintained during power down.

5.7 Standby Mode Standby mode is used to minimize average current consumption while maintaining short start up times to ShockBurstTM RX and ShockBurstTM TX. In this mode part of the crystal oscillator is active. Current consumption is dependent on crystal frequency, Ex: IDD= 12A @4MHz and IDD =46A @20MHz. If the uP-clock (pin 3) of nRF905 is enabled, current consumption increases and is dependent on the load capacitance and frequency. The configuration word content is maintained during standby.

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DEVICE CONFIGURATION

All configuration of the nRF905 is via the SPI interface. The interface consists of five registers; a SPI instruction set is used to decide which operation shall be performed. The SPI interface can be activated in any mode however Nordic Semiconductor ASA recommends the chip be in standby or power down mode. 6.1 SPI Register Configuration The SPI interface consists of five internal registers. A register read-back mode is implemented to allow verification of the register contents.
MISO MOSI SCK CSN EN I/O-reg DTA CLK STATUS-REGISTER

EN DTA CLK RF - CONFIGURATION REGISTER

EN DTA CLK TX-ADDRESS

EN DTA CLK TX-PAYLOAD

EN DTA CLK RX-PAYLOAD

Figure 5 SPI interface and the five internal registers. Status Register Register contains status of Data Ready (DR) and Address Match (AM). RF Configuration Register Register contains transceiver setup information such as frequency and output power ext. TX Address Register contains address of target device. How many bytes used is set in the configuration register. TX Payload Register containing the payload information to be sent in a ShockBurst How many bytes used is set in the configuration register. RX Payload Register containing the payload information derived from a received valid ShockBurst TM packet. How many bytes used is set in the configuration register. Valid data in the RX-Payload register is indicated with a high Date Ready (DR) signal.
TM

packet.

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6.2 SPI Instruction Set The available commands to be used on the SPI interface is shown below. Whenever CSN is set low the interface expects an instruction. Every new instruction must be started by a high to low transition on CSN.
Instruction set for the nRF905 SPI Serial Interface Instruction Operation Format W_CONFIG 0000 AAAA Write Configuration-register. AAAA indicates which byte (WC) the write operation is to be started from. Number of bytes depends on start address AAAA. R_CONFIG 0001 AAAA Read Configuration-register. AAAA indicates which byte (RC) the read operation is to be started from. Number of bytes depends on start address AAAA. W_TX_PAYLOAD 0010 0000 Write TX-payload: 1 32 bytes. A write operation will (WTP) always start at byte 0. R_TX_PAYLOAD 0010 0001 Read TX-payload: 1 32 bytes. A read operation will (RTP) always start at byte 0. W_TX_ADDRESS 0010 0010 Write TX-address: 1 4 bytes. A write operation will (WTA) always start at byte 0. R_TX_ADDRESS 0010 0011 Read TX-address: 1 4 bytes. A read operation will (RTA) always start at byte 0 R_RX_PAYLOAD 0010 0100 Read RX-payload: 1 32 bytes. A read operation will (RRP) always start at byte 0. CHANNEL_CONFIG 1000 pphc Special command for fast setting of CH_NO, (CC) cccc cccc HFREQ_PLL and PA_PWR in the CONFIGURATION REGISTER. CH_NO= ccccccccc, HFREQ_PLL = h PA_PWR = pp STATUS REGISTER N.A. The content of the status-register (S[7:0]) will always be read to MISO after a high to low transition on CSN as shown in Figure 6 and 7. Instruction Name

Table 7 Instruction set for the nRF905 SPI interface. A read or a write operation may operate on a single byte or on a set of succeeding bytes from a given start address defined by the instruction. When accessing succeeding bytes one will read or write MSB of the byte with the smallest byte number first.

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6.3 SPI Timing The interface supports SPI mode 0. SPI operation and timing is given in Figure 6 to Figure 8 and in Table 8. The device must be in one of the power saving modes for the configuration registers to be read or written to.
CSN SCK MOSI MISO
C7 C6 C5 C4 C3 C2 C1 C0

S7

S6

S5

S4

S3

S2

S1

S0

D7

D6

D5

D4

D3

D2

D1

D0

D1 5

D1 4

D1 3

D1 2

D1 1

D1 0

D9

D8

Figure 6 SPI read operation.

CSN SCK MOSI MISO

C7 C6 C5 C4 C3 C2 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0 D1 5 D1 4 D1 3 D1 2 D1 1 D1 0 D9 D8

S7

S6

S5

S4

S3

S2

S1

S0

Figure 7 SPI write operation.

Tcwh
CSN

Tcc
SCK

Tch

Tcl

Tcch

Tdh Tdc
MOSI
C7 C6 C0

Tcsd
MISO
S7

Tcd
S0

Tcdz

Figure 8 SPI NOP timing diagram.

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PARAMETER Data to SCK Setup SCK to Data Hold CSN to Data Valid SCK to Data Valid SCK Low Time SCK High Time SCK Frequency SCK Rise and Fall CSN to SCK Setup SCK to CSN Hold CSN Inactive time CSN to Output High Z

SYMBOL Tdc Tdh Tcsd Tcd Tcl Tch Tsck Tr,Tf Tcc Tcch Tcwh Tcdz

MIN 5 5

MAX

45 45 40 40 DC 5 5 500 45

10 100

UNITS ns ns ns ns ns ns MHz ns ns ns ns ns

Table 8 SPI timing parameters (Cload = 10pF).

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6.4

RF Configuration Register Description

Bitwidth 9 1 Description Sets center freq. together with HFREQ_PLL (default = 001101100b = 108d). fRF = ( 422.4 + CH_NOd /10)*(1+HFREQ_PLLd) MHz Sets PLL in 433 or 868/915 MHz mode (default = 0). '0' Chip operating in 433MHz band '1' Chip operating in 868 or 915 MHz band Output power (default = 00). '00' -10dBm '01' -2dBm '10' +6dBm '11' +10dBm Reduces current in RX mode by 1.6mA. Sensitivity is reduced (default = 0). '0' Normal operation '1' Reduced power Retransmit contents in TX register if TRX_CE and TXEN are high (default = 0). '0' No retransmission '1' Retransmission of data packet RX-address width (default = 100). '001' 1 byte RX address field width '100' 4 byte RX address field width TX-address width (default = 100). '001' 1 byte TX address field width '100' 4 byte TX address field width RX-payload width (default = 100000). '000001' 1 byte RX payload field width '000010' 2 byte RX payload field width . '100000' 32 byte RX payload field width TX-payload width (default = 100000). '000001' 1 byte TX payload field width '000010' 2 byte TX payload field width . '100000' 32 byte TX payload field width RX address identity. Used bytes depend on RX_AFW (default = E7E7E7E7h). Output clock frequency (default = 11). '00' 4MHz '01' 2MHz '10' 1MHz '11' 500kHz Output clock enable (default = 1). '0' No external clock signal available '1' External clock signal enabled Crystal oscillator frequency. Must be set according to external crystal resonantfrequency (default = 100). '000' 4MHz '001' 8MHz '010' 12MHz '011' 16MHz '100' 20MHz CRC check enable (default = 1). '0' Disable '1' Enable CRC mode (default = 1). '0' 8 CRC check bit '1' 16 CRC check bit

Parameter CH_NO HFREQ_ PLL PA_PWR

RX_RED_ PWR AUTO_ RETRAN RX_AFW

TX_AFW

RX_PW

TX_PW

RX_ ADDRESS UP_CLK_ FREQ

32 2

UP_CLK_ EN XOF

CRC_EN

CRC_ MODE

Table 9 Configuration-register description.

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6.5
Byte # 0 1 2 3 4 5 6 7 8 9

Register Contents
RF-CONFIG_REGISTER (R/W) Content bit[7:0], MSB = bit[7] CH_NO[7:0] bit[7:6] not used, AUTO_RETRAN, RX_RED_PWR, PA_PWR[1:0], HFREQ_PLL, CH_NO[8] bit[7] not used, TX_AFW[2:0] , bit[3] not used, RX_AFW[2:0] bit[7:6] not used, RX_PW[5:0] bit[7:6] not used, TX_PW[5:0] RX_ADDRESS (device identity) byte 0 RX_ADDRESS (device identity) byte 1 RX_ADDRESS (device identity) byte 2 RX_ADDRESS (device identity) byte 3 CRC_MODE,CRC_EN, XOF[2:0], UP_CLK_EN, UP_CLK_FREQ[1:0] TX_PAYLOAD (R/W) Content bit[7:0], MSB = bit[7] TX_PAYLOAD[7:0] TX_PAYLOAD[15:8] TX_PAYLOAD[247:240] TX_PAYLOAD[255:248] TX_ADDRESS (R/W) Content bit[7:0], MSB = bit[7] TX_ADDRESS[7:0] TX_ADDRESS[15:8] TX_ADDRESS[23:16] TX_ADDRESS[31:24] RX_PAYLOAD (R) Content bit[7:0], MSB = bit[7] RX_PAYLOAD[7:0] RX_PAYLOAD[15:8] RX_PAYLOAD[247:240] RX_PAYLOAD[255:248] STATUS_REGISTER (R) Content bit[7:0], MSB = bit[7]
AM, bit [6] not used, DR, bit [0:4] not used

Init value
0110_1100 0000_0000 0100_0100 0010_0000 0010_0000 E7 E7 E7 E7 1110_0111

Byte # 0 1 30 31

Init value
X X X X X X

Byte # 0 1 2 3

Init value
E7 E7 E7 E7

Byte # 0 1

Init value
X X X X X X

30 31

Byte # 0

Init value
X

Table 10 RF register contents. The length of all registers is fixed. However, the bytes in TX_PAYLOAD, RX_PAYLOAD, TX_ADDRESS and RX_ADDRESS used in ShockBurst TM RX/TX are set in the configuration register. Register content is not lost when the device enters one of the power saving modes.
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IMPORTANT TIMING DATA

The following timing must be obeyed during nRF905 operation. 7.1 Device Switching Times
nRF905 timing PWR_DWN ST_BY mode STBY TX ShockBurst STBY RX ShockBurst RX ShockBurst TX ShockBurst TX ShockBurst RX ShockBurst Notes to table: 1) Max. 3 ms 650 s 650 s 550 1s 550 1s

RX to TX or TX to RX switching is available without re-programming of the RF configuration register. The same frequency channel is maintained.

Table 11 Switching times for nRF905. ShockBurstTM TX timing

7.2
M OSI

CSN

PW R_U P

TX_EN

TRX_CE

TX DATA

T IM E P r o g r a m m in g o f C o n f i g u r a ti o n R e g is t e r a n d T X D a ta R e g is te r T0 T1 T2 T r a n s m it t e d D a t a 1 0 0 k b p s M a n c h e s te r E n c o d e d T3

T0 T1 T2 T3

= = = =

R a d io E n a b l e d T 0 + 1 0 u S M in im u m T R X _ C E p u ls e T 0 + 6 5 0 u S . S t a r t o f T X D a t a t r a n s m is s io n E n d o f D a ta P a c k e t, e n te r S ta n d b y m o d e

Figure 9 Timing diagram for standby to transmit.

After a data packet has finished transmitting the device will automatically enter Standby mode and wait for the next pulse of TRX_CE. If the Auto Re-Transmit function is enabled the data packet will continue re-sending the same data packet until TRX_CE is set low.

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7.3
PW R _U P

ShockBurstTM RX timing

TX_EN

TRX_CE

RX DATA

CD

AM

DR

T IM E

650uS 6 5 0 u S to e n te r R X m o d e fro m T R X _ C E b e in g s e t h ig h .

T0 T T T T 0 1 2 3 = = = =

T1

T2

T3

R e c e iv e r E n a b l e d - L is t e n in g f o r D a t a C a r r ie r D e t e c t f in d s a c a r r ie r A M - C o rre c t A d d re s s F o u n d D R - D a t a p a c k e t w it h c o r r e c t A d d r e s s / C R C

Figure 10 Timing diagram for standby to receiving. After the Data Ready (DR) has been set high a valid data packet is available in the RX data register. This may be clocked out in RX mode or standby mode. After the data has been clocked out via the SPI interface the Data Ready (DR) and Address Match (AM) pins are reset to low. The RX register is reset if the PWR_UP pin is taken low or if the device is switched into TX mode i.e. TXEN is taken high. This will also results in the Data Ready(DR) and Address Match (AM) pins being reset to low.

7.4 Preamble In each data-packet transmitted by the nRF905 a preamble is added automatically. The preamble is a predefined bit-sequence used to adjust the receiver for optimal performance. A ten-bit sequence is used as preamble in nRF905. The length of the preamble, tpreamble, is then 200s.

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7.5 Time On Air The time-on-air is the sum of the radio start-up time and the data-packet length. The length of the preamble, address field, payload and CRC-checksum give the datapacket length while the radio start-up time is given in Table 11. While preamble length and start-up time are fixed the user sets the other parameters in the RFconfiguration register. The below equation shows how to calculate TOA
TOA = t startup + t preamble + N address + N payload + N CRC BR

tstartup and tpreamble are RF-start-up time and preamble time respectively. Naddress, Npayload and NCRC are numbers of bits in the address, payload and CRC-checksum while BR is the bitrate, which is equal to 50kbps.

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PERIPHERAL RF INFORMATION

8.1 Crystal Specification Tolerance includes initially accuracy and tolerance over temperature and aging.
Frequency 4MHz 8MHz 12MHz 16MHz 20MHz CL 8pF 16pF 8pF 16pF 8pF 16pF 8pF 16pF 8pF 16pF ESR 150 100 100 100 100 C0max 7.0pF 7.0pF 7.0pF 7.0pF 7.0pF Tolerance @ 868/915 MHz 30ppm 30ppm 30ppm 30ppm 30ppm Tolerance @ 433 MHz 60ppm 60ppm 60ppm 60ppm 60ppm

Table 12 Crystal specification of nRF905. To achieve a crystal oscillator solution with low power consumption and fast start-up time, it is recommended to specify the crystal with a low value of crystal load capacitance. Specifying a lower value of crystal parallel equivalent capacitance, Co=1.5pF is also good, but this can increase the price of the crystal itself. Typically Co=1.5pF at a crystal specified for Co_max=7.0pF. The crystal load capacitance, CL, is given by:
CL = C1 'C 2 ' , C1 '+C 2 ' where C1 ' = C1 + C PCB1 + C I 1 and C 2 ' = C 2 + C PCB 2 + C I 2

C1 and C2 are 0603 SMD capacitors as shown in the application schematics. CPCB1 and CPCB2 are the layout parasitic on the circuit board. CI1 and CI2 are the capacitance seen into the XC1 and XC2 pin respectively; the value is typical 1pF. 8.2 External Clock Reference An external reference clock, such as a MCU clock, may be used instead of a crystal. The clock signal should be applied directly to the XC1 pin, the XC2 pin can be left high impedance. When operating with an external clock instead of a crystal the clock must be applied in standby mode to achieve low current consumption. If the device is set into standby mode with no external clock or crystal then the current consumption will increase up to a maximum of 1mA. 8.3 Microprocessor Output Clock By default a microprocessor clock output is provided. Providing an output clock will increase the current consumption in standby mode. The current consumption in standby will depend on frequency and load of external crystal, frequency of output clock and capacitive load of the provided output clock. Typical current consumption values are found in Table 5.

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PRODUCT SPECIFICATION
nRF905 Single Chip 433/868/915 MHz Radio Transceiver

8.4 Antenna Output The ANT1 & ANT2 output pins provide a balanced RF output to the antenna. The pins must have a DC path to VDD_PA, either via a RF choke or via the center point in a dipole antenna. The load impedance seen between the ANT1/ANT2 outputs should be in the range 200-700. The optimum differential load impedance at the antenna ports is given as: 900MHz 430MHz 225+j210 300+j100

A low load impedance (for instance 50) can be obtained by fitting a simple matching network or a RF transformer (balun). Further information regarding balun structures and matching networks may be found in the Application Examples chapter. 8.5 Output Power Adjustment The power amplifier in nRF905 can be programmed to four different output power settings by the configuration register. By reducing output power, the total TX current is reduced.
Power setting RF output power DC current consumption

00 -10 dBm 9.0 mA 01 -2 dBm 14.0 mA 10 6 dBm 20.0 mA 11 10 dBm 30.0 mA Conditions: VDD = 3.0V, VSS = 0V, TA = 27C, Load impedance = 400 .

Table 13 RF output power setting for the nRF905.

8.6 Modulation The modulation of nRF905 is Gaussian Frequency Shift Keying (GFSK) with a datarate of 100kbps. Deviation is 50kHz. GFSK modulation results in a more bandwidth effective transmission-link compared with ordinary FSK modulation. The data is internally Manchester encoded (TX) and Manchester decoded (RX). That is, the effective symbol-rate of the link is 50kbps. By using internally Manchester encoding, no scrambling in the microcontroller is needed.

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PRODUCT SPECIFICATION
nRF905 Single Chip 433/868/915 MHz Radio Transceiver

8.7 Output Frequency The operating RF-frequency of nRF905 is set in the configuration register by CH_NO and HFREQ_PLL. The operating frequency is given by: f OP = (422.4 + (CH _ NO / 10)) (1 + HFREQ _ PLL) MHz When HFREQ_PLL is 0 the frequency resolution is 100kHz and when it is 1 the resolution is 200kHz. The application operating frequency has to be chosen to apply with the Short Range Devise regulation in the area of operation.
Operating frequency 430.0 MHz 433.1 MHz 433.2 MHz 434.7 MHz HFREQ_PLL [0] [0] [0] [0] CH_NO [001001100] [001101011] [001101100] [001111011]

862.0 MHz 868.2 MHz 868.4 MHz 869.8 MHz 902.2 MHz 902.4 MHz 927.8 MHz

[1] [1] [1] [1] [1] [1] [1]

[001010110] [001110101] [001110110] [001111101] [100011111] [100100000] [110011111]

Table 14 Examples of real operating frequencies.

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PRODUCT SPECIFICATION
nRF905 Single Chip 433/868/915 MHz Radio Transceiver

8.8 PCB Layout and Decoupling Guidelines nRF905 is an extremely robust RF device due to internal voltage regulators and requires the minimum of RF layout protocols. However the following design rules should still be incorporated into the layout design. A PCB with a minimum of two layers including a ground plane is recommended for optimum performance. The nRF905 DC supply voltage should be decoupled as close as possible to the VDD pins with high performance RF capacitors. It is preferable to mount a large surface mount capacitor (e.g. 4.7F tantalum) in parallel with the smaller value capacitors. The nRF905 supply voltage should be filtered and routed separately from the supply voltages of any digital circuitry. Long power supply lines on the PCB should be avoided. All device grounds, VDD connections and VDD bypass capacitors must be connected as close as possible to the nRF905 IC. For a PCB with a topside RF ground plane, the VSS pins should be connected directly to the ground plane. For a PCB with a bottom ground plane, the best technique is to place via holes as close as possible to the VSS pins. A minimum of one via hole should be used for each VSS pin. Full swing digital data or control signals should not be routed close to the crystal or the power supply lines. A fully qualified RF-layout for the nRF905 and its surrounding components, including antennas and matching networks, can be downloaded from www.nordicsemi.no.

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nRF905 FEATURES

9.1 Carrier Detect. When the nRF905 is in ShockBurst TM RX, the Carrier Detect (CD) pin is set high if a RF carrier is present at the channel the device is programmed to. This feature is very effective to avoid collision of packets from different transmitters operating at the same frequency. Whenever a device is ready to transmit it could first be set into receive mode and sense whether or not the wanted channel is available for outgoing data. This forms a very simple listen before transmit protocol. Operating Carrier Detect (CD) with Reduced RX Power mode is an extremely power efficient RF system. Typical Carrier Detect level (CD) is typically 5dB lower than sensitivity, i.e. if sensitivity is 100dBm then the Carrier Detect function will sense a carrier wave as low as 105dBm. Below 105dBm the Carrier Detect signal will be low, i.e. 0V. Above 95dBm the Carrier Detect signal will be high, i.e. Vdd. Between approximately -95 to -105 the Carrier Detect Signal will toggle. 9.2 Address Match When the nRF905 is in ShockBurst TM RX mode, the Address Match (AM) pin is set high as soon as an incoming packet with an address that is identical with the devices own identity is received. With the Address Match pin the controller is alerted that the nRF905 is receiving data actually before the Data Ready (DR) signal is set high. If the Data Ready (DR) pin is not set high i.e. the CRC is incorrect then the Address Match (AM) pin is reset to low at the end of the received data packet. This function can be very useful for an MCU. If Address Match (AM) is high then the MCU can make a decision to wait and see if Data Ready (DR) will be set high indicating a valid data packet has been received or ignore that a possible packet is being received and switch modes. 9.3 Data Ready The Data Ready (DR) signal makes it possible to largely reduce the complexity of the MCU software program. In ShockBurst TM TX, the Data Ready (DR) signal is set high when a complete packet is transmitted, telling the MCU that the nRF905 is ready for new actions. It is reset to low at the start of a new packet transmission or when switched to a different mode i.e. receive mode or standby mode. In ShockBurst TM TX Auto Retransmit the Data Ready (DR) signal is set high at the beginning of the pre-amble and is set low at the end of the preamble. The Data Ready (DR) signal therefore pulses at the beginning of each transmitted data packet. In ShockBurst TM RX, the signal is set high when nRF905 has received a valid packet, i.e. a valid address, packet length and correct CRC. The MCU can then retrieve the payload via the SPI interface. The Data Ready (DR) pin is reset to low once the data has been clocked out of the data buffer or the device is switched to transmit mode.

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PRODUCT SPECIFICATION
nRF905 Single Chip 433/868/915 MHz Radio Transceiver

9.4 Auto Retransmit One way to increase system reliability in a noisy environment or in a system without collision control is to transmit a packet several times. This is easily accomplished with the Auto Retransmit feature in nRF905. By setting the AUTO_RETRAN bit to 1 in the configuration register, the circuit keeps sending the same data packet as long as TRX_CE and TX_EN are high. As soon as TRX_CE is set low the device will finish sending the packet it is currently transmitting and then return to standby mode. 9.5 RX Reduced Power Mode To maximize battery lifetime in application where the nRF905 high sensitivity is not necessary; nRF905 offers a built in reduced power mode. In this mode, the receive current consumption reduces from 12.5mA to only 10.5mA. The sensitivity is reduced to typical 85dBm, 10dB. Some degradation of the nRF905 blocking performance should be expected in this mode. The reduced power mode is an excellent option when using Carrier Detect to sense if the wanted channel is available for outgoing data.

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PRODUCT SPECIFICATION
nRF905 Single Chip 433/868/915 MHz Radio Transceiver

10 PACKAGE OUTLINE
nRF905 uses the QFN 32L 5x5 green package with a mat tin finish. Dimensions are in mm. Recommended soldering reflow profile can be found in application note nAN400-08, QFN soldering reflow guidelines, www.nordicsemi.no.

+
Package Type QFN32 (5x5 mm) A 0.8 A1 0.0 A2 0.65 b 0.18 0.23 0.3 D E e J 3.2 3.3 3.4 K 3.2 3.3 3.4 L 0.3 0.4 0.5

Min typ. Max

5 BSC

5 BSC

0.5 BSC

0.9

0.05

0.69

Figure 11 nRF905 package outline.

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PRODUCT SPECIFICATION
nRF905 Single Chip 433/868/915 MHz Radio Transceiver

10.1 Package marking

B X n R F D D D D D D Y Y W W L L
Figure 12 nRF905 package marking layout Abbreviations: DDDDDD Product number, e.g. 905 B Build Code, i.e. unique code for silicon revision, production site, package type and test platform X "X" grade, i.e. Engineering Samples (optional) YY 2 digit Year number WW 2 digit Week number LL 2 letter wafer lot number code

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PRODUCT SPECIFICATION
nRF905 Single Chip 433/868/915 MHz Radio Transceiver

11 APPLICATION EXAMPLES
11.1 Differential Connection to a Loop Antenna
aaaaaaaa VDD C7 10nF 0603 C5 33pF 0603 C6 4.7nF 0603

32 31 30 29 28 27 26 25

TXEN DVDD_1V2 VSS VSS VSS VSS VSS VDD

TXEN TRX_C E PWR_UP uPCLK aaaaaaaa VDD CD AM DR SPI_MISO SPI_MOSI SPI_SC K SPI_C SN

R2 22K C12 0603 27pF 24 23 22 21 20 19 18 17

J1 Loop Antenna, 433MHz 35x20mm C9 3.9pF aaaaaaaa

1 2 3 4 5 6 7 8

TRX_C E PWR_UP uPCLK VDD VSS CD AM DR

nRF 905

VSS IR EF VSS ANT2 ANT1 VDD_PA VSS VDD

C10 6.8pF VDD C13 27pF C3 180pF C11 4.7pF

C8 33pF 0603 C4 3.3nF 0603 X1

9 10 11 12 13 14 15 16 16 MHz R1 1M C1 22pF 0603 aaaaaaaa C2 22pF 0603

U1 nRF905

Figure 13 nRF905 Application schematic, differential connection to a loop antenna (433MHz).

Component
C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 R1 R2 U1 X1

Description
NP0 ceramic chip capacitor, (Crystal oscillator) NP0 ceramic chip capacitor, (Crystal oscillator) NP0 ceramic chip capacitor, (PA supply decoupling) X7R ceramic chip capacitor, (PA supply decoupling) NP0 ceramic chip capacitor, (Supply decoupling) X7R ceramic chip capacitor, (Supply decoupling) X7R ceramic chip capacitor, (Supply decoupling) NP0 ceramic chip capacitor, (Supply decoupling) NP0 ceramic chip capacitor, (Antenna tuning) NP0 ceramic chip capacitor, (Antenna tuning) NP0 ceramic chip capacitor, (Antenna tuning) NP0 ceramic chip capacitor, (Antenna tuning) NP0 ceramic chip capacitor, (Antenna tuning) 0.1W chip resistor, (Crystal oscillator bias) 0.1W chip resistor, (Reference bias) nRF905 Transceiver Crystal, CL = 12pF

VSS MISO MOSI SCK CSN XC1 XC2 VSS

Size
0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 QFN32L/5x5 LxWxH = 4.0x2.5x0.8

Value
22 22 180 3.3 33 4.7 10 33 3.9 6.8 4.7 27 27 1 22 16

Tol.
5% 5% 5% 10% 5% 10% 10% 5% 0.1 0.1 0.1 5% 5% 5% 1% 60ppm

Units
pF pF pF nF pF nF nF pF pF pF pF pF pF M k MHz

Table 15 Recommended external components, differential connection to a loop antenna (433MHz).

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PRODUCT SPECIFICATION
nRF905 Single Chip 433/868/915 MHz Radio Transceiver

11.2 PCB Layout Example; Differential Connection to a Loop Antenna Figure 14 shows a PCB layout example for the application schematic in Figure 13. A double-sided FR-4 board of 1.6mm thickness is used. This PCB has a ground plane on the bottom layer. Additionally, there are ground areas on the component side of the board to ensure sufficient grounding of critical components. A large number of via holes connect the top layer ground areas to the bottom layer ground plane. There is no ground plane beneath the antenna.

No components in bottom layer

a) Top silk screen

b) Bottom silk screen

c) Top view

d) Bottom view

Figure 14 PCB layout example for nRF905, differential connection to a loop antenna. A fully qualified RF-layout for the nRF905 and its surrounding components, including antennas and matching networks, can be downloaded from www.nordicsemi.no.

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PRODUCT SPECIFICATION
nRF905 Single Chip 433/868/915 MHz Radio Transceiver

11.3 Single ended connection to 50 antenna

868/915MHz C3 C9 33pF, 5% 3.9pF, 0.25pF
aaaaaaaa

433MHz 180pF, 5% 18pF, 5% 18pF, 5% Optional 6.8pF, 5% Optional 12nH, 5% 39nH, 5% 39nH, 5%

C10 3.9pF, 0.25pF C11 Optional

C12 2.2pF, 5%
VDD C7 10nF C5 33pF C6 4.7nF

C13 Optional L1 L2 L3 12nH, 5% 18nH, 5% 18nH, 5%

32 31 30 29 28 27 26 25

TXEN DVDD_1V2 VSS VSS VSS VSS VSS VDD

R2 22K 24 23 22 21 20 19 18 17

C9 L2 C12

C13 Optional aaaaaaaa 50 ohm RF I/O

TXEN TRX_CE PWR_UP uPCLK aaaaaaaa VDD CD AM DR SPI_MISO SPI_MOSI SPI_SCK SPI_CSN

1 2 3 4 5 6 7 8

TRX_CE PWR_UP uPCLK VDD VSS CD AM DR

nRF905

VSS IREF VSS ANT2 ANT1 VDD_PA VSS VDD

L1 C11 Optional L3 VDD C3

VSS MISO MOSI SCK CSN XC1 XC2 VSS

C10

C8 33pF

9 10 11 12 13 14 15 16

U1 nRF905

C4 3.3nF X1

16 MHz R1 1M C1 22pF C2 22pF

aaaaaaaa

Figure 15 nRF905 Application schematic, single ended connection to 50 antenna by using a differential to single ended matching network. It is recommended to add pull up or pull down resistors on signals that can enter a floating state. For the nRF905 it is recommended to have pull up on the CSN signal and pull down on the MOSI and SCK signal.

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PRODUCT SPECIFICATION
nRF905 Single Chip 433/868/915 MHz Radio Transceiver

Component
C1 C2 C3

Description
NP0 ceramic chip capacitor, (Crystal oscillator) NP0 ceramic chip capacitor, (Crystal oscillator) NP0 ceramic chip capacitor, (PA supply decoupling) @ 433MHz @ 868MHz @ 915MHz X7R ceramic chip capacitor, (PA supply decoupling) NP0 ceramic chip capacitor, (Supply decoupling) X7R ceramic chip capacitor, (Supply decoupling) X7R ceramic chip capacitor, (Supply decoupling) NP0 ceramic chip capacitor, (Supply decoupling) NP0 ceramic chip capacitor, (Impedance matching) @ 433MHz @ 868MHz @ 915MHz NP0 ceramic chip capacitor, (Impedance matching) @ 433MHz @ 868MHz @ 915MHz NP0 ceramic chip capacitor, (Impedance matching) NP0 ceramic chip capacitor, (Impedance matching) @ 433MHz @ 868MHz @ 915MHz NP0 ceramic chip capacitor, (Impedance matching) @ 433MHz @ 868MHz @ 915MHz Chip inductor, (Impedance matching) @ 433MHz: SRF> 433MHz @ 868MHz: SRF> 868MHz @ 915MHz: SRF> 915MHz Chip inductor, (Impedance matching) @ 433MHz: SRF> 433MHz @ 868MHz: SRF> 868MHz @ 915MHz: SRF> 915MHz Chip inductor, (Impedance matching) @ 433MHz: SRF> 433MHz @ 868MHz: SRF> 868MHz @ 915MHz: SRF> 915MHz 0.1W chip resistor, (Crystal oscillator bias) 0.1W chip resistor, (Reference bias) nRF905 Transceiver Crystal, CL = 12pF

Size
0603 0603 0603

Value
22 22 180 33 33 3.3 33 4.7 10 33 18 3.9 3.9

Tol.
5% 5% 5%

Units
pF pF pF

C4 C5 C6 C7 C8 C9

0603 0603 0603 0603 0603 0603

10% 5% 10% 10% 5% 5% <0.25pF <0.25pF

nF pF nF nF pF pF

C10

0603 18 3.9 3.9 Not fitted 6.8 2.2 2.2 0603 Not fitted Not fitted Not fitted 0603 12 12 12 0603 39 18 18 0603 39 12 12 1 22 16 5% 5% 5% 5% 1% 30ppm 5% 5% 5% 5% 5% <0.25pF <0.25pF

pF

C11 C12

0603 0603

pF pF 5% 5% 5% pF

C13

L1

nH

L2

nH

L3

nH

R1 R2 U1 X1

0603 0603 QFN32L/5x5 LxWxH = 4.0x2.5x0.8

M k MHz

Table 16 Recommended external components, single ended connection to 50 antenna.

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PRODUCT SPECIFICATION
nRF905 Single Chip 433/868/915 MHz Radio Transceiver

11.4 PCB Layout Example; Single Ended Connection to 50 Antenna Figure 16 shows a PCB layout example for the application schematic in Figure 15. A double-sided FR-4 board of 1.6mm thickness is used. This PCB has a ground plane on the bottom layer. Additionally, there are ground areas on the component side of the board to ensure sufficient grounding of critical components. A large number of via holes connect the top layer ground areas to the bottom layer ground plane.

No components in bottom layer

a) Top silk screen

b) Bottom silk screen

c) Top view

d) Bottom view

Figure 16 PCB layout example for nRF905, single ended connection to 50 antenna by using a differential to single ended matching network. A fully qualified RF-layout for the nRF905 and its surrounding components, including antennas and matching networks, can be downloaded from www.nordicsemi.no.

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nRF905 Single Chip 433/868/915 MHz Radio Transceiver

12 ABSOLUTE MAXIMUM RATINGS

Supply Voltages VDD.............................. - 0.3V to + 3.6V VSS .....................................................0V Input Voltage VI ..........................- 0.3V to VDD + 0.3V Output Voltage VO .........................- 0.3V to VDD + 0.3V Total Power Dissipation PD (TA=85C) ................................ 200mW Temperatures Operating temperature ........................................... - 40C to + 85C Storage temperature .............................................. - 40C to + 125C Note: Stress exceeding one or more of the limiting values may cause permanent damage to the device.

ATTENTION! Electrostatic sensitive device. Observe precaution for handling.

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PRODUCT SPECIFICATION
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13 GLOSSARY OF TERMS
Term ADC AM CD CLK CRC DR GFSK ISM kSPS MCU PWR_DWN PWR_UP RX SPI CSN MISO MOSI SCK SPS STBY TRX_EN TX TX_EN Description Analog to Digital Converter Address Match Carrier Detect Clock Cyclic Redundancy Check Data Ready Gaussian Frequency Shift Keying Industrial-Scientific-Medical kilo Samples per Second Micro Controller Unit Power Down Power Up Receive Serial Programmable Interface SPI Chip Select Not SPI Master In Slave Out SPI Master Out Slave In SPI Serial Clock Samples per Second Standby Transmit/Receive Enable Transmit Transmit Enable

Table 17 Glossary of terms.

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14 DEFINITIONS
Product Specification Identification
Objective Product Specification

Product Status Definition

Planned or Under Development. This specification contains the design objectives for product development. nRF: Specifications may change in any manner without notice. Engineering Samples and Pre Production series. This specification contains preliminary data. nRF: Nordic Semiconductor reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. The product is qualified for production. Changes will be notified according to industry standard criteria for Product/Process Change Notifications. Not In Production. This specification contains specifications on a product that has been discontinued by Nordic Semiconductor. The specification is printed for reference information only.

Preliminary Product Specification

Product Specification

Obsolete Product Specification

Table 18 Product status definitions Nordic Semiconductor ASA reserves the right to make changes without further notice to the product to improve reliability, function or design. Nordic Semiconductor does not assume any liability arising out of the application or use of any product or circuits described herein.

LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Nordic Semiconductor ASA customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Nordic Semiconductor ASA for any damages resulting from such improper use or sale.

Product specification revision date: 06.12.2005 Datasheet order code: 061205nRF905

All rights reserved . Reproduction in whole or in part is prohibited without the prior written permission of the copyright holder.

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nRF905 Single Chip 433/868/915 MHz Radio Transceiver

YOUR NOTES

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Nordic Semiconductor ASA World Wide Distributors

For Your nearest dealer, please see http://www.nordicsemi.no

Main Office: Vestre Rosten 81, N-7075 Tiller, Norway Phone: +47 72 89 89 00, Fax: +47 72 89 89 89 Visit the Nordic Semiconductor ASA website at http://www.nordicsemi.no

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Appendix C Source Code

delay.h /* delay.h */ #ifndef __DELAY_H #define __DELAY_H

10/07/2006

//20MHz #define dly200n asm("nop") #define dly400n dly200n;dly200n #define WaitFor1Us dly200n; dly200n; dly200n; dly200n; dly200n #define Jumpback asm("goto $ - 2") #define dly1u dly200n; dly200n; dly200n; dly200n #define dly2u dly1u; dly1u void DelayUs(unsigned char x); void DelayMs(unsigned char cnt); #endif

delay.c

30/07/2006

/***************************************************************************** * File: delay.c Date: July 10, 2006 Author: Dennis Leote Compiler: Hi-Tech PICC, Hi-Tech Software (http://www.htsoft.com) Description: This program provide the functions to perform delays between 0 - 255 us, and 0 - 255 ms for a PIC 16f877A u controller with a 20 MHz crystal. ***************************************************************************** */ #ifndef __DELAY_C #define __DELAY_C #include #include <pic.h> "delay.h"

unsigned char delayus_variable; /* * Function: DelayUs * Input: 8-bit value which defines the delay time (0 - 255 us) * Output: None * * Description: Will delay execution of further instructions (except Interrupts) * for a length of 0 - 255 us defined by x */ void DelayUs(unsigned char x) { delayus_variable=x; WaitFor1Us; asm("decfsz _delayus_variable,f"); Jumpback; } /* * Function: DelayMs * Input: 8-bit value which defines the delay time (0 - 255 ms) * Output: None * * Description: Will delay execution of further instructions (except Interrupts) * for a length of 0 - 255 ms defined by x */ void DelayMs(unsigned char cnt) { unsigned char i; do { i = 4; do { DelayUs(250); DelayUs(57); // fine tuning } while(--i); } while(--cnt); } #endif

mainRx.c

30/07/2006

/***************************************************************************** * File: main.c Date: July 10, 2006 Author: Dennis Leote Compiler: Hi-Tech PICC, Hi-Tech Software (http://www.htsoft.com) Description: This program runs on th PIC 16f877A uController for use with an nRF24L01 tranceiver Module configured as a receiver. Information is accepted in a 30-byte array and each byte is output to a PC via the UART in 0.5 ms intervals. ***************************************************************************** */ #include #include #include #include #include <pic.h> "Rx24L01.h" "C:\ekg\includes\delay.h" "C:\ekg\includes\uart.h" "C:\ekg\includes\spi.h"

void main(void) { spiConfig(); SetupComPort(); configure16f877_for_24L01(); configure_Rx24L01(); TRISB1 = 0; RB1 = 0; while(1) { while(IRQ); Rx24L01(); } }

// // // //

configure configure configure configure

16f877A SPI 16f877A UART 16f877A I/O nRF24L01 receiver

// wait for next received data packet // receive the next data packet and output to PC

mainTx.c

30/07/2006

/***************************************************************************** * File: main.c Date: July 10, 2006 Author: Dennis Loete Compiler: Hi-Tech PICC, Hi-Tech Software (http://www.htsoft.com) Description: This Program performs an A/D conversion on three input channels into the PIC 16f877A uController in regular 0.5ms intervals and saves the data in an 30-byte array. Once the array is full. The information is sent to an nRF24L01 tranceiver via the SPI interface on the PIC. ***************************************************************************** */ #include #include #include #include #include <pic.h> "C:\ekg\includes\delay.h" "C:\ekg\includes\uart.h" "C:\ekg\includes\spi.h" "Tx24L01.h"

#define CHAN1 1 #define CHAN2 2 #define CHAN3 3 void ekgTxInit(void); char getData(char); void convertByteToBits(char); main() { char leads[30], dataToSend[30]; int i, j = 0; ekgTxInit(); SetupComPort(); configure16f877_for_24L01(); configure_Tx24L01(); PORTD = 0x00; while(1){ // obtain 10 bytes of data from each of the A/D input channels for (i = 0; i < 30;) { leads[i++] = getData(CHAN1); // lead I data leads[i++] = getData(CHAN2); // lead II data leads[i++] = getData(CHAN3); // lead III data // delay 0.5 ms until next conversion. if (i != 30) { DelayUs(250); DelayUs(250); } } // transmit data through nRF24L01 Tx24L01(leads); // wait until transmission complete while (IRQ); } } /* * Function: ekgTxInit * Input: None 1

mainTx.c * Output: None * * Description: Configure the PIC A/D for three input channels. * RA0 = Lead I, RA1 = Lead II, RA5 = Lead III * RA2 = reference voltage - 0V * RA3 = reference voltage - 5V */ void ekgTxInit(void){ TRISD = 0x00; TRISA0 = 1; TRISA1 = 1; TRISA2 = 1; TRISA3 = 1; TRISA5 = 1; ADCON0 = 0x81; ADCON1 = 0x09; } // // // // // // output A/D result A/D channel 0 A/D channel 1 VrefVref+ A/D channel 2

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// set Fosc/32 and channel 0 (RA0) // RA0 = Analogue input, Vref+/Vref- = VDD/VSS;

/* * Function: getData * Input: channel - chooses which channel to perform the A/D conversion * Output: Result of A/D conversion. Stored in an 8-bit char * * Description: Performs the A/D conversion on a single channel defined by * "channel" input and obtains the lower 8 bits of the 10 bit * result. */ char getData(char channel) { // select channel switch(channel) { case CHAN1: ADCON0 = 0x81; break; case CHAN2: ADCON0 = 0x89; break; case CHAN3: ADCON0 = 0xA1; break; default: break; } // begin conversion DelayUs(50); ADGO = 1; while(ADGO); return ADRESH; } /* * Function: convertByteToBits * Input: byte_value = single byte * Output: None * * Description: Takes a byte and displays a the value in 8 bits - xxxxxxxx. * The bits are displayed by sending ascii '0' or '1' through * the serial port on a PC. PC would use Hyperterminal or some * similiar software to display the value */ void convertByteToBits(char byte_value) { char tmp; char i; // parse the byte bit-by-bit and send the appropriate '0' or '1' to UART for (i = 128; i > 0;) { tmp = byte_value & i; if (tmp == 0) uartTx('0'); else uartTx('1'); i >>= 1; 2

mainTx.c } uartTx(32); NEW_LINE; // move cursor to next line }

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Rx24L01.c

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/***************************************************************************** * File: Rx24L01.c Date: July 10, 2006 Author: Dennis Loete Compiler: Hi-Tech PICC, Hi-Tech Software (http://www.htsoft.com) Description: This program provides the functions necessary to interface with the Nordic Semiconductor nRF24L01 Transceiver modules. The is configured as a receiver with a 5-byte datapipe address, datarate of 2Mbps, CRC, Retransmit, and Enhanced Shockburst. ***************************************************************************** */ #include #include #include #include #include <pic.h> "Rx24L01.h" "C:\ekg\includes\uart.h" "C:\ekg\includes\delay.h" "C:\ekg\includes\spi.h"

void byteToBits(char); /* * Function: configure16f877_for_24L01 * Input: None * Output: None * * Description: Configures the PIC 16f877A uController to interface with the * transceiver through the SPI. */ void configure16f877_for_24L01(void) { spiConfig(); TRISB5 = 1; // IRQ pin TRISC2 = 0; // CE pin TRISC1 = 0; // CSN pin CE = 0; CSN = 1; } /* * Function: configure_Rx24L01 * Input: None * Output: None * * Description: Configures the nRF24L01 transceiver to perform as a receiver */ void configure_Rx24L01(void) { wReg(0x00, 0x09); // set this device as PRX wReg(0x01, 0x3F); // enable auto acknowledge (Tx) wReg(0x02, 0x03); // enable auto acknowledge (Rx) wReg(0x03, 0x03); // set address width to 5 Bytes wReg(0x04, 0x1F); // disable retransmit wReg(0x05, 0x02); // set channel 2 (default value) wReg(0x06, 0x0F); // set data rate = 2 Mbps // set Rx (pipe 1) address to E7E7E7E7E7 CSN = 0; spiTx(0x2A); spiTx(0xE7); spiTx(0xE7); spiTx(0xE7); spiTx(0xE7); spiTx(0xE7); CSN = 1; 1

Rx24L01.c DelayUs(10); // set Rx (pipe 1) address to C2C2C2C2C2 CSN = 0; spiTx(0x2B); spiTx(0xC2); spiTx(0xC2); spiTx(0xC2); spiTx(0xC2); spiTx(0xC2); CSN = 1; DelayUs(10); wReg(0x11, 0x1E); wReg(0x12, 0x1E); wReg(0x00, 0x0B); CE = 1; } /* * * * * * Function: Rx24L01 Input: None Output: None // set # bytes in payload (pipe 0) // set # bytes in payload (pipe 1) // power up

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Description: Receives a 30 byte array and sends the information through the

* PIC UART for display on a PC in 0.5 ms intervals. */ void Rx24L01(void) { int i, data[3]; char status; CE = 0; CSN = 0; status = spiTx(0x61); for (i = 0; i < 30;) { // LeadI data data[i] = spiRx(); uartTx(data[i++]); // LeadII data data[i] = spiRx(); uartTx(data[i++]); // LeadIII data data[i] = spiRx(); uartTx(data[i++]); // delay 0.5 ms if (i != 30) { DelayUs(250); DelayUs(250); } } RB1 ^= 1; CSN = 1; DelayUs(10); flushRx(); wReg(0x07, 0x7F); CE = 1; // flush Rx FIFO // clear previous interrupts // power up RF front end 2 // Power down RF front end // receive payload

Rx24L01.c }

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/* * Function: getStatus * Input: None * Output: Value of the nRF24L01 Staus register * * Description: Obtains the value of the nRF24L01 status register for debugging * purposes. */ char getStatus(void) { char status; CSN = 0; status = spiTx(0xFF); CSN = 1; DelayUs(10); return status; } /* * Function: showStatus * Input: None * Output: Value of the nRF24L01 Status register * * Description: Obtains and displays Status register and sends the value to * the PIC 16f877A UART for display on PC */ char showStatus(void) { char status; CSN = 0; status = spiTx(0xFF); CSN = 1; DelayUs(10); byteToBits(status); return status; } /* * Function: wReg * Input: address - addr of nRF24L01 register, value - byte value to be written * register at "address" * Output: Value of Staus register * * Description: This function writes an 8-bit value to one of the configuration * registers of the nRF24L01. The contents of the "Status" register * is returned for debugging purposes. */ char wReg(char address, char value) { char addr, status; addr = address | 0x20; CSN = 0; status = spiTx(addr); spiTx(value); CSN = 1; DelayUs(10); 3

Rx24L01.c return status; }

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/* * Function: rReg * Input: address - addr of configuration register to be read * Output: Contents of the register being addressed. * * Description: This function reads the value of the configuration register * at "address" */ char rReg(char address) { char reg_value; CSN = 0; spiTx(address); reg_value = spiRx(); CSN = 1; byteToBits(reg_value); DelayUs(10); return reg_value; } /* * Function: flushTx * Input: None * Output: None * * Description: Flushes the Transmit Stack of any values currently being stored */ void flushTx(void) { // flush tx stack CSN = 0; spiTx(0xE1); CSN = 1; DelayUs(10); } /* * Function: flushRx * Input: None * Output: None * * Description: Flushes the Receive Stack of any values currently being stored */ void flushRx(void) { // flush rx stack CSN = 0; spiTx(0xE2); CSN = 1; DelayUs(10); } /* * Function: readRegisters * Input: None * Output: None * * Description: Reads the values of the first seven configuration registers for * debugging purposes. */ void readRegisters(void) { 4

Rx24L01.c uartTx('R'); NEW_LINE; rReg(0x00); rReg(0x01); rReg(0x02); rReg(0x03); rReg(0x04); rReg(0x05); rReg(0x06); }

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/* * Function: ByteToBits * Input: byte_value = single byte * Output: None * * Description: Takes a byte and displays a the value in 8 bits - xxxxxxxx. * The bits are displayed by sending ascii '0' or '1' through * the serial port on a PC. PC would use Hyperterminal or some * similiar software to display the value */ void byteToBits(char byte_value) { char tmp; char i; for (i = 128; i > 0;) { tmp = byte_value & i; if (tmp == 0) uartTx('0'); else uartTx('1'); i >>= 1; } NEW_LINE; }

Rx24L01.h #ifndef __RX24L01_H #define __RX24L01_H #define CE #define CSN #define IRQ #define COMMAND #define DATA RC2 // Chip Enable RC1 // Chip Select NOT RB5 // Interrupt Request 1 0

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void configure16f877_for_24L01(void); void configure_Rx24L01(void); void Rx24L01(void); void byteToBits(char); void readRegisters(void); char getStatus(void); char showStatus(void); char wReg(char, char); char rReg(char); void flushTx(void); void flushRx(void); #endif

spi.c

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/***************************************************************************** * File: spi.c Date: July 10, 2006 Author: Dennis Leote Compiler: Hi-Tech PICC, Hi-Tech Software (http://www.htsoft.com) Description: This file rovides the functions necessary to use the PIC 16f877A SPI interface running on a 20MHz crystal oscillator. ***************************************************************************** */ #include <pic.h> #include "spi.h" #include "delay.h" /* * Function: spiConfig * Input: None * Output: None * * Description: Configures the 16f877 SPI */ void spiConfig(void) { STAT_CKE = 1; // Data transmitted on rising edge of SCK STAT_SMP = 0; // Input data sampled at middle of data output time CKP = 0; // Idle state for clock is a low level SSPEN = 1; // Enables serial port and configrues SCK, SDO, SDI, and SS as the source of the serial port pins SSPM0 = 1; // SPI Master mode, clock = Fosc/16 TRISC5 = 0; // SDO TRISC3 = 0; // SCK } /* * Function: spiTx * Input: 8-bit data value * Output: Value of the nRF24L01 Staus register * * Description: This function sends one byte of data to an nRF24L01 tranceiver * module through the SPI interface. The value of the Status * register is returned */ char spiTx(char data) { char buf_value; SSPBUF = data; while(!SSPIF); buf_value = SSPBUF; SSPIF = 0; return buf_value; } /* * Function: spiRx * Input: None * Output: 8-bit value * * Description: Obtains one byte of data from the nRF24L01 tranceiver module */ char spiRx(void) { 1

spi.c char value; TRISC5 = 1; value = spiTx(0x00); TRISC5 = 0; return value; }

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spi.h #ifndef __SPI_H #define __SPI_H void spiConfig(void); char spiTx(char); char spiRx(void); #endif

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Tx24L01.c

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/***************************************************************************** * File: Tx24L01.c Date: July 10, 2006 Author: Dennis Loete Compiler: Hi-Tech PICC, Hi-Tech Software (http://www.htsoft.com) Description: This program provides the functions necessary to interface with the Nordic Semiconductor nRF24L01 Transceiver modules. The is configured as a transmitter with a 5-byte datapipe address, datarate of 2Mbps, CRC, Retransmit, and Enhanced Shockburst. ***************************************************************************** */ #include #include #include #include #include <pic.h> "Tx24L01.h" "C:\ekg\includes\uart.h" "C:\ekg\includes\delay.h" "C:\ekg\includes\spi.h"

void byteToBits(char); /* * Function: configure16f877_for_24L01 * Input: None * Output: None * * Description: Configures the PIC 16f877A uController to interface with the * transceiver through the SPI. */ void configure16f877_for_24L01(void) { spiConfig(); // configure the SPI with clock = 20MHz / 16 TRISB5 = 1; // IRQ pin TRISC2 = 0; // CE pin TRISC1 = 0; // CSN pin CE = 0; CSN = 1; // RB0 used for debugging TRISB1 = 0; RB0 = 0; } /* * Function: configure_Tx24L01 * Input: None * Output: None * * Description: Configures the nRF24L01 transceiver to perform as a transmitter */ void configure_Tx24L01(void) { CE = 0; CSN = 0; wReg(0x00, wReg(0x01, wReg(0x02, wReg(0x03, wReg(0x04, wReg(0x05, wReg(0x06, 0x08); 0x3F); 0x03); 0x03); 0x1F); 0x02); 0x0F); // // // // // // // set PTX enable auto acknowledge (Tx) enable auto acknowledge (Rx) set address width to 5 Bytes four retransmit attempts set channel 2 (default value) set data rate = 2 Mbps

// set Rx address to E7E7E7E7E7 1

Tx24L01.c CSN = 0; spiTx(0x2A); spiTx(0xC2); spiTx(0xC2); spiTx(0xC2); spiTx(0xC2); spiTx(0xC2); CSN = 1; DelayUs(50); // set Tx address to E7E7E7E7E7 CSN = 0; spiTx(0x30); spiTx(0xC2); spiTx(0xC2); spiTx(0xC2); spiTx(0xC2); spiTx(0xC2); CSN = 1; DelayUs(50); } /* * Function: Tx24L01 * Input: 30-byte array * Output: None * * Description: Transmits the input array */ void Tx24L01(char leads[]) { int i; wReg(0x07, 0x7F); wReg(0x00, 0x0A); flushTx(); // Transmit data CSN = 0; spiTx(0xA0); for(i = 0; i < 30; i++) { spiTx(leads[i]); } CSN = 1; DelayUs(10); CE = 1; DelayUs(20); CE = 0; } // clear previous interrupts // power up

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/* * Function: showStatus * Input: None * Output: None * * Description: Sends the contents of the nRF24L01 status register through * the UART for display in Hyperterminal - Used for debugging */ void showStatus(void) { char status; CSN = 0; status = spiTx(0xFF); 2

Tx24L01.c CSN = 1; DelayUs(10); byteToBits(status); }

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/* * Function: wReg * Input: address - addr of nRF24L01 register, value - byte value to be written * register at "address" * Output: Value of Staus register * * Description: This function writes an 8-bit value to one of the configuration * registers of the nRF24L01. The contents of the "Status" register * is returned for debugging purposes. */ char wReg(char address, char value) { char addr, status; addr = address | 0x20; CSN = 0; status = spiTx(addr); spiTx(value); CSN = 1; DelayUs(10); return status; } /* * Function: rReg * Input: address - addr of configuration register to be read * Output: Contents of the register being addressed. * * Description: This function reads the value of the configuration register * at "address" */ char rReg(char address) { char reg_value; CSN = 0; spiTx(address); reg_value = spiRx(); CSN = 1; byteToBits(reg_value); DelayUs(10); return reg_value; } /* * Function: flushTx * Input: None * Output: None * * Description: Flushes the Transmit Stack of any values currently being stored */ void flushTx(void) { // flush tx stack CSN = 0; spiTx(0xE1); CSN = 1; 3

Tx24L01.c DelayUs(10); }

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/* * Function: flushRx * Input: None * Output: None * * Description: Flushes the Receive Stack of any values currently being stored */ void flushRx(void) { // flush rx stack CSN = 0; spiTx(0xE2); CSN = 1; DelayUs(10); } /* * Function: readRegisters * Input: None * Output: None * * Description: Reads the values of the first seven configuration registers for * debugging purposes. */ void readRegisters(void) { uartTx('R'); NEW_LINE; rReg(0x00); rReg(0x01); rReg(0x02); rReg(0x03); rReg(0x04); rReg(0x05); rReg(0x06); } /* * Function: ByteToBits * Input: byte_value = single byte * Output: None * * Description: Takes a byte and displays a the value in 8 bits - xxxxxxxx. * The bits are displayed by sending ascii '0' or '1' through * the serial port on a PC. PC would use Hyperterminal or some * similiar software to display the value */ void byteToBits(char byte_value) { char tmp; char i; for (i = 128; i > 0;) { tmp = byte_value & i; if (tmp == 0) uartTx('0'); else uartTx('1'); i >>= 1; } NEW_LINE; }

Tx24L01.h #ifndef __TX24L01_H #define __TX24L01_H #define CE #define CSN #define IRQ #define COMMAND #define DATA void void void void void char char void void RC2 // Chip Enable RC1 // Chip Select NOT RB5 // Interrupt Request 1 0

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configure16f877_for_24L01(void); configure_Tx24L01(void); Tx24L01(char data[]); readRegisters(void); showStatus(void); wReg(char, char); rReg(char); flushTx(void); flushRx(void);

#endif

uart.c

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/***************************************************************************** * File: uart.c Date: July 10, 2006 Author: Dennis Leote Compiler: Hi-Tech PICC, Hi-Tech Software (http://www.htsoft.com) Description: This file provides the functions necessary to use the PIC 16f877A Universal Asynchronous Receiver Transmitter (UART) interface. ***************************************************************************** */ #include <pic.h> #include "uart.h" /* * Function: SetupComPort * Input: None * Output: None * * Description: Will setup COM port for 20Mhz clk with 115200 Baud */ void SetupComPort(void) { char dummy; TRISC6 = 1; TRISC7 = 1; SPBRG = 10; // 115200 Baud // SPBRG = (20000000/(16UL * 19200) -1); // 19200 Baud BRGH = 1; TX9 = 0; // High data rate for sending // 8-bit transmission // 8-bit reception // Asynchronous // Enable serial port pins // Clear the RCIF interrupt flag // Enable reception // Enable the transmitter // Clear the RCREG

RX9 = 0; SYNC = 0; SPEN = 1; RCIF = 0; CREN = 1; TXEN = 1; dummy = RCREG; }

/* * Function: uartTx * Input: One byte value to transmit * Output: None * * Description: Will transmit a given character defined by txChar */ void uartTx(char txChar) { while(!TXIF); // Wait while other transmission is over TXREG = txChar; // Place the given character in tx buffer ResetRx(); // Clears Interrupt flags } /* * Function: uartRx * Input: None 1

uart.c

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* Output: One byte value received by UART * * Description: Receive a character from object interfaced to by UART */ char uartRx(void) { char dummy = '\0'; if (RCIF) { dummy = RCREG; ResetRx(); ResetTx(); } return dummy; } /* * Function: uartTxLine * Input: String to be transmitted * Output: None * * Description: Sends a string of characters through the UART one byte at a time */ void uartTxLine(char *line_out) { int i; while(line_out[i] != '\0') {uartTx(line_out[i++]);} } /* * * * * * Function: ResetTx Input: None Output: None Description: Resets the interrupt flags associated with the UART to prepare // If receive interrupt flag is set // Get the character stored in rx buffer // Clears the interrupt flags // Clears the interrupt flags

* for next transmission. */ void ResetTx(void) { TXEN = 0; TXEN = 1; } /* * * * * * Function: ResetRx Input: None Output: None Description: Resets the interrupt flags associated with the UART to prepare

* for next reception. */ void ResetRx(void) { CREN = 0; CREN = 1; }

uart.h #ifndef __UART_H #define __UART_H #define NEW_LINE uartTx(10);uartTx(13) void void void void char void SetupComPort(void); uartTxLine(char*); ResetTx(void); ResetRx(void); uartRx(void); uartTx(char); // // // // // // Setup for 19200 Baud Transmit a line Reset Transmitter Reset Receiver Receieve a char Transmit a char

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#endif