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1.Designacircuit(positiveedge)thatdetectthesequencewheninputchanges from0to1,theoutputshouldgohighforonlyoneclockpulse.

clk rst in out

2.Designacircuittodetectwhenthe216bitsinputsaresame. 3.Assumeb=3andc=5,afterthefirst@(posedgeclk)whatisthevalueofa?

4. Afterthefirst@(posedgeclk),doesthisdoaswap?

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5.Considerthefollowingcode: `defineFALSE0 `defineTRUE1 initial begin a=`FALSE; a<=`TRUE; if(a==`TRUE) $display("True"); else $display("False"); end Whatwillprintout?TrueorFalse? 6.DesignAND,ORgateusing2:1mux. 7.DrawthecircuittoavoidtheSetupandHoldtimeviolation. 8.Considerthefollowingcode: always@(posedgeclk) if(rst==0) out<=1b0; else out<=data_in; a. Drawthesynthesisviewfortheabovecode. b. ModifythecodeforAsynchronousReset. c. Drawthetimingdiagramforsynchronousandasynchronousreset. 9.Howtotestthefunctionality(testcases)ofaFIFO. 10.WhatistheadvantageofusingGraycodeinsteadofBinarycodewhile designingFIFO. 11.Whataretheparameterstobeconsideredbeforestartingthedesignwork. 12.DesignEXORgateusing4NANDgates. 13.DesignEXNORgateusing4NORgates.
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14.Whatwillbethesynthesisstructure?

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15.Considerthefollowingcode, always@(posedgeclk) begin a=b; b=c; c=a; end Whatlogicdoesthecodeimplies.

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