Project Man Hinh TFT Voi FPGA

Application Report
Thit k b iu khin cho TFT LCD trn

Kit FPGA Leopard I
April 2013 , HFAR04 Rev 1.0
Hoang Nguyen
1. Gii thiu:
Ngy ny, cc thit b LCD hin din trong hu ht cc sn phm t dn dng cho ti
qun s bi v kh nng hin th nhiu thng tin, giao din p bt mt v giao tip vi
ngi dng hiu qu. s dng c LCD,h thng cn cc b iu khin hin th
(LCD controller) , n chu trch nhim ly d liu , nh dng v xut ra LCD cng cc
tn hiu iu khin tng ng. B iu khin LCD s gip cc MCU tp trung vo cc
cng vic x l khc. Hin nay nhiu MCU ) , n chu trch nhim ly d liu , nh
dng v xut ra LCD cng cc tn hiu iu khin tng ng. B iu khin LCD s gip
cc MCU tp trung vo cc cng vic x l khc. Hin nay nhiu MCU tch hp sn
cc b iu khin LCD bn trong chip nh Motorola MC9328MX1, TI OMAP ,
StrongARM , Freescale iMX
Trong ti liu ny, chng ta s xem xt thit k mt LCD Controller IP trn chip
FPGA s dng ngn ng verilog. Thit k s dng Kit FPGA Leopard I ca Titans
technology th nghim trn thc t.
Hnh 1: Kit FPGA Leopard I
bit thm chi tit , chc nng v hng dn s dng kit FPGA Leopard I, vui lng
tham kho ti y:
http://titans.com.vn/index.php?page=shop.product_details&product_id=70&option=co
m_virtuemart
Design a LCD Controller on FPGA Leopard I Dev Kit
2. Nguyn l hot ng :
Hnh sau th hin h thng thng thng c tch hp b LCD controller.
Hnh 2: H thng thng thng vi b LCD controller tch hp
B LCD controller s chu trch nhim iu khin TFT LCD, c d liu t

framebuffer (cha trong SRAM hoc SDRAM) bng DMA , v xut d liu hin th ln
LCD. B iu khin LCD thng thng c th cu hnh cc ch hot ng bi cc
master nh CPU.
B LCD Controller c th truy xut trc tip b nh SRAM hoc SDRAM bng
DMA m khng cn thng qua CPU m bo bng thng hin th c m bo.
B LCD Controller cng phi to ra cc ngt EOF (end of frame) , cc ngt ny
gip cho CPU kim sot c hot ng ca LCD controller iu khin d liu cho
ng b vi qu trnh hin th.
Titans Technology | www.titans.com.vn / www.hlab.com.vn

Copyright 2013, Titans Technology
HFAR04
Kit FPGA Leopard I ca Titans Technology:

Kit FPGA Leopard I do Titans Technology (www.titans.com.vn ) sn xut theo
thit k ca phng th nghim H-laboratory (www.hlab.com.vn) . Kit Leopard thit k
da trn FPGA Altera Cyclone III vi kin trc multi-core bao gm chip FPGA giao tip
vi chip MCU ARM Cortex M3 ca ST Microelectronics. Board c thit k nhm
ti cc thit k v iu khin cn cc b tng tc hardware, hoc cc i tng mi tm
hiu v FPGA c th thit k giao tip vi cc ngoi vi c bn nh led, nt nhn, lcd
charactor, sd card, uart Ngoi ra, board cng ph hp vi nhng ai pht trin cc li
IP cn giao tip vi MCU test nh thit k core I2C, UART, SPI, hay cc giao tip tc
cao khc.
Hnh 3 : Kit FPGA Leopard I ca Titans Technology
FPGA Leopard I Development Kit
Cyclone III EP3C16Q240

ARM Cortex M3 STM32F103RCT
8x User Buttons, 8x general purpose leds
USB 2.0 Interface
LCD 16x2 charactor.
4x Led 7-Segments
2x RS232 with DB9 Connector
MMC/SD Card socket
32KB SRAM
4Mbits EEPROM
AS and JTAG configuration support.

HFAR04
3 Oscilators : 50Mhz, 27Mhz, external SMA

40-Pins Expansion Connector.
Cyclone III EP3C16Q240

o 15.400 LEs.
o 56 M9K Memory Blocks.
o 516.096 On-chip Memory bits.
o 56 18x18 Multipliers.
o 4xPLL.
o Maximum 160 IOs.
STM32F103RCT
o ARM 32-bit Cortex-M3 CPU
o 72 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.1)
o 512 Kbytes of Flash memory
o 64 Kbytes of SRAM
o 3 12-bit, 1 s A/D converters (up to 21 channels)
o 2 12-bit D/A converters
o DMA: 12-channel DMA controller
o Debug Serial wire debug (SWD) & JTAG interfaces
o Up to 11 timers
2
o Up to 2 I C interfaces (SMBus/PMBus)
o Up to 5 USARTs (ISO 7816 interface, LIN, IrDA capability, modem control)
2
o Up to 3 SPIs (18 Mbit/s), 2 with I S interface multiplexed
o USB 2.0 full speed interface
o CRC calculation unit, 96-bit unique ID
bit thm chi tit , chc nng v hng dn s dng kit FPGA Leopard I, vui lng
tham kho ti y:
http://titans.com.vn/index.php?page=shop.product_details&product_id=70&option=com_virtuemart.

HFAR04
Module LCD 4.3 Inch (TLCD43F):
Hnh 4 : Module TLCD43F ca titans Technology
Module LCD ny tng thch vi Kit FPGA Leopard I, LCD c phn gii 480x272 ,
Kch thc mn hnh 4.3Inch (16:9) , h tr Touch Screen , chun giao tip song song .
Chi tit v sn phm, xem y :
http://www.titans.com.vn/index.php?option=com_virtuemart&page=shop.product_details
&flypage=flypage.tpl&product_id=128
3. Kin trc :
3.1. S khi ca LCD Controller IP Core:
Trc tin Hnh sau m t s khi chc nng ca LCD IP Core.Core ny c hai
port d liu. Mt port DMA read master v mt port configuration slave. D liu video
c c t b nh h thng bng port DMA read master v c lu vo b RBG FIFO.
Sau d liu c c ra khi FIFO v c a ra LCD bi khi Timing Control. Port
configuration Slave dng cu hnh cc thanh ghi hot ng ca LCD Controller Core.

HFAR04

Hnh 5 : S khi chc nng ca LCD IP Core.
S chn ca LCD Controller
Hnh 6 : S chn ca LCD IP Core.
3.2. Cc khi chc nng:

a. Khi timing Control :
Khi ny c nhim v iu khin timing cho LCD. Khi ny iu khin cc tn

hiu VSYNC, HSYNC, LCD_OE , PCLK ca LCD.

HFAR04

Hnh 7 : nh thi cho qut ngang ca LCD
Hnh 8 : nh thi cho qut dc ca LCD
c thi gian chnh xc ca thpw ,thbp , thfp , tvpw ,tvbp , tvfp , tham kho LCD
Module tng ng.
b. Khi Colorbar Test :
Khi ny c nhim v to ra cc thanh mu test mn hnh. Vi khi ny, ta c

th test hin th m khng cn phi ly d liu video t b nh h thng.
c. Khi DMA Engine :
Khi ny thc hin vic c d liu t b nh h thng ly d liu hin th. V

d liu hnh nh l rt ln, do khi ny phi truy xut mt lng d liu rt nhiu
trong mt khong thi gian ti thiu. Khi DMA cho php LCD Controller ly d
liu hin th t b nh trc tip , m khng cn thng qua CPU.
d. Khi FIFO :
Khi ny lu d liu tm thi RGB t b nh h thng hin th ln LCD. Bi

v khi hin th cn chui d liu lin tc. Do bt k mt s ngt qung d liu
no cng gy nn s hin th sai. V vy, FIFO phi di lu tr ton b mt
dng ca hnh nh.
6
B FIFO c iu khin bi hai min clock khc nhau. N c ghi d liu vo

bi khi DMA v ng b vi clock h thng. Trong khi ti pha bn kia, n li c
c ra bi b hin th LCD vi tn s ng b vi tc hin th ca LCD . Tc

HFAR04
ny lin quan n tc qut mn hnh, phn gii , tn hiu qut dc v qut

ngang.
e. Khi Control/Status Register :
y l khi thanh ghi iu khin, iu khin cc chc nng hin th ca LCD .

Chi tit cc thanh ghi xem phn thanh ghi iu khin.
3.3. Thanh ghi iu khin:
f.
Control Register (CR):
Thanh ghi ny iu khin cc hot ng chnh ca LCD

Control Register
Bit
0
2:1
T vit tt
EN_DMA
VDM
VSD
IE
BL
PS
M t
Cho php DMA hot ng
Video Display Mode
0 : RGB666
1 : RGB565
2 : RGB8bit
0 : hng bnh thng
1: o hng
0 : DMA Interrupt Disable
1 : DMA Interrupt Enable
0 : LCD Backlight OFF
1 : LCD Backlight ON
0 : LCD Power Supply OFF
1 : LCD Power Supply ON

HFAR04

g. Status Register (SR):
Thanh ghi ny th hin trng thi hot ng ca LCD

Status Register
Bit
0
31:0
T vit tt
EOF
--
M t
Tch cc khi hin th n cui Frame
Khng s dng
h. Next Buffer Address Register (NBA):
Thanh ghi ny cho bit a ch ca Frame Buffer m b hin th cn ly d liu

hin th.
Next Buffer Address Register
Bit
13:0
i.
T vit tt
NBAR
M t
Ch nh a ch ca video buffer k tip
Interrupt Status Register (ISR):
Thanh ghi ny cho trng thi ca ngt nu cho php ngt. Ngt xy ra khi kt thc
mt frame, tn hiu ny gip CPU ng b qu trnh x l d liu vi qu trnh hin
th trn mn hnh.
Next Buffer Address Register
Bit
31:0
T vit tt
ISR
M t
1 : c ngt xy ra
0 : Khng c ngt xy ra
c tn hiu ny s t ng xa ngt hin ti.
3.4. Thc hin LCD Controller IP Core trn Kit Leopard I:

thc hin demo ny, chng ta cn b Kit LCD FTS5 tng thch vi Kit
Leopard I.
Kt ni phn cng:
chy c demo ny, chng ta cn cc thnh phn sau.
o
o
o
o
o
Phn mm Altera Quartus II version 9.0 hoc cao hn.

Kit FPGA Leopard I (xem ti y )
Cp USB Blaster (xem ti y )
Module LCD 4.3Inch (xem ti y)
Kt ni Kit Leopard vi TLCD43F nh hnh sau

HFAR04
Hnh 9 : Kt ni HPS Leopard I vi Module LCD Touch Screen
4. Hnh nh Demo trn Kit Leopard I:

Demo c compile trn Quartus II 9.0, test trn Kit HPS Leopard I , v LCD
4.3Inch TLCD43F
Hnh 10 : Demo LCD Controller trn Kit FPGA HPS Leopard I

HFAR04
5. Table of Contents
Application Report............................................................................................ 0
Thit k b iu khin cho TFT LCD trn Kit FPGA Leopard I .............................................. 0
1.
Gii thiu:........................................................................................................................................ 0
2.
Nguyn l hot ng : ...................................................................................................................... 1
3.
Kin trc : ........................................................................................................................................ 4

3.1.
S khi ca LCD Controller IP Core: ..................................................................................... 4
3.2.
Cc khi chc nng: ................................................................................................................. 5
a.
Khi timing Control : ................................................................................................................ 5
b.
Khi Colorbar Test : .................................................................................................................. 6
c.
Khi DMA Engine :.................................................................................................................... 6
d.
Khi FIFO :................................................................................................................................ 6
e.
Khi Control/Status Register : .................................................................................................. 7
3.3.
Thanh ghi iu khin: ............................................................................................................... 7
f.
Control Register (CR): ............................................................................................................... 7
g.
Status Register (SR): ................................................................................................................. 8
h.
Next Buffer Address Register (NBA): ......................................................................................... 8
i.
Interrupt Status Register (ISR): ................................................................................................. 8
3.4.
Thc hin LCD Controller IP Core trn Kit Leopard I: ................................................................. 8
4.
Hnh nh Demo trn Kit Leopard I: ................................................................................................... 9
5.
Table of Contents........................................................................................................................... 10
5.1.
6.
Reference............................................................................................................................... 11
Document Revision History ............................................................................................................ 11
10

HFAR04
5.1. Reference
tt_nios2_hardware_tutorial
Wikipedia.com
Websites from Internet
http://www.altera.com
6. Document Revision History
HFAR04 Rev 1.0 ( 4/2013 )

Phin bn u tin
Copyright 2009 Titans Technology. Ti liu ny thuc

bn quyn ca Titans Technology (www.titans.com.vn),
chng ti hy vng cc bn khi s dng vi bt k mc ch
no bng bt c hnh thc no bao gm sao chp, in, copy,
trch dn cn phi ghi r xut x ngun gc t trang web
ca chng ti
Hy truy xut trang web ca chng ti thng xuyn c nhng cp nht mi nht
v cc thit b mi nht ti website www.titans.com.vn.
11
Nu c bt c kin ng gp cng nh cn h tr, t vn thm thng tin v sn

phm, vui lng gi mail n a ch email: support@titans.com.vn

HFAR04

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Application Report

Thit k b iu khin cho TFT LCD trn

Hnh 1: Kit FPGA Leopard I

Design a LCD Controller on FPGA Leopard I Dev Kit

Hnh 2: H thng thng thng vi b LCD controller tch hp

B LCD controller s chu trch nhim iu khin TFT LCD, c d liu t

Titans Technology | www.titans.com.vn / www.hlab.com.vn

Design a LCD Controller on FPGA Leopard I Dev Kit

Kit FPGA Leopard I ca Titans Technology:

Hnh 3 : Kit FPGA Leopard I ca Titans Technology

FPGA Leopard I Development Kit

Cyclone III EP3C16Q240

Titans Technology | www.titans.com.vn / www.hlab.com.vn

Design a LCD Controller on FPGA Leopard I Dev Kit

3 Oscilators : 50Mhz, 27Mhz, external SMA

Cyclone III EP3C16Q240

Titans Technology | www.titans.com.vn / www.hlab.com.vn

Design a LCD Controller on FPGA Leopard I Dev Kit

Module LCD 4.3 Inch (TLCD43F):

Hnh 4 : Module TLCD43F ca titans Technology

Titans Technology | www.titans.com.vn / www.hlab.com.vn

Design a LCD Controller on FPGA Leopard I Dev Kit

S chn ca LCD Controller

Hnh 6 : S chn ca LCD IP Core.

3.2. Cc khi chc nng:

Khi ny c nhim v iu khin timing cho LCD. Khi ny iu khin cc tn

Titans Technology | www.titans.com.vn / www.hlab.com.vn

Design a LCD Controller on FPGA Leopard I Dev Kit

Hnh 8 : nh thi cho qut dc ca LCD

b. Khi Colorbar Test :

Khi ny c nhim v to ra cc thanh mu test mn hnh. Vi khi ny, ta c

Khi ny thc hin vic c d liu t b nh h thng ly d liu hin th. V

Khi ny lu d liu tm thi RGB t b nh h thng hin th ln LCD. Bi

B FIFO c iu khin bi hai min clock khc nhau. N c ghi d liu vo

Titans Technology | www.titans.com.vn / www.hlab.com.vn

Design a LCD Controller on FPGA Leopard I Dev Kit

ny lin quan n tc qut mn hnh, phn gii , tn hiu qut dc v qut

y l khi thanh ghi iu khin, iu khin cc chc nng hin th ca LCD .

3.3. Thanh ghi iu khin:

Control Register (CR):

Thanh ghi ny iu khin cc hot ng chnh ca LCD

Titans Technology | www.titans.com.vn / www.hlab.com.vn

Design a LCD Controller on FPGA Leopard I Dev Kit

Thanh ghi ny th hin trng thi hot ng ca LCD

h. Next Buffer Address Register (NBA):

Thanh ghi ny cho bit a ch ca Frame Buffer m b hin th cn ly d liu

Interrupt Status Register (ISR):

3.4. Thc hin LCD Controller IP Core trn Kit Leopard I:

Phn mm Altera Quartus II version 9.0 hoc cao hn.

Titans Technology | www.titans.com.vn / www.hlab.com.vn

Design a LCD Controller on FPGA Leopard I Dev Kit

Hnh 9 : Kt ni HPS Leopard I vi Module LCD Touch Screen

4. Hnh nh Demo trn Kit Leopard I:

Hnh 10 : Demo LCD Controller trn Kit FPGA HPS Leopard I

Design a LCD Controller on FPGA Leopard I Dev Kit

Nguyn l hot ng : ...................................................................................................................... 1

Kin trc : ........................................................................................................................................ 4

S khi ca LCD Controller IP Core: ..................................................................................... 4

Cc khi chc nng: ................................................................................................................. 5

Khi timing Control : ................................................................................................................ 5

Khi Colorbar Test : .................................................................................................................. 6

Khi DMA Engine :.................................................................................................................... 6

Khi FIFO :................................................................................................................................ 6

Khi Control/Status Register : .................................................................................................. 7