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The charts that follow are extracted from this I/O Guidelines document
Disk Array 2 Disk Array 3 Disk Array 4 Disk Array 5 Disk Array 6
48 Port BYNET/SM Switch
Clique 1
the 2-clique cabinet 3 Optional TMS in the 1-clique cabinet 2 Optional Channel Servers in the 1-clique cabinet
3 > November 09, 2009 Teradata Confidential
19 18 17 16 15 14 13 12 12 Disk Arrays (one 12-disk tray per DA) 11 > 12 disk tray with built-in dual controllers 10 > 36 disks per node (3 12-disk arrays) 9 8 > SAS 15K 300GB disk drives 7 2 BYNET/SM Ethernet Switches 6 > Two 48 Port Ethernet Switches (Dell 6248) 5 4 1 SMWeb CMIC 1 Optional Teradata Managed Server (TMS) in 3 2
1
Disk Array 6 Disk Array 5 Disk Array 3 Disk Array 2 Disk Array 1 Node 2 Node 1 TMS CMIC Node 1 Node 2 Disk Array 1 Disk Array 4
Clique 2
TMS
TMS
Channel Server Channel Server TMS CMIC Node Node 12 Drive Enclosure 12 Drive Enclosure 12 Drive Enclosure 12 Drive Enclosure 12 Drive Enclosure 12 Drive 48 Port BYNET/SM Switch Enclosure AC box PD AC box U
AC box PD AC box
2-Clique Cabinet
Rear View
4 Gb Ethernet ports
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Disk Arrays are connected to Adapters according to BIOS slot discovery sequence
A1
A3 A2
SM Ports
Left = eth0 Right = eth1
BYNET Ports
Left = eth2 = BYNET 1 Right = eth3 = BYNET 0
2555 Node
SM Ports
BYNET Ports
Left = eth0 = BYNET 0 Right = eth1 = BYNET 1
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MEMORY
MEMORY
ESI x4
0 4
Tylersburg-36D IOH
5 6 7 8 9 10
x4 x4 x4 x4 x4 x4 x4 x8 x8 8 C 10
1 x2 x4 2 3 x4
x2
PCI 1
Enet
SM3G
x4 x1 x1
PCIe SW APIC 8
PCI 2
Enet
BYNET
PCI 3
ICH9
33 PCI 14
Center Riser
In HBA: PCI 9,A,B PCI 8 S1: Quad FC S2: Quad Enet PCI 4 PCI 10 PCI C
Left Riser
S3: Quad FC S4: Quad FC In HBA: PCI 11,12,13 In HBA: PCI D,E,F
iDRAC
Video
R710 Node
Dev 1D Dev 1F Dev 1F F 0-3 Fun 0 Fun 2 PCI 32/33 PCI 0 Dev 0 Dev 0 Dev 0
SLOT 1 Dev 0
Quad FC
SLOT 3 Dev 0
Quad FC
Dev 3
PCIe x4 PCI 3
PCIe x4 PCI 1
Broadcom 5709C Ethernet
PCIe x4 PCI 2
Broadcom 5709C Ethernet
USB
LPC
SATA Ctrl
SAS Ctrl
SLOT 2 Dev 0
Quad Enet
Copper
PCIe2 x4 PCI 4
PCIe2 x8 PCI C
SLOT 4 Dev 0
Quad FC
SM3G ports
BYNET ports
1 Storage HBA plus 1 Quad Ethernet adapter for client and BAR
2 Storage HBAs
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FICON (PXFA) or ESCON (PXSA4) adapter 2nd FICON (PXFA) or ESCON (PXSA4) adapter if needed Not used (limit 2 Channel adapters) Option slot (1Gb Ethernet (PRO/1000 PT Quad)) Option slot for SM3G connections
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Name
Form
PCIe2/HP PCIe/LP
Supplier
Feature #
9157-F248 9157-F237
Mfg Part #
007-9970566 007-9984264
System
2580
Class#
9157
PPL#
315-0601255
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For this configuration the ports on the host adapters are as follows:
2555 Clique
Quad 4Gb HBAs
Node 1
1 4 3
Node 2
1 4 3
Node 1
Node 2
1 2 3
PCI Slots
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
Array 1
(12 dsks)
Array 2
(12 dsks)
Array 3
(12 dsks)
Array 4
(12 dsks)
Array 5
(12 dsks)
Array 6
(12 dsks)
Array 1
(12 dsks)
Array 2
(12 dsks)
Array 3
(12 dsks)
Array 4
(12 dsks)
Array 5
(12 dsks)
Array 6
(12 dsks)
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A1
A3
A2
Dell Node
SM Ports
Left = eth0 Right = eth1
BYNET Ports
Left = eth2 = BYNET 1 Right = eth3 = BYNET 0
FC Port 1 FC Port 2
FC Port 1 FC Port 2
Controller B
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19
18 17 16 15 14
13 12
9 8
7 6 5 4 3
12 Drive CRUs
Drive CRU LEDs Service Action Allowed Self ID / Fault In Place / Active
Tray 0, Slot 12
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LUN Layout
0 1 2 3 4 5
0 0 0 0 0 0
1, 2, 5, 6, 9, 10,
3 4 7 8 11 12
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Backup
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Device #
Func #
Vendor ID
SID
0235
1028
0235
ICH/USB Controllers ICH/USB 2.0 EHCI Controller ICH/PCI Bridges (to bus X - disabled) ICH/PCI Bridges (to bus X - disabled) ICH/PCI Bridges (to bus X - disabled) ICH/USB Controllers ICH/USB 2.0 EHCI Controller ICH/82801 PCI Bridge (to bus 14) (VGA ctrl) ICH/ISA bridge ICH/IDE bridge ICH/SMBus Controller
0 0 0 0 0 0 0 0 0 0 0
1A 1A 1C 1C 1C 1D 1D 1E 1F 1F 1F
0,1 7 0 4 5 0,1 7 0 0 2 3
8086 8086 8086 8086 8086 8086 8086 8086 8086 8086 8086
2937-8 293C 2940 2948 294A 2934-5 293A 244E 2918 2921 2930
1028 1028
0235 0235
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Device #
Func #
Vendor ID
SID
0235 0235 1F0C
+The PCI bus number will be higher if there are PCI bridged adapters on the lower numbered PCI busses.
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Vend ID
Dev ID
SVID
SID
Dev#
Fun#
Vendor IDs:
1000 LSI Logic 1233 BTI 1014 IBM 12D8 Pericom 101A - NCR 1B3E Teradata 111D Integrated Device Tech 8086 Intel
Legend:
W PCI width F PCI frequency K PCI key CLS Cache line size LxH Board length & height SVID Subsystem Vendor ID SID Subsystem ID Dev - Device Fun - Function
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The chipset supports emulated INTx type interrupts for legacy support which will be used by any PCI device that do not have MSI/MSI-X enabled See the INTx Interrupt Routing chart a couple of charts later
> PCIe devices that use INTx type interrupts would generate Assert INTx messages over the PCIe bus > In the node, Assert INTx messages are routed to either the I/OxAPIC in the ICH9 chip or the I/O APIC in the IOH chip depending upon if the I/OxAPIC in the IOH chip is disabled or enabled (by BIOS) It should be enabled! > ORing of some Assert INTx messages may occur in the I/OxAPIC in the IOH (see INTx Interrupt Routing chart)
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When Assert INTA rotates it become Assert INTB or Assert INTC or Assert INTD depending on the rotation amount
Similar rotation is followed by Assert INTB, Assert INTC and Assert INTD. Rotation past INTD goes back to INTA INTx rotation occurs in PCI bridges and follow the rotation rules established in the PCI Bridge specification. PCIe switches are represented as 2 levels of bridges and follow the same rules The amount of INTx rotation depends on the device # of the device on the secondary bus of the PCI bridge
> > > > INTx INTx INTx INTx for for for for devices devices devices devices 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, etc. do not rotate (INTA INTA) etc. rotate by 1 (INTA INTB) etc. rotate by 2 (INTA INTC) etc. rotate by 3 (INTA INTD)
INTx rotation may occur on every PCIe switch on the interrupt path from the originating device to the I/OxAPIC (switches are found within the adapters themselves)
23 > November 09, 2009 Teradata Confidential 2580 Node 007-0008216 C
PCI 1
(PCIe x4)
Enet
1 3 4
PCI 2
(PCIe x4)
Enet
PCI 3
(PCIe x4)
SAS
PCI 5+
(PCIe x4)
1 2 3 4
Top
* * *
PCI 4
(PCIe x8)
Bottom
PCI 7+
(PCIe x8)
Top
PCI 6+
(PCIe x8)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Tylersburg IOH
QPI
IOxAPIC 9 MSI messages to the CPUs
Bottom
ICH9
PCI 9+
(32/33)
VGA
PCI 0
15
A B C D E F G H
Emulated INTx: The Assert INTx messages from PCI devices that do not have MSI/MSI-X enabled go to the IOxAPIC in the Tylersburg IOH. Note that the Assert INTx message can get rotated on the I/O Riser switch on the way to the I/OxAPIC as illustrated above. *If the PCI adapter has an internal PCIe switch, the Assert INTx messages can also get rotated in the adapter switch before leaving the adapter.
24 > November 09, 2009 Teradata Confidential
Description Processor interrupt NMI to processor In APIC mode, 8259 cascade Keyboard In APIC mode, Timer
Real Time Clock (RTC) SCI, TCO, boot interrupt SCI, TCO SCI, TCO Mouse FERR# Logic
SIO3
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