C:\Users\William\Documents\School\Spring 2014\ECEN 442\Labs\Lab 7\Main.

Wednesday, April 16, 2014 12:42 PM

#include "DSP28x_Project.h" // Device Headerfile and Examples Include File //Timer Period for 20kHz #define EPWM_TIMER_TBPRD 2999; interrupt void adcint1_isr(void); void InitEPwm4(void); void InitEPwm6(void); //Initial Duty Cycle int16 duty_cycle = 100; int16 dac0 = 200; int16 dac1 = 200; volatile Uint32 speed = 0; long Result = 0; volatile volatile volatile volatile volatile volatile volatile int32 int32 int32 int32 int32 int32 int16 speed_ref=600; speed_error=0; integral=0; ki=8; kp=0; control=0; speed_scaler = 600;

void main() { InitSysCtrl(); DINT; InitPieCtrl(); InitAdc(); IER = 0x0000; IFR = 0x0000; InitPieVectTable(); //########################################################################### // User specific code: //########################################################################### EALLOW; //Mux GPIO6,GPIO10,GPIO11 to PWM pins GpioCtrlRegs.GPAMUX1.bit.GPIO6 = 1; GpioCtrlRegs.GPAMUX1.bit.GPIO10 = 1; GpioCtrlRegs.GPAMUX1.bit.GPIO11 = 1; //GPIO 7 set as output and low GpioCtrlRegs.GPAMUX1.bit.GPIO7 = 0; GpioCtrlRegs.GPADIR.bit.GPIO7 = 1; GpioDataRegs.GPACLEAR.bit.GPIO7 = 1; //MUX EQEP GpioCtrlRegs.GPAMUX2.bit.GPIO20 = 1; GpioCtrlRegs.GPAMUX2.bit.GPIO21 = 1;
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C:\Users\William\Documents\School\Spring 2014\ECEN 442\Labs\Lab 7\Main.c

Wednesday, April 16, 2014 12:42 PM

GpioCtrlRegs.GPAMUX2.bit.GPIO23 = 1; //Set up CpuTimer0 for 15 to 60 ms CpuTimer0Regs.PRD.all = 0x000DBB9F; CpuTimer0Regs.TCR.bit.TSS = 1; CpuTimer0Regs.TCR.bit.TRB = 1; CpuTimer0Regs.TCR.bit.TSS = 0; CpuTimer0Regs.TCR.bit.TIE = 1; // Set up ADC Channel, SOC trigger and acquisition period AdcRegs.ADCSOC0CTL.bit.CHSEL = 0x0; AdcRegs.ADCSOC0CTL.bit.TRIGSEL = 0x01; AdcRegs.ADCSOC0CTL.bit.ACQPS = 0x3F; //Set up continuous Update and enable EOC interrupt AdcRegs.INTSEL1N2.bit.INT1CONT = 1; AdcRegs.INTSEL1N2.bit.INT1E = 1; AdcRegs.INTSEL1N2.bit.INT1SEL = 0x00; //set up custom interupt handling PieVectTable.ADCINT1 = &adcint1_isr; PieCtrlRegs.PIECTRL.bit.ENPIE = 1; PieCtrlRegs.PIEIER1.bit.INTx1 = 1; IER |= M_INT1; //Set up EQEP EQep1Regs.QDECCTL.bit.QSRC=0; EQep1Regs.QEPCTL.bit.PCRM=1; EQep1Regs.QPOSMAX=0xFFFFFFFF; EQep1Regs.QEPCTL.bit.QPEN=1; // Enable the PIE block // Enable PIE Group 1 INT1 (for SOC0) // Enable CPU INT1 includes SOC0

// // // //

QEP quadrature count mode QPOSCNT reset on maximum Maximum value of QPOSCNT QEP enable

//Disable EPWM CLK to syncronize clks SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0; EDIS; InitEPwm4(); InitEPwm6(); //Enable EPWM clk EALLOW; SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1; EDIS; EINT; for(;;){ dac0 = speed; dac1 = speed_ref; duty_cycle = control; EPwm6Regs.CMPA.half.CMPA = dac0; EPwm6Regs.CMPB = dac1; EPwm4Regs.CMPA.half.CMPA = duty_cycle;
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C:\Users\William\Documents\School\Spring 2014\ECEN 442\Labs\Lab 7\Main.c

Wednesday, April 16, 2014 12:42 PM

} } //###################### End of main code ####################### interrupt void adcint1_isr(void) { //Save adc result back to Result variable Result = AdcResult.ADCRESULT0; PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; speed_ref = speed_scaler * (AdcResult.ADCRESULT0/1024); // Speed reference speed = (EQep1Regs.QPOSCNT*67*60)/4000; EQep1Regs.QPOSCNT = 0; speed_error = speed_ref-speed; // Speed error calculation integral = integral+speed_error/ki; // Controller integrator if(integral < 0){ integral = 0; } if(integral > 2999 ){ integral = EPWM_TIMER_TBPRD; } control = speed_error*kp + integral; //Controller proportional + integrator } void InitEPwm4() { // Setup TBCLK EPwm4Regs.TBCTL.bit.CTRMODE = 0; EPwm4Regs.TBPRD = EPWM_TIMER_TBPRD; EPwm4Regs.TBCTL.bit.HSPCLKDIV = 0; EPwm4Regs.TBCTL.bit.CLKDIV = 0; // Setup shadow register load on EPwm4Regs.CMPCTL.bit.SHDWAMODE = EPwm4Regs.CMPCTL.bit.SHDWBMODE = EPwm4Regs.CMPCTL.bit.LOADAMODE = EPwm4Regs.CMPCTL.bit.LOADBMODE =

// Count up // Set timer period // Clock ratio to SYSCLKOUT

ZERO CC_SHADOW; CC_SHADOW; CC_CTR_ZERO; CC_CTR_ZERO;

// Set Compare values,Compare B is not used EPwm4Regs.CMPA.half.CMPA = duty_cycle; // Set actions EPwm4Regs.AQCTLA.bit.ZRO = AQ_SET; EPwm4Regs.AQCTLA.bit.CAU = AQ_CLEAR; } void InitEPwm6() { // Setup TBCLK EPwm6Regs.TBCTL.bit.CTRMODE = 0; EPwm6Regs.TBPRD = EPWM_TIMER_TBPRD; EPwm6Regs.TBCTL.bit.HSPCLKDIV = 0; EPwm6Regs.TBCTL.bit.CLKDIV = 0;

// Set compare A value

// Set PWM4A pin on Zero // Clear PWM4A pin on event A, up count

// Count up // Set timer period // Clock ratio to SYSCLKOUT

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C:\Users\William\Documents\School\Spring 2014\ECEN 442\Labs\Lab 7\Main.c

Wednesday, April 16, 2014 12:42 PM

// Setup shadow register load on EPwm6Regs.CMPCTL.bit.SHDWAMODE = EPwm6Regs.CMPCTL.bit.SHDWBMODE = EPwm6Regs.CMPCTL.bit.LOADAMODE = EPwm6Regs.CMPCTL.bit.LOADBMODE = // Set Compare values EPwm6Regs.CMPA.half.CMPA = dac0; EPwm6Regs.CMPB = dac1; // Set actions EPwm6Regs.AQCTLA.bit.ZRO EPwm6Regs.AQCTLA.bit.CAU EPwm6Regs.AQCTLB.bit.ZRO EPwm6Regs.AQCTLB.bit.CBU }

ZERO CC_SHADOW; CC_SHADOW; CC_CTR_ZERO; CC_CTR_ZERO;

// Set compare A value // Set compare B value

= = = =

AQ_SET; AQ_CLEAR; AQ_SET; AQ_CLEAR;

// // // //

Set PWM7B pin on Zero Clear PWM1A pin on event B, up count Set PWM7B pin on Zero Clear PWM1A pin on event B, up count

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