Design Experiments for

Measurement and Modeling

of Digital Substrate Noise
Generation
Marc van Heijningen
John Compiet
Piet Wambacq
Stephane Donnay

© IMEC 2000
IMEC, Belgium
1
 Project partners

IWT project FRONTENDS ESPRIT project BANDIT

- Alcatel Microelectronics - IMEC

- K.U. Leuven - K.U. Leuven
- IMEC - Ericsson Radio Systems

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 Outline

• Motivation

• Introduction Substrate Noise Generation

• low-level (SPICE) modeling and measurements

• Conclusions

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 Goal: simulate substrate noise
generation of large digital circuits

generation
propagation impact

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 Approach:

• Find simple but accurate SPICE substrate models

for digital standard cells
• Very the SPICE substrate noise simulations with
measurements
• Develop a high-level substrate noise simulation
methodology, based on the SPICE models

• At first, for low-ohmic epi-type substrates

(Alcatel Microelectronics 0.5 um CMOS)

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 Outline

• Motivation

• Introduction Substrate Noise Generation

• low-level (SPICE) modeling and measurements

• Conclusions

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 Two sources of substrate noise:
switching gates and the power supply

digital analog
Vdd Vdd

Vss Vss

2
1
2

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 External parasitics create power supply
noise

package
bondwire
IC
trace

pin
L R L,R,C L R
1 Ghz => Z = 75 ohm
4 nH 0.01 ohm 4 nH 4 nH 0.1 ohm
1 ohm
2 pF
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 Dominant noise source is determined by
the external parasitics
Vsub_pp[mV]
1000
noise coupling from noise coupling from
MOSFETs is dominant power supply is dominant

100

total generated
substrate noise

10
only MOSFET noise
only power supply
noise coupling

1
1 pH 10 pH 100 pH 1 nH 10 nH
inductance in power supply connection

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 Substrate noise versus package parasitics
Wirebond and Flipchip implementation

W
Log(Vsub,rms)

Log(R)
Log(L)
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 Outline

• Motivation

• Introduction Substrate Noise Generation

• low-level (SPICE) modeling and measurements

• Conclusions

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 Epi-type substrate can be approximated
by one electrical substrate bulk node

p- epi 10 Ùcm 4 ìm

epi type substrate

low-ohmic bulk
500 ì m ↓
1 electrical node
p+ bulk 0.01 Ùcm

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 Low-level (SPICE) substrate model

in
Vss Vdd
out

p+ n+ n+ p+ p+ n+

p-well n-well

p- epi

p+ bulk

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 Active substrate noise sensor to directly
measure the substrate voltage

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 Transfer function of the noise sensor

peaking due to parasitics

amplification [dB] in measurement setup
10
measurement
5 simulation

-5

-10

-15

-20
3 4 5 6 7 8 9 10
10 10 10 10 10 10 10 10
frequency [Hz]
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 Experimental ASICs to verify the low-
level SPICE substrate models
AuE 0.5um CMOS, 3.3 V AuE 0.5um CMOS, 3.3V
test chip with noise generators 86kgate ASIC

DIGITAL MULTIRATE
UP/DOWN CONVERTER
power region 1

power region 2

ANALOG DIGITAL
NOISE NOISE ANALOG
SENSORS GENERATORS NOISE SENSORS
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 Clocked ring oscillator used for substrate
noise generation

7x
D Q

CLK

4 or 6 x 4 or 6 x 4 or 6 x

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 Dominant substrate noise source
determines the noise waveform
Noise coupling from source/drain nodes
Vsub [mV]
6

-6
0 10 20 30
time [ns]
Noise coupling from the on-chip power/ground
Vsub [mV]
50

-50
0 10 20 30
time [ns]

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 Good agreement between measured
and simulated substrate noise
Vsub [mV]
25
measurement
SPICE
20

15

10

-5

-10

-15
0 5 10 15 20 25 30
time [ns]
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 >80% of noise power is generated by
simultaneous switching of core cells
Vsub [mV]
40

20

-20
core output
switching switching

-40
20 20.1 20.2 20.3 20.4 20.5
time [us]
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 Substrate noise power scales as CMOS
power consumption : Vsub2 ~ f Vdd2

Vsub [mVrms] at Vdd=3.3V Vsub [mVrms] at Fclk = 50 MHz

25
100
linear

20
slope 0.5

10 15

10

1 5
0.1 1 10 100 2 2.5 3 3.5 4 4.5
Fclk [MHz] Vdd [V]

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 Frequency spectrum of generated
substrate noise

MOSFETs power supply

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 Increase of substrate noise at clock
multiples and due to ringing
Vsub [dBV]

data input clock data output clock

-40

+40 dB
at clock
multiples -60

+20 dB
-80
from
ringing

-100

0 50 100 150 200

Freq [MHz]
ringing
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 Conclusions from the measurements

• in most practical cases, substrate noise is caused by

power supply noise coupling

• simultaneous switching of core cells (mostly flip-

flops) generate more noise than IO buffers

• ringing of the power supply will increase the

substrate noise

• in the frequency domain, substrate noise is concen-

trated at multiples of the digital clock frequency, with
peaks up to 40 dB above the substrate noise floor
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 Conclusions on modeling

• when modeling and simulating substrate noise gene-

ration all noise sources should be taken into account:
• switching gates
• power supply noise
• package parasitics

• for epi-type substrates a simple SPICE substrate

model can be used

© IMEC 2000
 Related work and References
• Related work: High-level modeling and simulation of
digital substrate noise generation
• BANDIT project (see HTTP://www.imec.be/bandit/)
• References:
• M. van Heijningen, J. Compiet, P. Wambacq, S. Donnay, M. Engels, and I. Bolsens, "Analysis and
Experimental Verification of Digital Substrate Noise Generation for Epi-Type Substrates," IEEE J.
Solid-State Circuits, vol. 35, pp. 1002-1008, July 2000.
• M. van Heijningen, M. Badaroglu, S. Donnay, M. Engels, and I. Bolsens, "High-Level Simulation of
Substrate Noise Generation Including Power Supply Noise Coupling," in Proc. 37nd Design
Automation Conference, pp. 446-451, 2000.
• Y. Rolain, W. van Moer, G. Vandersteen, and M. van Heijningen, "Measuring mixed signal substrate
coupling," in Proc. IMTC'2000, Baltimore, May, 2000.
• M. van Heijningen, J. Compiet, P. Wambacq, S. Donnay, M. Engels, and I. Bolsens, "Modeling of
Digital Substrate Noise Generation and Experimental Verification Using a Novel Substrate Noise
Sensor," in Proceedings of the ESSCIRC, pp. 186-189, 1999.
• M. van Heijningen, J. Compiet, P. Wambacq, S. Donnay, and I. Bolsens, "A Design Experiment for
Measurement of the Spectral Content of Substrate Noise in Mixed-Signal Integrated Circuits," in
Proc. 1999 Southwest Symposium on Mixed-Signal Design, April 11-13, Tucson AZ, USA, pp. 27-32,
1999.

© IMEC 2000