org 00h

rd1 bit p2.5

wr1 bit p2.6
intr bit p2.7
back:mov p1,#0ffh
setb intr
clr wr1
setb wr1
test:jb intr,test
clr rd1
acall bin_to_dec
acall dec_to_ascii
acall data_disp
setb rd1
sjmp back
bin_to_dec:mov r0,#40h
mov a,p1
mov b,#10
div ab
mov @r0,b
inc r0
mov b,#10
div ab
mov @r0,b
inc r0
mov @r0,a
ret
dec_to_ascii:mov r0,#40h
mov r1,#50h
mov r2,#3
bck:mov a,@r0
orl a,#30h
mov @r1,a
inc r0
inc r1
djnz r2,bck
ret
data_disp:mov p3,#38h
acall cmdwrt
acall delay
mov p3,#0eh
acall cmdwrt
acall delay
mov p3,#06h
acall cmdwrt
acall delay
mov p3,#80h
acall cmdwrt
acall delay
mov r1,#52h
mov r2,#3
loop:mov a,@r1
acall datawrt
acall delay
dec r1
clr a
djnz r2,loop
ret
cmdwrt:clr p2.0
clr p2.1
setb p2.2
acall delay
clr p2.2
ret
datawrt:mov p3,a
setb p2.0
clr p2.1
setb p2.2
acall delay
clr p2.2
ret
delay:mov r3,#50
h2:mov r4,#0ffh
h1:djnz r4,h1
djnz r3,h2
ret
end