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‡ 16-bit Arithmetic Logic Unit

‡ 16-bit data bus (8088 has 8-bit data bus)

‡ 20-bit address bus - 220 = 1,048,576 = 1 meg

The address refers to a byte in memory. In the 8088, these bytes come in on
the 8-bit data bus. In the 8086, bytes at even addresses come in on the low
half of the data bus (bits 0-7) and bytes at odd addresses come in on the upper
half of the data bus (bits 8-15).

The 8086 can read a 16-bit word at an even address in one operation and at an
odd address in two operations. The 8088 needs two operations in either case.

The least significant byte of a word on an 8086 family microprocessor is at the

lower address.
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‡ The 8086 has two parts, the Bus Interface Unit (BIU) and the
Execution Unit (EU).

‡ The BIU fetches instructions, reads and writes data, and computes the
20-bit address.

‡ The EU decodes and executes the instructions using the 16-bit ALU.

‡ The BIU contains the following registers:

IP - the Instruction Pointer

CS - the Code Segment Register
DS - the Data Segment Register
SS - the Stack Segment Register
ES - the Extra Segment Register

The BIU fetches instructions using the CS and IP, written CS:IP, to contract
the 20-bit address. Data is fetched using a segment register (usually the DS)
and an effective address (EA) computed by the EU depending on the
addressing mode.
The EU contains the following 16-bit registers:

AX - the Accumulator
BX - the Base Register
CX - the Count Register
DX - the Data Register
SP - the Stack Pointer \ defaults to stack segment
BP - the Base Pointer /
SI - the Source Index Register
DI - the Destination Register

These are referred to as general-purpose registers, although, as seen by

their names, they often have a special-purpose use for some instructions.

The AX, BX, CX, and DX registers can be considers as two 8-bit registers, a
High byte and a Low byte. This allows byte operations and compatibility with
the previous generation of 8-bit processors, the 8080 and 8085. 8085 source
code could be translated in 8086 code and assembled. The 8-bit registers are:

AX --> AH,AL
BX --> BH,BL
CX --> CH,CL
DX --> DH,DL
„  
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ES Extra Segment
BIU registers
(20 bit adder) CS Code Segment
SS Stack Segment
DS Data Segment
IP Instruction Pointer

EU registers AX AH AL Accumulator
BX BH BL Base Register
CX CH CL Count Register
DX DH DL Data Register
SP Stack Pointer
BP Base Pointer
SI Source Index Register
DI Destination Index Register
FLAGS
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0FFFFFH

Absolute Address

The offset is the distance in bytes from the start of the segment.
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Data is usually fetched with respect to the DS register.

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The EA depends on the addressing mode.
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Physical Address 0A100H

The offset is given by the SP register.

The stack is always referenced with respect to the stack segment register.
The stack grows toward decreasing memory locations.
The SP points to the last or top item on the stack.

PUSH - pre-decrement the SP

POP - post-increment the SP
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The IB? PC is a maximum mode 8088 system. When an 8086/8088 is used
in the maximum mode (?/?X pin grounded) it requires the use of an 8288
Bus Controller. The system can support multiple processors on the system
bus by the use of an 8289 Bus Arbiter.

The following signals now come from the 8288: ALE, DT/R¶, DE, and ITA¶.

The ?/IO¶, RD¶, and WR¶ signals are replaced by:

?RDC¶ - memory read command

?WTC¶ - memory write command
IORC¶ - I/O read command
IOWC¶ - I/O write command
A?WC¶ - Advanced memory write command
AIOWC¶ - Advanced I/O write command

The advanced commands become active earlier in the cycle to give devices
an earlier indication of a write operation.

IV-1
 | |
9   
When in the maximum mode, the 8086/8088 has 3 status lines that are
connected to the 8288 and provide it with the information it needs to
generate the system bus signals. The information provided by the status
bits is as follows.

S2¶ S1¶ S0¶ operation signal

0 0 0 Interrupt Acknowledge ITA¶
0 0 1 Read I/O port IORC¶
0 1 0 Write I/O port IOWC¶, AIOWC¶
0 1 1 Halt none
1 0 0 Instruction Fetch ?RDC¶
1 0 1 Read ?emory ?RDC¶
1 1 0 Write ?emory ?WTC¶, A?WC¶
1 1 1 Passive none

IV-2
 0 § ( 0§
D?A allows data to go between memory and a peripheral, such as a disk
drive, without going through the cpu.

The D?A controller takes over the address bus, data bus, and control bus.
The 8237A D?A Controller is a commonly used device and is in the IB? PC.

Figure 11-4 is a simplified block diagram showing the use of a D?A controller.
For example, to read a disk file the following operations occur.

1. Send a series of commands to the disk controller to find and read a

block of data.
2. When the controller has the first byte of the block, it sends a D?A
request DREQ to the D?A controller.
3. If that input of the D?A controller is unmasked, the D?A controller
sends a hold-request HQR to the cpu.
4. The cpu responds with a hold-acknowledge HLDA and floats its buses.
5. The D?A controller then takes control of the buses.
6. The D?A controller sends out the memory address and D?A
acknowledge DACK0 to the disk controller.
7. The D?A controller asserts the ?E?W¶ and IOR¶ lines.

IV-4
  
Terminology
Volatile - data is lost when power is turned off.
onvolatile - retains data when powered off.

Random Access - all data locations accessed in the same amount of time.
Sequential Access - data accessed in varying amounts of time, e.g., tape.

RO? - Read Only ?emory.

RA? - Random Access ?emory

By convention, RA? in a PC is really Read/Write ?emory and RO?

(EPRO?) in a PC, although random access memory, is not referred to
as RA?.

Examples
VOLATILE OVOLATILE
Static RA? RO?, PRO?, EPRO?, EEPRO?, FLASH
Dynamic RA? Disk, tape
?agnetic core, magnetic bubble

IV-6

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