TOPIC:-INTERFACING OF 8255 AND 8085

PREPARED BY :-GANDHI KUNJ

DEPARTMENT :-CP
ENROLLMENT NO:-170010107014
SUBJECT :-MICROPROCESSOR AND
INTERFACING
INTERFACING MEMORY CHIPS
WITH 8085
Interfacing is a technique through which two separate components
of a computer system exchange information or interact with each
other.
Interfacing a microprocessor is to connect the microprocessor to
various peripherals to perform operations to obtain output.
 Two types of interfacing can be done with the 8085 microprocessor
- Memory interfacing
-I/O interfacing
INTERFACING MEMORY CHIPS
WITH 8085
 8085 has 16 address lines
 Hence, 216 = 64KB of memory locations can be interfaced with it.
 The memory address ranges from 0000H to FFFFH.
 Control Signals for memory

When is IO/ M high, both memory control signals are deactivated irrespective
of the status of RDand WRsignals.
INTERFACEAN IC 2764 WITH 8085 USING NAND GATEADDRESS DECODERSUCH THAT THE
ADDRESS RANGE ALLOCATED TO THE CHIP IS 0000H – 1FFFH.

 Specification of IC 2764:
8 KB(8 x 2 ^ 10 byte) EPROM chip
13 address lines (2 ^ 13 bytes = 8 KB)
Interfacing:
13 address lines of IC are connected to the corresponding address lines of 8085.
Remaining address lines of 8085 are connected to address decoder formed using logicgates, the
output of which is connected to the CEpin of IC.
 Address range allocated to thechip is shown in Table.
Chip is enabled whenever the 8085 places an address allocated to EPROMchip in the addressbus.
This is shown in Fig..
 TABLEADDRESSALLOCATEDTOIC2764

INTERFACING IC 2764 WITH THE8085

 INTERFACE A 6264 IC (8K X 8 RAM) WITH THE8085 USING NAND GATE DECODER
SUCHTHAT THE STARTING ADDRESS ASSIGNEDTO THE CHIP IS4000H.

 Specification of IC 6264:
8K x 8 RAM
8 KB= 2 ^ 13 bytes
13 address lines
The ending address of the chip is 5FFFH (since 4000H + 1FFFH =5FFFH).
When the address 4000H to 5FFFH are written in binary form, the values in the lines A15, A14, A13 are
0, 1 and 0 respectively.
 The NAND gate is designed such that when the lines A15 and A13 carry 0 and A14 carries 1, the output
of the NAND gate is0.
 The NAND gate output is in turn connected to the pin of the RAM chip.
A NAND output of 0 selects the RAM chip for read or write operation, since CE2is already 1because of
its connection to +5V. Fig. shows the interfacing of IC 6264 with the 8085.
INTERFACING 6264 IC WITH THE8085
INTERFACETWO 6116 ICSWITH THE8085 USING74LS138DECODERSUCH THATTHE
STARTINGADDRESSESASSIGNEDTOTHEM ARE8000H AND 9000H, RESPECTIVELY.
 Specification of IC 6116:
2 Kx 8 RAM
2 KB= 2 ^ 11 bytes
11 address lines
A0 – A10 lines of 8085 are connected to 11 address lines of the RAM chips.
Three address lines of 8085 having specific value for a particular RAM are connected to the
three select inputs (C, Band A) of 74LS138decoder.
Table shows that A13=A12=A11=0 for the address assigned to RAM 1 and A13=0, A12=1and
A11=0 for the address assigned to RAM2.
Remaining lines of 8085 which are constant for the address range assigned to the two RAM are
connected to the enable inputs of decoder.
When 8085 places any address between 8000H and 87FFH in the address bus, the selectinputs
C, B and A of the decoder are all 0. The Y0 output of the decoder is also 0, selecting RAM1.
When 8085 places any address between 9000H and 97FFH in the address bus, the selectinputs
C, B and A of the decoder are 0, 1 and 0. The Y2 output of the decoder is also 0, selecting RAM2.
MEMORY MAPPED I/O
INTERFACING
 8085 uses its 16 bit address bus to identify a memory location.
 Memory address space : 0000H to FFFFH
 8085 needs to identify I/O devices also.
 I/O device can be interfaced using addresses from memory space .
 8085 treats such an I/O device as a memory location.
 This is called Memory mapped I/O.
MEMORY MAPPED I/O
INTERFACING
Memory mapped i/o instruction:
 i/o device are identified by 16 bit addresses .
8085 communicates with an i/o device as if it were one of the memory
location memory related instruction areuse
 Ex: LDA,STA
LDA8000H= load A with data read from input device with16 bit
address 8000H
STA8001H= store contents of Ato output device with 16 bit address
8001H
 INTERFACING 8-BIT DIP
SWITCH WITH8085

 address lines are connected to AND

gates.
 output of these gates along with MEMR
 signal are connected to a NANDgate,
 when the address F0F0H is placed in the
 address bus and MEMR = 0 its output
becomes 0; enables the buffer 74LS244.
 data from the DIP switch is placed in
the 8085 data bus.
 8085 reads the data from thedata bus
and stores it in theaccumulator.
Programmable Peripheral
Interface

Support chips: 8155, 8255,

8279,8254,8257, 8259,8251
ProgrammableInterface
Devices
 used to interface a I/O device to
the microprocessor
System Bus Programmable
I/O I/O
8085 Devices
Interface

 Can be programmed/configured to
perform various I/O functions by
writing software instructions
 PROGRAMMABLE PERIPHERAL
INTERFACE DEVICE
 Designed to be compatible with 8085
 It consists of
 Three I/O ports
 Port A
 Port B
 Port C
 Port C can be used as two 4-bit ports
 PCu (Port C upper 4 bits)
 PCl (Port C lower 4 bits)
 I/O Interfacing using 8255

Port A

System Temperature
8-bit
Bus
Port C u Sensor
ADC
8085 8255
Port Cl
LED
Port B DISPLAY
Interfacing with Analog-to-Digital
Converter

Port A

System Temperature
Bus SOC Sensor
8-bit
8085 8255 ADC
EOC

OE

Port C
lines
APPLICATION PROGRAMMING LOGIC

 Configure 8255 I/O ports

 8085 sends SOC command to ADC
 8085 waits for EOC signal from ADC
 8085 sends OE command to ADC
 8085 reads 8-bit temperature value
from port A
 8085 displays temperature value on
LED display connected to port B
 1. Configure 8255 I/O PORTS

Port A

System Temperature
8-bit
Bus
Port C u Sensor
ADC
8085 8255
Port Cl
LED
Port B DISPLAY
 Port A as INPUT port
 Port B as OUTPUT port
 Port C (PCu – O/P , PCl – I/P )
 SOC (PC4) is a OUTUT line
 EOC (PC0) is a INPUT line
 OE (PC7) is a OUTPUT line
 Know more about
 Modes of operation of 8255
 Control word format of 8255
Modes of Operation of 8255
 Two primary modes of operation
1.Parallel I/O mode
 Mode 0 (Simple Input/Output)
 Mode 1 (Input/Output with Handshake)
 Mode 2 (Bidirectional data transfer)
2.Bit Set/Reset Mode This
 application uses
 Parallel I/O mode - Mode 0
 Bit Set/Reset mode
Control Word for 8255
 8255 has a 8-bit Control word
register
 8255 ports can be configured for
operation by writing a appropriate
control word in it
for Parallel I/O

1
0
0

91H
0
1
0
0
1
for Bit Set/Reset Mode
ApplicationProgramming
 Configure 8255 I/O ports
MVI A, 91H
OUT CWR
 Writing value 91H in Control Word
Register of 8255
 CWR represents the 8-bit port
address of Control Word Register
Application Programming
 8085 sends SOC (PC4=1)command
to ADC
MVI A, 00001001B
OUT CWR
 Uses Bit Set/Reset mode of
8255
ApplicationProgramming
 8085 waits for EOC signal from ADC
WAIT: IN PORTC
RAR
JC WAIT
 EOC is taken to be active low
ApplicationProgramming
 8085 sends OE command to ADC
MVI A, 00001111H
OUT PORTC
 8085 reads 8-bit temperature value
from port A
IN PORTA
MOV B, A
ApplicationProgramming
 8085 displays temperature value on
LED display connected to port B
OUT PORTB
Pin diagram of 8255
D7 – D0 Data Bus
PA7 – PA0 Port A
PB7 – PB0 Port B
PC7 – PC0 Port C
CS Chip Select
A0, A1 Address bits
RD Read Input
WR Write Input
RESET Reset Input
Vcc +5V
GND 0 Volts
Interfacing 8255 with 8085
 8255 can be interfaced to 8085 using
 Memory-mapped I/O
 Peripheral-mapped I/O
 As application program uses
IN/OUT instructions
 Peripheral-mapping is used
 8-bit addresses are used for ports
and control register of 8255
 For e.g.
 OUT CWR
 IN PORTA
 OUT PORTB
 In actual program, label CWR will
be substituted by 8-bit address of
Control Word Register of 8255
8255 Chip selection & Port Addresses

A7
A = 80H
A6
A5
CS B = 81H
A4
A3 8255 C = 82H
A2 A1 A0 Port
A1 A1 0 0 A
A0 A0 0 1 B
1 0 C
1 1 CWR
Programming with port address
 OUT CWR  OUT 83H
 IN PORTA  IN 80H
 OUT PORTB  OUT 81H
Block diagram of
8255
THANK YOU