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Peripheral Devices
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• The 8255A is a widely used, programmable, parallel I/O
device.
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• The 8255A has 24 I/O pins that can be grouped
primarily in two 8-bit parallel ports: A and B, with the
remaining eight bits as port C.
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8255A
• The I/O mode is further divided into three modes: Mode 0, Mode
1, and Mode 2.
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Block Diagram of the 8255A.
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Block diagram.
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Expanded version of the Control logic.
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Block diagram description.
• The block diagram shows two 8-bit ports (A and B), Two 4-bit
ports (CU and CL), The data bus buffer, and control logic.
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Control Logic
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• RESET (Reset): This is an active high signal; it
clears the control register and sets all ports in the
input mode.
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• The CS signal is the master chip select, and A0 and A1 specify
one of the I/O ports or the control register as given below:
CS A1 A0 Selected
0 0 0 port A
0 0 1 Port B
0 1 0 Port C
0 1 1 Control Register
1 x x 8255 is not selected.
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• The port addresses are determined by the CS, A0, and A1
lines.
• When these signals are combined with A0 and A1, the port
addresses range from 80H to 83H.
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8255 Chip select Logic & I/O port address.
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Control word
• The contents of Control register, called the control word, specify an
I/O function for each port.
• Bit D7 of the control register specifies either the I/O function or the
Bit Set/Reset function.
• The BSR control word does not affect the functions of ports A and
B.
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• To communicate with peripherals through the 8255A, three
steps are necessary:
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Mode 0: Simple Input or Output
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Example
l. Identify the port addresses
in Figure shown.
2. Identify the Mode 0 control
word to configure port A
and port CU as output ports
and port B and port CL, as
input ports.
3. Write a program to read the
DIP switches and display
the reading from port B at
port A and from port CL at
port CU.
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Solution:
l. Port Addresses
• This is a memory-mapped l/O; when the address line A15 is
high, the Chip Select line is enabled. Assuming all don't care
lines are at logic 0, the port addresses are as follows:
Port A = 8000H (A1 = 0, A0, = 0)
Port B = 8001H (A1 = 0, A0 = l)
Port C = 8002H (A1 = l, A0 = 0)
Control Register = 8003H (A1 =l, A0= l)
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Program:
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BSR (Bit Set/Reset) Mode:
• The BSR mode is concerned only with the eight bits of port C,
which can be set or reset by writing an appropriate control
word in the control register.
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BSR Control Word:
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Example:
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Solution: BSR CONTROL WORDS
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Port address:
• Control register address = 83 H;
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Subroutine:
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• From an analysis of the above routine, the following points
can be noted:
3. The BSR control word does not affect the I/O mode.
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Mode 1: Input or Output with
Handshake
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Mode 1: Input or Output with Handshake
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MODE 1: INPUT CONTROL SIGNALS:
• Port A uses the upper three signals: PC3 PC4, and PC5.
• Port B uses the lower three signals: PC2, PC1 and PC0.
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8255A Mode 1 : Input Configuration:
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• The functions of these signals are as follows:
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• INTR (Interrupt Request): This is an output signal that may be
used to interrupt the MPU. This signal is generated if STB,
IBF and INTE (Internal flip-flop) are all at logic 1. This is
reset by the falling edge of the RD signal.
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8255 Mode 1: Timing waveforms for Strobed
Input (With Handshake)
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CONTROL AND STATUS WORDS:
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MODE 1: OUTPUT CONTROL SIGNALS:
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• OBF {Output Buffer Full): This is an output signal that goes
low when the MPU writes data into the output latch of the
8255A, This signal indicates to an output peripheral that new
data are ready to be read. It goes high again after the 8255A
receives an ACK from the peripheral.
• ACK (Acknowledge): This is an input signal from a peripheral
that must output a low when the peripheral receives the data
from the 8255A ports.
• INTR (Interrupt Request): This is an output signal, and it is set
by the rising edge of the ACK signal. This signal can be used
to interrupt MPU to request the next data byte for output. The
INTR is set when OBF, ACK, and INTE are all one and reset
by the falling edge of WR.
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CONTROL AND STATUS WORD.
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Illustration: An Application of the 8255A in the
Handshake Mode (Mode 1)
• Figure shows an interfacing
circuit using the 8255A in
Mode l. Port A is designed
as the input port for a
keyboard with interrupt I/O,
and port B is designed as
the output port for a printer
with status check I/O.
1. Find port addresses by
analyzing the decode logic
2. Determine the control
word to set up port A as
input and port B as output
in Mode l.
3. Determine the BSR word
to enable INTEA (port A).
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l. Port Addresses: The 8255A is connected as peripheral I/O.
When the address lines A7-A2 are all l, the output of the
NAND gate -goes low and selects the 8255A. The individual
ports are selected as follows:
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3. BSR word to set INTEA:
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Mode – 2 operation of 8255A
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Bidirectional Data Transfer: