#TUTORIALSPOINT

Programmable peripheral interface 8255

PPI 8255 is a general purpose programmable I/O device designed to interface the CPU with its
outside world such as ADC, DAC, keyboard etc. We can program it according to the given
condition. It can be used with almost any microprocessor.
It consists of three 8-bit bidirectional I/O ports i.e. PORT A, PORT B and PORT C. We can assign
different ports as input or output functions.
Block diagram –

It consists of 40 pins and operates in +5V regulated power supply. Port C is further divided into
two 4-bit ports i.e. port C lower and port C upper and port C can work in either BSR (bit set rest)
mode or in mode 0 of input-output mode of 8255. Port B can work in either mode or in mode 1 of
input-output mode. Port A can work either in mode 0, mode 1 or mode 2 of input-output mode.
It has two control groups, control group A and control group B. Control group A consist of port A
and port C upper. Control group B consists of port C lower and port B.
Depending upon the value if CS’, A1 and A0 we can select different ports in different modes as
input-output function or BSR. This is done by writing a suitable word in control register (control
word D0-D7).

CS’ A1 A0 SELECTION ADDRESS

0 0 0 PORT A 80 H
 CS’ A1 A0 SELECTION ADDRESS

0 0 1 PORT B 81 H

0 1 0 PORT C 82 H

0 1 1 Control Register 83 H

1 X X No Seletion X

Pin diagram –

 PA0 – PA7 – Pins of port A

 PB0 – PB7 – Pins of port B
 PC0 – PC7 – Pins of port C
 D0 – D7 – Data pins for the transfer of data
 RESET – Reset input
 RD’ – Read input
 WR’ – Write input
 CS’ – Chip select
 A1 and A0 – Address pins
Operating modes –
1. Bit set reset (BSR) mode –
If MSB of control word (D7) is 0, PPI works in BSR mode. In this mode only port C bits are
used for set or reset.
2. Input-Outpt mode –
If MSB of control word (D7) is 1, PPI works in input-output mode. This is further divided into
three modes:

 Mode 0 –In this mode all the three ports (port A, B, C) can work as simple input function
or simple output function. In this mode there is no interrupt handling capacity.
 Mode 1 – Handshake I/O mode or strobbed I/O mode. In this mode either port A or port
B can work as simple input port or simple output port, and port C bits are used for
handshake signals before actual data transmission. It has interrupt handling capacity
and input and output are latched.
Example: A CPU wants to transfer data to a printer. In this case since speed of
processor is very fast as compared to relatively slow printer, so before actual data
transfer it will send handshake signals to the printer for synchronization of the speed of
the CPU and the peripherals.
  Mode 2 – Bi-directional data bus mode. In this mode only port A works, and port B can
work either in mode 0 or mode 1. 6 bits port C are used as handshake signals. It also
has interrupt handling capacity.

Let us first take a look at the pin diagram of Intel 8255A −

Now let us discuss the functional description of the pins in 8255A.

Data Bus Buffer

It is a tri-state 8-bit buffer, which is used to interface the microprocessor to the system data bus.
Data is transmitted or received by the buffer as per the instructions by the CPU. Control words and
status information is also transferred using this bus.

Read/Write Control Logic

This block is responsible for controlling the internal/external transfer of data/control/status word. It
accepts the input from the CPU address and control buses, and in turn issues command to both
the control groups.

CS
It stands for Chip Select. A LOW on this input selects the chip and enables the communication
between the 8255A and the CPU. It is connected to the decoded address, and A0 & A1 are
connected to the microprocessor address lines.
Their result depends on the following conditions −

CS A1 A0 Result

0 0 0 PORT A

0 0 1 PORT B

0 1 0 PORT C

0 1 1 Control Register
 1 X X No Selection

WR
It stands for write. This control signal enables the write operation. When this signal goes low, the
microprocessor writes into a selected I/O port or control register.

RESET
This is an active high signal. It clears the control register and sets all ports in the input mode.

RD
It stands for Read. This control signal enables the Read operation. When the signal is low, the
microprocessor reads the data from the selected I/O port of the 8255.

A0 and A1
These input signals work with RD, WR, and one of the control signal. Following is the table showing
their various signals with their result.

A1 A0 RD WR CS Result

0 0 0 1 0 Input Operation
PORT A → Data Bus

0 1 0 1 0 PORT B → Data Bus

1 0 0 1 0 PORT C → Data Bus

Output Operation
0 0 1 0 0
Data Bus → PORT A

0 1 1 0 0 Data Bus → PORT A

1 0 1 0 0 Data Bus → PORT B

1 1 1 0 0 Data Bus → PORT D

#GeeksforGeeks

Microprocessor | 8255 (programmable peripheral interface)

8255 is a popularly used parallel, programmable input-output device. It can be used to transfer
data under various condition from simple input-output to interrupt input-output. This is economical,
functional, flexible but is a little complex and general purpose i/o device that can be used with
almost any microprocessor.
8255 pin diagram –
It has 24 pins that can be grouped in two 8-bit parallel ports: A and B called Port A(PA) and Port
B(PB) with the remaining eight known as Port C(PC). Port C can be further divided into groups of
4-bits ports named Cupper(Cu) and Clower(Cl). There are 40 pins and operates in +5 regulated
power supply.

Modes of 8255 – It works in two modes:

1. Bit set reset (BSR) mode
2. Input/output (I/O) mode
To know in which mode the interface is working we need to know the value of Control word.
Control word is a part of control register in 8255 which specify an I/O function for each port. This is
format of control word 8255.
If the most significant bit of control word or D7 is 1 then 8255 works in I/O mode else, if it’s value is
0 it works in BSR mode.
1. BSR Mode – When MSB of the control register is zero(0), 8255 works in Bit Set-Reset
mode.in this only PC bit are used for set and reset.
2. I/O Mode – When MSB of the control register is one(1), 8255 works in Input-Output mode.it is
further divided into three categories.
3. Mode 0 – In this mode all three ports (PA, PB, PC) can work as simple input function or
output function also in this mode there is no interrupt handling capabilities.
4. Mode 1 – In this either port A or port B can work and port C bits are used as Handshake
signal before actual data transmission plus it has interrupt handling capabilities.
5. Mode 2 – In this only port A works and port B can work either in Mode 0 or Mode 1 and the 6
bits of port C are used as Handshake signal plus it also has to interrupt handling capability.
To communicate with peripherals through 8255 three steps are necessary:
1. Determine the addresses of Port A, B, C and Control register according to Chip Select Logic
and the Address lines A0 and A1.
2. Write a control word in control register.
3. Write I/O intructions to communicate with peripherals through port A, B, C.
The common applications of 8255 are:
 Traffic light control
 Generating square wave
 Interfacing with DC motors and stepper motors
#Engineersgarage

8255 is general purpose programmable peripheral interface. It is used with many microprocessors and
microcontrollers for various purposes. The device has three 8-bit ports port A, port B and port C. These ports
can be used as input or output. These ports are further divided in to two groups A and B. Each group further
has ports. Group A is comprised of port A and port C upper nibbles (pins 7, 6, 5, 4) control. Group B contains
port B and port C lower nibble( 0, 1, 2, 3).

8255 PPI pin out

 Vcc Apply 5 volts to this pin.
 GND Ground this pin
 CS (chip select) A low on this selects the 8255.
Now you can use the chip.
 RD (read) A low on this pin indicates that we
want to read data from specified port of
8255.
 WR (write) A low on this pin indicates that we
want to write to 8255.
 RESET A high on this pin clear all registers and
ports.

8255A Pinout

A0 and A1
These both pins select the ports. Combination of high
and low level signal on these pins selects the ports A,
B and C. Not only these pins are used to select port
but also can write control word in device.
Control Word is an instruction or command send
to 8255 to set its ports or pins as input, output or
interrupt driven.
8255A Port selection Pins— A0 and A1

8255 Modes
There are three modes in which the device can be used.

 Mode-0
 Mode-1
 Mode-2

8255 PPI in Mode-0

In mode 0 each group can be used as input or output. Port A , port B and port C can be used as input or
output. Port C has the specialty that it can be divided in to two nibbles upper and lower. Both upper and
lower can now be programmed to use as input or output. Mode 0 is also known as input/output mode (I/O
mode). Question arises how we can do so. Yes it’s simple. Just send a control word to 8255 and it will set
itself according to your control word. The control word for mode 0 is like this.

8255 control word

D7 will always be high for mode 0. For selecting all ports as output the control word will be 0x80 in
hexadecimal, or 10000000 in binary.

8255a control word

In mode 0 you can also access individual bits of port C. For bit set reset mode D7 will always be 0.

8255 control word

8255 PPI in Mode-1
In mode 1 each group can be used as 8-bit input or output data bus and the remaining 4-bits are used as
handshaking and interrupt control signals. Port A is used with port c upper three bits and port B is used with
port c lower 3 bits. The remaining 2 bits of port C can be used as control signals. For more details on mode
1 download the data sheet released from Intel from the links below.

8255 Mode-2
Mode 2 is a bidirectional bus mode it is used very rarely. Mode 2 is used with port A only and port C is used
for interrupt and control signals only. For more details on mode 1 download the data sheet released from
Intel from the links below.

Microcontroller Projects Related to 8255A. Practical

Examples with Code.
 Increasing digital Input/Output Pins of Arduino Uno using 8255A.
 Interfacing 8255A with 89c51 microcontroller and Blinking Leds.

What is the purpose of 8255 PPI?

PPI 8255 is a general purpose programmable I/O device designed to
interface the CPU with its outside world such as ADC, DAC, keyboard
etc. We can program it according to the given condition. It can be used
with almost any microprocessor. It consists of three 8-bit bidirectional I/O
ports i.e. PORT A, PORT B and PORT C.
Why do we use 8255?
Microprocessor | 8255 (programmable peripheral interface) 8255 is a popularly used parallel,
programmable input-output device. It can be used to transfer data under various condition from
simple input-output to interrupt input-output.

Why 8255 Is resetted ?

The RESET input (pin 35) is connected to the RESET line of system like 8085, 8086,
etc., so that when the system is reset, all the ports are initialized as input lines. This is
done to prevent 8255 and/or any peripheral connected to it from being destroyed due to
mismatch of ports. As an example, consider an input device connected to 8255 at port
A. If from the previous operation, port A is initialized as an output port and if 8255 is not
reset before using the current configuration, then there is a possibility of damage of
either the input device connected or 8255 or both, since both 8255 and the device
connected will be sending out data.
The control register (or the control logic, or the command word register) is an 8-bit
register used to select the modes of operation and input/output designation of the
ports.[9]
Describe the types of interrupts in 8086

Interrupt is the method of creating a temporary halt during program execution and allows
peripheral devices to access the microprocessor. The microprocessor responds to that interrupt
with an ISR (Interrupt Service Routine), which is a short program to instruct the microprocessor on
how to handle the interrupt.
The following image shows the types of interrupts we have in a 8086 microprocessor −

Hardware Interrupts
Hardware interrupt is caused by any peripheral device by sending a signal through a specified pin
to the microprocessor.
The 8086 has two hardware interrupt pins, i.e. NMI and INTR. NMI is a non-maskable interrupt and
INTR is a maskable interrupt having lower priority. One more interrupt pin associated is INTA called
interrupt acknowledge.
NMI
It is a single non-maskable interrupt pin (NMI) having higher priority than the maskable interrupt
request pin (INTR)and it is of type 2 interrupt.
When this interrupt is activated, these actions take place −
 Completes the current instruction that is in progress.
 Pushes the Flag register values on to the stack.
 Pushes the CS (code segment) value and IP (instruction pointer) value of the return address on to the
stack.
 IP is loaded from the contents of the word location 00008H.
 CS is loaded from the contents of the next word location 0000AH.
 Interrupt flag and trap flag are reset to 0.
INTR
The INTR is a maskable interrupt because the microprocessor will be interrupted only if interrupts
are enabled using set interrupt flag instruction. It should not be enabled using clear interrupt Flag
instruction.
The INTR interrupt is activated by an I/O port. If the interrupt is enabled and NMI is disabled, then
the microprocessor first completes the current execution and sends ‘0’ on INTA pin twice. The first
‘0’ means INTA informs the external device to get ready and during the second ‘0’ the
microprocessor receives the 8 bit, say X, from the programmable interrupt controller.
These actions are taken by the microprocessor −
 First completes the current instruction.
 Activates INTA output and receives the interrupt type, say X.
 Flag register value, CS value of the return address and IP value of the return address are pushed on to
the stack.
 IP value is loaded from the contents of word location X × 4
 CS is loaded from the contents of the next word location.
 Interrupt flag and trap flag is reset to 0

Software Interrupts
Some instructions are inserted at the desired position into the program to create interrupts. These
interrupt instructions can be used to test the working of various interrupt handlers. It includes −
INT- Interrupt instruction with type number
It is 2-byte instruction. First byte provides the op-code and the second byte provides the interrupt
type number. There are 256 interrupt types under this group.
Its execution includes the following steps −
 Flag register value is pushed on to the stack.
 CS value of the return address and IP value of the return address are pushed on to the stack.
 IP is loaded from the contents of the word location ‘type number’ × 4
 CS is loaded from the contents of the next word location.
 Interrupt Flag and Trap Flag are reset to 0
The starting address for type0 interrupt is 000000H, for type1 interrupt is 00004H similarly for type2
is 00008H and ……so on. The first five pointers are dedicated interrupt pointers. i.e. −
 TYPE 0 interrupt represents division by zero situation.
 TYPE 1 interrupt represents single-step execution during the debugging of a program.
 TYPE 2 interrupt represents non-maskable NMI interrupt.
 TYPE 3 interrupt represents break-point interrupt.
 TYPE 4 interrupt represents overflow interrupt.
The interrupts from Type 5 to Type 31 are reserved for other advanced microprocessors, and
interrupts from 32 to Type 255 are available for hardware and software interrupts.
INT 3-Break Point Interrupt Instruction
It is a 1-byte instruction having op-code is CCH. These instructions are inserted into the program
so that when the processor reaches there, then it stops the normal execution of program and follows
the break-point procedure.
Its execution includes the following steps −
 Flag register value is pushed on to the stack.
 CS value of the return address and IP value of the return address are pushed on to the stack.
 IP is loaded from the contents of the word location 3×4 = 0000CH
  CS is loaded from the contents of the next word location.
 Interrupt Flag and Trap Flag are reset to 0
INTO - Interrupt on overflow instruction
It is a 1-byte instruction and their mnemonic INTO. The op-code for this instruction is CEH. As the
name suggests it is a conditional interrupt instruction, i.e. it is active only when the overflow flag is
set to 1 and branches to the interrupt handler whose interrupt type number is 4. If the overflow flag
is reset then, the execution continues to the next instruction.
Its execution includes the following steps −
 Flag register values are pushed on to the stack.
 CS value of the return address and IP value of the return address are pushed on to the stack.
 IP is loaded from the contents of word location 4×4 = 00010H
 CS is loaded from the contents of the next word location.
 Interrupt flag and Trap flag are reset to 0

#8259PIC
The 8259 is known as the Programmable Interrupt Controller (PIC) microprocessor. In 8085 and
8086 there are five hardware interrupts and two hardware interrupts respectively. Bu adding 8259,
we can increase the interrupt handling capability. This chip combines the multi-interrupt input source
to single interrupt output. This provides 8-interrupts from IR0 to IR7. Let us see some features of
this microprocessor.
 This chip is designed for 8085 and 8086.
 It can be programmed either in edge triggered, or in level triggered mode
 We can mask individual bits of Interrupt Request Register.
 By cascading 8259 chips, we can increase interrupts up to 64 interrupt lines
 Clock cycle is not needed.

The pin level diagram and functional pin diagram is like below -
The block diagram is like below -
 Block Description

Data Bus Buffer This block is used to communicate between 8259 and 8085/8086 by
acting as buffer. It takes the control word from 8085/8086 and send it
to the 8259. It transfers the opcode of the selected interrupts and
address of ISR to the other connected microprocessor. It can send
maximum 8-bit at a time.

R/W Control Logic This block works when the value of pin CS is 0. This block is used to
flow the data depending upon the inputs of RD and WR. These are
active low pins for read and write.

Control Logic It controls the functionality of each block. It has pin called INTR. This is
connected to other microprocessors for taking the interrupt request.
The INT pin is used to give the output. If 8259 is enabled, and also the
interrupt flags of other microprocessors are high then this causes the
value of the output INT pin high, and in this way this chip can responds
requests made by other microprocessors.

Interrupt Request It stores all interrupt level that are requesting for interrupt service.
Register
 Block Description

Interrupt Service It stores interrupt level that are currently being execute.
Register

Interrupt Mask It stores interrupt level that will be masked, by storing the masking bits
Register of interrupt level.

Priority Resolver It checks all three registers, and set the priority of the interrupts.
Interrupt with the highest priority is set in the ISR register. It also reset
the interrupt level which is already been serviced in the IRR.

Cascade Buffer To increase number of interrupt pin, we can cascade more number of
pins, by using cascade buffer. When we are going to increase the
interrupt capability, CSA lines are used to control multiple interrupts.

GEEKSFORGEEKS

8259 PIC Microprocessor

8259 microprocessor is defined as Programmable Interrupt Controller (PIC) microprocessor.
There are 5 hardware interrupts and 2 hardware interrupts in 8085 and 8086 respectively. But by
connecting 8259 with CPU, we can increase the interrupt handling capability. 8259 combines the
multi interrupt input sources into a single interrupt output. Interfacing of single PIC provides 8
interrupts inputs from IR0-IR7.
For example, Interfacing of 8085 and 8259 increases the interrupt handling capability of 8085
microprocessor from 5 to 8 interrupt levels.
Features of 8259 PIC microprocessor –

1. Intel 8259 is designed for Intel 8085 and Intel 8086 microprocessor.
2. It can be programmed either in level triggered or in edge triggered interrupt level.
3. We can masked individual bits of interrupt request register.
4. We can increase interrupt handling capability upto 64 interrupt level by cascading further
8259 PIC.
5. Clock cycle is not required.
Pin Diagram of 8259 –
We can see through above diagram that there are total 28 pins in 8259 PIC microprocessor where
Vcc :5V Power supply and Gnd: ground. Other pins use are explained below.
Block Diagram of 8259 PIC microprocessor –

The Block Diagram consists of 8 blocks which are – Data Bus Buffer, Read/Write Logic, Cascade
Buffer Comparator, Control Logic, Priority Resolver and 3 registers- ISR, IRR, IMR.
 1. Data bus buffer –
This Block is used as a mediator between 8259 and 8085/8086 microprocessor by acting as
a buffer. It takes the control word from the 8085 (let say) microprocessor and transfer it to the
control logic of 8259 microprocessor. Also, after selection of Interrupt by 8259
microprocessor, it transfer the opcode of the selected Interrupt and address of the Interrupt
service sub routine to the other connected microprocessor. The data bus buffer consists of 8
bits represented as D0-D7 in the block diagram. Thus, shows that a maximum of 8 bits data
can be transferred at a time.
2. Read/Write logic –
This block works only when the value of pin CS is low (as this pin is active low). This block is
responsible for the flow of data depending upon the inputs of RD and WR. These two pins
are active low pins used for read and write operations.
3. Control logic –
It is the centre of the microprocessor and controls the functioning of every block. It has pin
INTR which is connected with other microprocessor for taking interrupt request and pin INT
for giving the output. If 8259 is enabled, and the other microprocessor Interrupt flag is high
then this causes the value of the output INT pin high and in this way 8259 responds to the
request made by other microprocessor.
4. Interrupt request register (IRR) –
It stores all the interrupt level which are requesting for Interrupt services.
5. Interrupt service register (ISR) –
It stores the interrupt level which are currently being executed.
6. Interrupt mask register (IMR) –
It stores the interrupt level which have to be masked by storing the masking bits of the
interrupt level.
7. Priority resolver –
It examines all the three registers and set the priority of interrupts and according to the
priority of the interrupts, interrupt with highest priority is set in ISR register. Also, it reset the
interrupt level which is already been serviced in IRR.
8. Cascade buffer –
To increase the Interrupt handling capability, we can further cascade more number of pins by
using cascade buffer. So, during increment of interrupt capability, CSA lines are used to
control multiple interrupt structure.
SP/EN (Slave program/Enable buffer) pin is when set to high, works in master mode else in slave
mode. In Non Buffered mode, SP/EN pin is used to specify whether 8259 work as master or slave
and in Buffered mode, SP/EN pin is used as an output to enable data bus.
 IVT :::::::::::

8086 Interrupts
August 15, 2018

8086 INTERRUPTS, MICROPROCESSORS

8086 Interrupt:
An 8086 interrupt can come from any one the three sources :
 External signal
 Special Instruction in the program
 Condition produced by instruction
External Signal (Hardware Interrupt):
An 8086 can get interrupt from an external signal applied to the nonmaskable interrupt (NMI)
input pin; or the interrupt (INTR) input pin.
Special Instruction:
8086 supports a special instruction, INT to execute special program. At the end of the
interrupt service routine, execution is usually returned to the interrupted program.
Condition Produced by Instruction:
An 8086 is interrupted by some condition produced in the 8086 by the execution of an
instruction. For example divide by zero : Program execution will automatically be interrupted
if you attempt to divide an operand by zero.
At the end of each instruction cycle 8086 Interrupts checks to see if there is any interrupt
request. If so, 8086 responds to the interrupt by performing series of actions (Refer Fig. 9.1).

1. It decrements stack pointer by 2 and pushes the flag register on the stack..
2. It disables the INTR interrupt input by clearing the interrupt flag in the flag
3. It resets the trap flag in the flag register.
4. It decrements stack pointer by 2 and pushes the current code segment register contents on the
stack.
5. It decrements stack pointer by 2 and pushes the current instruction pointer contents on the stack.
6. It does an indirect far jump at the start of the procedure by loading the CS and IP values for the
start of the interrupt service routine (ISR).
An IRET instruction at the end of the interrupt service procedure returns execution to the
main program.
Now the question is “How to get the values of CS and IP register ?” The 8086 gets the new
values of CS and IP register from four memory addresses. When it responds to an interrupt,
the 8686 goes to memory locations to get the CS and IP values for the start of the interrupt
service routine. In an 8086 Interrupt system the first 1 Kbyte of memory from 00000H to
003FFH is reserved for storing the starting addresses of interrupt service routines. This block
of memory is often called the interrupt vector table or the interrupt pointer table. Since 4
bytes are required to store the CS and IP values for each interrupt service procedure, the
table can hold the starting addresses for 256 interrupt service routines. Fig. 9.2 shows how
the 256 interrupt pointers are arranged in the memory table.

An interrupt vector table (IVT) is a data structure that associates a list of interrupt
handlers with a list of interrupt requests in a table of interrupt vectors. Each entry of the
interrupt vector table, called an interrupt vector, is the address of an interrupt handler.
While the concept is common across processor architectures, IVTs may be implemented
in architecture-specific fashions. For example, a dispatch table is one method of
implementing an interrupt vector table.
Each interrupt type is given a number between 0 to 255 and the address of each interrupt js
found by multiplying the type by 4 e.g. for type 11, interrupt address is 11 x 4 = 4410= 0002CH
Only first five types have explicit definitions such as divide by zero and non maskable
interrupt. The next 27 interrupt types, from 5 to 31, are reserved by Intel for use in future
microprocessors. The upper 224 interrupt types, from 32 to 255, are available for user for
hardware or software interrupts.
When the 8086 Interrupt responds to an interrupt, it automatically goes to the specified
location in the interrupt vector table to get the starting address of interrupt service routine.
So user has to load these starting addresses for different routines at the start of the program.

#IV2_2

1. An interrupt is a special condition that arises during the working of a microprocessor. The
microprocessor services it by executing a subroutine called Interrupt Service Routine (ISR).
2. There are three sources of interrupts for 8086:
3. Hardware interrupt-
 These interrupts occur as signals on the external pins of the microprocessor. 8086 has two
pins to accept hardware interrupts, NMI and INTR.

4. Software interrupt-

These interrupts are caused by writing the software interrupt instruction INT n where ‘n’ can
be any value from 0 to 255 (00H to FFH). Hence all 256 interrupts can be invoked by
software.

5. Error conditions (Exception or types)-

8086 is interrupted when some special conditions occur while executing certain instructions
in the program. Example: An error in division automatically causes the INT 0 interrupt.

Interrupt Vector Table (IVT):

1. The interrupt vector (or interrupt pointer) table is the link between an interrupt type code
and the procedure that has been designated to service interrupts associated with that code.
8086 supports total 256 types i.e. 00H to FFH.
2. For each type it has to reserve four bytes i.e. double word. This double word pointer
contains the address of the procedure that is to service interrupts of that type.
3. The higher addressed word of the pointer contains the base address of the segment
containing the procedure. This base address of the segment is normally referred as NEW
CS.
4. The lower addressed word contains the procedure’s offset from the beginning of the
segment. This offset is normally referred as NEW IP.
5. Thus NEW CS: NEW IP provides NEW physical address from where user ISR routine will
start.
 6. As for each type, four bytes (2 for NEW CS and 2 for NEW IP) are required; therefore
interrupt pointer table occupies up to the first 1k bytes (i.e. 256 x 4 = 1024 bytes) of low
memory.
7. The total interrupt vector table is divided into three groups namely,

A. Dedicated interrupts (INT 0…..INT 4)

B. Reserved interrupts (INT 5…..INT 31)

C. Available interrupts (INT 32…..INT 225)

A. Dedicated interrupts (INT 0…..INT 4):

1. INT 0 (Divide Error)-

o This interrupt occurs whenever there is division error i.e. when the result of a division
is too large to be stored. This condition normally occurs when the divisor is very
small as compared to the dividend or the divisor is zero.
o Its ISR address is stored at location 0 x 4 = 00000H in the IVT.
2. INT 1 (Single Step)-

o The microprocessor executes this interrupt after every instruction if the TF is set.
o It puts microprocessor in single stepping mode i.e. the microprocessor pauses after
executing every instruction. This is very useful during debugging.
o Its ISR generally displays contents of all registers. Its ISR address is stored at
location 1 x 4 = 00004H in the IVT.
3. INT 2 (Non mask-able Interrupt)-

o The microprocessor executes this ISR in response to an interrupt on the NMI (Non
mask-able Interrupt) line.
o Its ISR address is stored at location 2 x 4 = 00008H in the IVT.
4. INT 3 (Breakpoint Interrupt)-

o This interrupt is used to cause breakpoints in the program. It is caused by writing the
instruction INT 03H or simply INT.
o It is useful in debugging large programs where single stepping is efficient.
o Its ISR is used to display the contents of all registers on the screen. Its ISR address
is stored at location 3 x 4 = 0000CH in the IVT.
5. INT 4 (Overflow Interrupt)-

o This interrupt occurs if the overflow flag is set and the microprocessor executes the
INTO (Interrupt on Overflow) instruction.
o It is used to detect overflow error in signed arithmetic operations.
o Its ISR address is stored at location 4 x 4 = 00010H in the IVT.

B. Reserved interrupts (INT 5…..INT 31):

1. These levels are reserved by Intel to be used in higher processors like 80386, Pentium etc.
They are not available to the user.
C. Available interrupts (INT 32…..INT 225):

1. These are user defined, software interrupts.

2. ISRs for these interrupts are written by the users to service various user defined conditions.
3. These interrupts are invoked by writing the instruction INT n. Its ISR address is obtained by
the microprocessor from location n x 4 in the IVT.

Hardware Interrupts:

1. NMI (Non mask-able interrupt)-

o This is a non-mask-able, edge triggered, high priority interrupt.

o On receiving an interrupt on NMI line, the microprocessor executes INT
o Microprocessor obtains the ISR address from location 2 x 4 = 00008H from the IVT.
o It reads 4 locations starting from this address to get the values for IP and CS to
execute the ISR.
2. INTR-

o This is a mask-able, level triggered, low priority interrupt.

o On receiving an interrupt on INTR line, the microprocessor executes
2 INTA¯¯¯¯¯¯¯¯¯¯¯¯¯¯INTA¯ pulses.
o 1st INTA¯¯¯¯¯¯¯¯¯¯¯¯¯¯INTA¯ pulse – The interrupting device calculates (prepares to
send) the vector number.
2nd INTA¯¯¯¯¯¯¯¯¯¯¯¯¯¯INTA¯ pulse – The interrupting device sends the vector
number ‘N’ to the microprocessor.

o Now microprocessor multiplies N x 4 and goes to the corresponding location in the

IVT to obtain the ISR address. INTR is a mask-able interrupt.
o It is masked by making IF = 0 by software through CLI instruction.
o It is unmasked by making IF = 1 by software through STI instruction.

8259PPI :::::::

Features:

1. It is a LSI chip which manages 8 levels of interrupts i.e. it is used to implement 8 level
interrupt systems.
2. It can be cascaded in a master slave configuration to handle up to 64 levels of interrupts.
3. It can identify the interrupting device.
4. It can resolve the priority of interrupt requests i.e. it does not require any external priority
resolver.
5. It can be operated in various priority modes such as fixed priority and rotating priority.
6. The interrupt requests are individually mask-able.
7. The operating modes and masks may be dynamically changed by the software at any time
during execution of programs.
 8. It accepts requests from the peripherals, determines priority of incoming request, checks
whether the incoming request has a higher priority value than the level currently being
serviced and issues an interrupt signal to the microprocessor.
9. It provides 8 bit vector number as an interrupt information.
10. It does not require clock signal.
11. It can be used in polled as well as interrupt modes.
12. The starting address of vector number is programmable.
13. It can be used in buffered mode.

The block diagram of 8259 is shown in the figure below:

It contains following blocks-

1. Data bus buffer-

 It is used to transfer data between microprocessor and internal bus.

1. Read/write logic-

 It sets the direction of data bus buffer.

 It controls all internal read/write operations.
 It contains initialization and operation command registers.

1. Cascaded buffer and comparator-

 In master mode, it functions as a cascaded buffer. The cascaded buffers outputs slave
identification number on cascade lines.
 In slave mode, it functions as a comparator. The comparator reads slave identification
number from cascade lines and compares this number with its internal identification
number.
 In buffered mode, it generates an (EN) ̅ signal.

1. Control logic-

 It generates an INT signal. In response to an (INTA) ̅ signal, it releases three byte CALL
address or one byte vector number.
 It controls read/write control logic, cascade buffer/comparator, in service register, priority
resolver and IRR.
1. Interrupt request register-

 It is used to store all pending interrupt requests.

 Each bit of this register is set at the rising edge or at the high level of the corresponding
interrupt request line.
 The microprocessor can read contents of this register by issuing appropriate command
word.

1. In service register (InSR)-

 It is used to store all interrupt levels currently being serviced.

 Each bit of this register is set by priority resolver and reset by end of interrupt command
word.
 The microprocessor can read contents of this register by issuing appropriate command
word.

1. Priority resolver-

 It determines the priorities of the bit set in the IRR. To make decision, the priority resolver
looks at the ISR.
 If the higher priority bit in the InSR is set then it ignores the new request.
 If the priority resolvers find that the new interrupt has a higher priority than the highest
priority interrupt currently being serviced and the new interrupt is not in service, then it will
set appropriate bit in the InSR and send the INT signal to the microprocessor for new
interrupt request.

1. Interrupt mask register (IMR)-

 It is a programmable register.
 It is used to mask unwanted interrupt request by writing appropriate command word.
 The microprocessor can read contents of this register without issuing any command word.