Programmable Peripheral Interface (8255)

Features

1) 3, 8bit parallel ports (Port A, Port B, Port C)

2) Operating modes

a) Simple I/O mode – Port A, Port B, Port C

b) Bit Set Reset (BSR) – Port C

Pin Details

Data Bus Buffer (D7-D0)

It is a tri-state 8-bit buffer, which is used to interface the microprocessor to the system data
bus. Data is transmitted or received by the buffer as per the instructions by the CPU. Control
words and status information is also transferred using this bus.

Read/Write Control Logic

This block is responsible for controlling the internal/external transfer of data/control/status

word. It accepts the input from the CPU address and control buses, and in turn issues
command to both the control groups.

CS
It stands for Chip Select. A LOW on this input selects the chip and enables the communication
between the 8255A and the CPU. It is connected to the decoded address, and A 0 & A1 are
connected to the microprocessor address lines.
Their result depends on the following conditions −

CS A1 A0 Result

0 0 0 PORT A

0 0 1 PORT B

0 1 0 PORT C

0 1 1 Control Register

1 X X No Selection

WR

It stands for write. This control signal enables the write operation. When this signal goes low,
the microprocessor writes into a selected I/O port or control register.

RESET

This is an active high signal. It clears the control register and sets all ports in the input mode.

RD

It stands for Read. This control signal enables the Read operation. When the signal is low, the
microprocessor reads the data from the selected I/O port of the 8255.

A0 and A1

A0 , A1 are the address lines, meant for selecting PORT A, PORT B, PORT C, Control Word
Register.

A1 A0 Result

0 0 PORT A

0 1 PORT B

1 0 PORT C
 1 1 Control Register

Block Diagram of 8255

The parallel input-output port chip 8255 is also called as programmable peripheral input-
output port. The Intel’s 8255 is designed for use with Intel’s 8-bit, 16-bit and higher capability
microprocessors.

It has 24 input/output lines which may be individually programmed in two groups of twelve lines
each, or three groups of eight lines. The two groups of I/O pins are named as Group A and Group
B. Each of these two groups contains a subgroup of eight I/O lines called as 8-bit port and
another subgroup of four lines or a 4-bit port.

Thus Group A contains an 8-bit port A along with a 4-bit port. C upper. The port A lines are
identified by symbols PA0-PA7 while the port C lines are identified as PC4-PC7. Similarly,
Group B contains an 8-bit port B, containing lines PB0-PB7 and a 4-bit port C with lower bits
PC0- PC3. The port C upper and port C lower can be used in combination as an 8-bit port C.
Both the port C are assigned the same address. Thus one may have either three 8-bit I/O ports or
two 8-bit and two 4-bit ports from 8255. All of these ports can function independently either as
input or as output ports. This can be achieved by programming the bits of an internal register of
8255 called as control word register (CWR). This buffer receives or transmits data upon the
execution of input or output instructions by the microprocessor. The control words or status
information is also transferred through the buffer.

Control Word Register

Modes of operation

1) Simple I/O modes (Mode0, Mode1, Mode 2)

2) BSR ( Bit Set Reset)

1 0 0 0 0 0 1 0= 82H

1 0 0 1 0 0 0 0 – 90H

1 1 1 1 0 1 0 0 – F4H
1 0 0 0 0 0 0 0 – 80H; 1001 0000- 90H

Simple I/O mode

Mode 0: Basic I/O mode (PORT A, B, C)

Mode 1: Strobe I/O mode (PORT A, B,)
Port C involved in taking care of handshaking signals
INPUT PORT
Handshaking signals:
STB, IBF, INTR
OUTPUT PORT
Handshaking signals:
OBF, ACK, INTR

Mode 2: (Bi directional port)

PORT A - Bi directional port

BSR Mode

Interfacing Diagram

Address of CWR as 43- 0100 0011, PORTB – 41- 0100 0001

MOV AL, 80H

OUT 43, AL
MOV AL, FFH / AA H 1111 1111- FFH

OUT 41, AL

1010 1010 – AA

Assume that 8 push buttons are connected to PORT B. Write a program to read the
pressed push button and store in the memory address of 4000. Consider the following
address,

CWR –50, PORT B- 45.

MOV AL, 82H

OUT 50H, AL
IN AL, 45H
MOV [4000], AL
8251-Serial Communication Interface- USART
(Universal Synchronous Asynchronous Receiver Transmitter)
Serial Data Communication
1111 0000 – bit by bit
Serial Data Communication (Direction)

1) Simplex ( one way communication)

2) Half duplex (two way communication but in one direction at a time only)
3) Full duplex ( both directions simultaneously)
Serial Data Communication (Timing signals)

1) Asynchronous
TX and RX not synchronized with same clock, Data format – start, data, parity,
stop bits, low speed data transfer
2) Synchronous
TX and RX synchronized with same clock, data format – block header (Sync
characters) data bits, high speed data transfer
Features of 8251
1) Synchronous and asynchronous
 2) Programmable data word length, parity and stop bits
3) Programmable at 3 different baud rates
Pin Description (Signals) of 8251

Data lines: (D7-D0)

Read Write Control Logic

 CS: It is chip select. A low signal at this pin shows that processor has selected 8251 in
order to communicate with the peripheral devices.
 C/D: As the system has control, status and data register. So, when a high signal is
present at this pin then control or status register is addressed. While in case of low
signal data register is addressed.
 RD and WR: Both read and write are active low signal pins. A low signal at RD shows
that the processor is reading the control, status or data bytes from the 8251. While
at WR indicates the write operation over the data bus of 8251.
 CLK and RESET: CLK stands for clock and it produces the internal timing for the
device. While an active high signal at the RESET pin puts the 8251 in the idle mode.
Transmitter Section

 TxRDY: It implies transmit ready. This signal is used to notify the processor that the
buffer register of the 8251 is empty and ready to accept the data.
The status read operation is utilized by the processor in order to check the presence
of the signal.
 TxE: This stands for transmitter empty. It is an active high signal that indicates that
the output buffer is empty and thus data received from the processor can be loaded
to it for conversion.
 TxC: It stands for transmitter clock and is an active low pin. It controls the rate of
character transmission by the USART.

Receiver Section

 RxRDY: It stands for receiver ready. When this signal goes high then it indicates that
the receiver buffer register is holding the data and is ready to transfer it to the
processor. Once the CPU reads the data sent by the 8251 then this pin is reset.
 RxC: It stands for receiver clock. This clock signalling controls the rate at which the
8251 receives the data in the synchronous mode of operation. It is provided by the
modem and is equal to the baud rate.
While asynchronous mode offers the clock rate as 1, 16 or 64 times of the baud rate
as it is programmable.
Modem Control

 DSR: Stands for data set ready and the signal is used to check whether the data set is
ready or not when the processor is in the urge of communication.
 DTR: Implies data terminal ready. An active-low signal at this pin shows that the
8251 is now ready to accept the data from the processor.
 RTS: It stands for the request to send. A low signal shows an assertion for data
transmission.
 CTS: Clear to send. When 8251 receives a low signal at this pin then it clears all the
data present in the modem in order to allow further communication.

Block Diagram
Control Word of 8251

Mode instruction
1101 1010- DA H ;

MOV AL, DA H

OUT 20H, AL; MOV AL, 05H; OUT 20H, AL

The instruction can be considered as four 2-bit fields. The first 2-bit field (D 1-D0) determines
whether the USART is to operate in the synchronous (00) or asynchronous mode. In the
asychronous mode, this field determines the division factor for clock to decide the baud rate.
For example, if D1 and D0 are both ones, the RxC and TxC will be divided by 64 to establish the
baud rate.
The second 2-bit field (D 3-D2) determines number of data bits in one character. With this 2-bit
field we can set character length from 5-bits to 8 bits.
The third 2-bit field, (D 5-D4), controls the parity generation. The parity bit is added to the data
bits only if parity is enabled.
The last field, (D7-D6), has two meanings depending on whether operation is to be in the
synchronous or asynchronous mode. For asynchronous mode, (i.e. D 1D0 ≠ 00), it controls the
number of STOP bits to be transmitted with the character. In synchronous mode, (i.e. D 1D0) = 00)
this field controls the synchronizing process. It decides whether to operate with external
synchronization or internal synchronization and whether to transmit single synchronizing
character or two synchronizing characters.

Command Instruction
Status Word
 Programmable Interval Timer 8253/54

1) Three independent 16-bit down counters.

2) 8254 can handle clock inputs- 10 MHz where as 8253 can operate upto 2.6 MHz.

3) Three counters are identical presettable, and can be programmed for either binary or BCD count.

4) Counter can be programmed in six different modes.

6) 8254 has powerful command called READ BACK command which allows the user to check the count
value, programmed mode and current mode and current status of the counter.

In the above figure, there are three counters, a data bus buffer, Read/Write control logic, and a
control register. Each counter has two input signals - CLOCK & GATE, and one output signal -
OUT.
Data Bus Buffer
It is a tri-state, bi-directional, 8-bit buffer, which is used to interface the 8253/54 to the system
data bus. It has three basic functions −
 Programming the modes of 8253/54.
 Loading the count registers.
 Reading the count values.
Read/Write Logic
It includes 5 signals, i.e. RD, WR, CS, and the address lines A 0 & A1. In the peripheral I/O
mode, the RD and WR signals are connected to IOR and IOW, respectively. In the
memorymapped I/O mode, these are connected to MEMR and MEMW.
Address lines A0 & A1 of the CPU are connected to lines A 0 and A1 of the 8253/54, and CS is
tied to a decoded address. The control word register and counters are selected according to the
signals on lines A0 & A1.

A1 A0 Result

0 0 Counter 0

0 1 Counter 1

1 0 Counter 2

1 1 Control Word Register

X X No Selection

Control Word Register

This register is accessed when lines A0 & A1 are at logic 1. It is used to write a command word,
which specifies the counter to be used, its mode, and either a read or write operation. Following
table shows the result for various control inputs.

A1 A0 RD WR CS Result

0 0 1 0 0 Write Counter 0

0 1 1 0 0 Write Counter 1

1 0 1 0 0 Write Counter 2

1 1 1 0 0 Write Control Word

0 0 0 1 0 Read Counter 0

0 1 0 1 0 Read Counter 1

1 0 0 1 0 Read Counter 2

1 1 0 1 0 No operation
 X X 1 1 0 No operation

X X X X 1 No operation

Counters
Each counter consists of a single, 16 bit-down counter, which can be operated in either binary or
BCD. Its input and output is configured by the selection of modes stored in the control word
register. The programmer can read the contents of any of the three counters without disturbing
the actual count in process.
GATE: It’s an input used to enable/disable the counting process.
Clock: It’s an input and based on this counter value gets decremented by one.
OUT: It’s an output signal used to indicate the completion of required counting or timing
operation.

9999-0000
Control Word Register : 1011 0100- B4 FFFF-0000

The values of M2, M1, M 0 are used to decide the operating modes of 8254:

M2 M1 M0 OPERATING MODE

0 0 0 MODE 0

0 0 1 MODE 1

X (0/1) 1 0 MODE 2

X (0/1) 1 1 MODE 3

1 0 0 MODE 4

1 0 1 MODE 5
Operating Modes of 8254:

1. Mode 0 (Interrupt on Terminal Count) – Mode 0 is typically used for event counting.
After the Control Word is written, OUT is initially low, and will remain low until the
counter reaches zero it is decremented by 1 after every clock cycle. OUT then goes high
and remains high until a new count or a new Mode 0 Control Word is written into the
counter. GATE = 1 enables counting, GATE = 0 disables counting.

2. Mode 1 (Hardware Retriggreable One Shot) – OUT will be initially high. OUT will go
low on the CLK pulse following a trigger to begin the one-shot pulse, and will remain low
until the counter reaches zero.
3. Mode 2 (Rate Generator) – Initially value of OUT is low. When counting is enabled, it
becomes high and this process repeats periodically. Value of count = Input Frequency /
Output Frequency. This mode works as a frequency divider.

4. Mode 3 (Square Wave Generator) – Counting is enabled when GATE = 1 and disabled
when GATE = 0. This mode is used to generate square waveform and time period (equal to
count) is generated.
If N is count and is even then ontime of wave = N/2 and offtime = N/2
If N is odd the ontime = (N + 1) / 2 and offtime = (N – 1) / 2

5. Mode 4 (Software Triggered Strobe) – In this mode counting is enabled by using GATE
= 1 and disabled by GATE = 0. Initially value of OUT is high and becomes low when
value of count is at last stage. Count is reloaded again for subsequent clock pulse.

6. Mode 5 (Hardware Triggered Strobe) – OUT will initially be high. Counting is triggered
by a rising edge of GATE. When the initial count has expired, OUT will go low for one
clock pulse and then go high again. After writing the Control Word and initial count, the
counter will not be loaded until the clock pulse after a trigger.
Delay = 10ms, Clk freq=1MHz,

Count value = required time delay/ clock period ; = 10ms/ 1 microseconds= 10,000

0000-9999 – BCD;

Represent in the value 10,000 terms of Hexadecimal

 8279 - Programmable Keyboard and Display Controller

Features
1) Simultaneous-keyboard and display operations
2) 64-contact keys/switches
3) 16- 7segment LED
4) Operating – Input mode (Keyboard)
Output mode (display)
Pin Description

Data Bus Lines, DB0 - DB7

These are 8 bidirectional data bus lines used to transfer the data to/from the CPU.

CLK

The clock input is used to generate internal timings required by the microprocessor.

RESET
As the name suggests this pin is used to reset the microprocessor.

CS Chip Select

When this pin is set to low, it allows read/write operations, else this pin should be set to
high.

A0

This pin indicates the transfer of command/status information. When it is low, it

indicates the transfer of data.

RD, WR

This Read/Write pin enables the data buffer to send/receive data over the data bus.

IRQ

This interrupt output line goes high when there is data in the FIFO sensor RAM. The
interrupt line goes low with each FIFO RAM read operation. However, if the FIFO
RAM further contains any key-code entry to be read by the CPU, this pin again goes
high to generate an interrupt to the CPU.

Vss, Vcc

These are the ground and power supply lines of the microprocessor.

SL0 − SL3

These are the scan lines used to scan the keyboard matrix and display the digits. These
lines can be programmed as encoded or decoded, using the mode control register.

RL0 − RL7

These are the Return Lines which are connected to one terminal of keys, while the other
terminal of the keys is connected to the decoded scan lines. These lines are set to 0 when
any key is pressed.

SHIFT

The Shift input line status is stored along with every key code in FIFO in the scanned
keyboard mode. Till it is pulled low with a key closure, it is pulled up internally to keep
it high
CNTL/STB - CONTROL/STROBED I/P Mode

In the keyboard mode, this line is used as a control input and stored in FIFO on a key
closure. The line is a strobe line that enters the data into FIFO RAM, in the strobed input
mode. It has an internal pull up. The line is pulled down with a key closure.

BD

It stands for blank display. It is used to blank the display during digit switching.

OUTA0 – OUTA3 and OUTB0 – OUTB3

These are the output ports for two 16x4 or one 16x8 internal display refresh registers.
The data from these lines is synchronized with the scan lines to scan the display and the
keyboard.
Block Diagram of 8279
I/O Control and Data Buffer
This unit controls the flow of data through the microprocessor. It is enabled only when
D is low. Its data buffer interfaces the external bus of the system with the internal bus of
the microprocessor. The pins A0, RD, and WR are used for command, status or data
read/write operations.
Control and Timing Register and Timing Control
This unit contains registers to store the keyboard, display modes, and other operations as
programmed by the CPU. The timing and control unit handles the timings for the
operation of the circuit.
Scan Counter
It has two modes i.e. Encoded mode and Decoded mode. In the encoded mode, the
counter provides the binary count that is to be externally decoded to provide the scan
lines for the keyboard and display.
In the decoded scan mode, the counter internally decodes the least significant 2 bits and
provides a decoded 1 out of 4 scan on SL0-SL3.
Return Buffers, Keyboard Debounce, and Control
This unit first scans the key closure row-wise, if found then the keyboard debounce unit
debounces the key entry. In case, the same key is detected, then the code of that key is
directly transferred to the sensor RAM along with SHIFT & CONTROL key status.
FIFO/Sensor RAM and Status Logic
This unit acts as 8-byte first-in-first-out (FIFO) RAM where the key code of every
pressed key is entered into the RAM as per their sequence. The status logic generates an
interrupt request after each FIFO read operation till the FIFO gets empty.
In the scanned sensor matrix mode, this unit acts as sensor RAM where its each row is
loaded with the status of their corresponding row of sensors into the matrix. When the
sensor changes its state, the IRQ line changes to high and interrupts the CPU.
Display Address Registers and Display RAM
This unit consists of display address registers which holds the addresses of the word
currently read/written by the CPU to/from the display RAM.

N key Roll over and 2 key lock out

b) Read FIFO/ Sensor RAM

000 – Memory location 0

001- Memory location 1
-----
111 – Memory location 7

C) Read Display RAM

d) Write display RAM

e) Scanned Keyboard Data format.

DMA CONTROLLER – 8257 ( Direct Memory Access)

DMA
It is a technique that enables the data transfer between memory and Input/output
devices without any involvement of CPU.
Features of 8257

1. It consists of 4 channels that can be utilized over 4 input/output devices.

2. All of the 4 channels can be separately programmed.
3. All the 4 channels hold the 16-bit address and 14-bit counters individually.
4. The permissible data transfer is up to 64 Kb.
5. The three operations performed are: read transfer, write transfer and verify the
transfer.
6. The two operating modes of 8257 are master mode and slave mode.
Pin Description:
DRQ0−DRQ3
These are the four individual channel DMA request inputs, which are used by the
peripheral devices for using DMA services. When the fixed priority mode is selected,
then DRQ0 has the highest priority and DRQ3 has the lowest priority among them.
DACKo − DACK3
These are the active-low DMA acknowledge lines, which updates the requesting
peripheral about the status of their request by the CPU. These lines can also act as
strobe lines for the requesting devices.
Do − D7
These are bidirectional, data lines which are used to interface the system bus with the
internal data bus of DMA controller. In the Slave mode, it carries command words to
8257 and status word from 8257. In the master mode, these lines are used to send
higher byte of the generated address to the latch. This address is further latched using
ADSTB signal.
IOR
It is an active-low bidirectional tri-state input line, which is used by the CPU to read
internal registers of 8257 in the Slave mode. In the master mode, it is used to read data
from the peripheral devices during a memory write cycle.
IOW
It is an active low bi-direction tri-state line, which is used to load the contents of the
data bus to the 8-bit mode register or upper/lower byte of a 16-bit DMA address
register or terminal count register. In the master mode, it is used to load the data to
the peripheral devices during DMA memory read cycle.
CLK
It is a clock frequency signal which is required for the internal operation of 8257.
RESET
This signal is used to RESET the DMA controller by disabling all the DMA channels.
A o - A3
These are the four least significant address lines. In the slave mode, they act as an
input, which selects one of the registers to be read or written. In the master mode,
they are the four least significant memory address output lines generated by 8257.
A3 A2 A1 A0 REGISTER SELECTED
0 0 0 0 CH0- DMA ADDRESS REGISTER
0 0 0 1 CH0- TERMINAL COUNT REGISTER
0 0 1 0 CH1- DMA ADDRESS REGISTER
0 0 1 1 CH1- TERMINAL COUNT REGISTER
- - - - -
0 1 1 1 CH3- TERMINAL COUNTER REGISTER

CS
It is an active-low chip select line. In the Slave mode, it enables the read/write
operations to/from 8257. In the master mode, it disables the read/write operations
to/from 8257.
A 4 - A7
These are the higher nibble of the lower byte address generated by DMA in the master
mode.
READY
It is an active-high asynchronous input signal, which makes DMA ready by inserting
wait states.
HRQ
This signal is used to receive the hold request signal from the output device. In the
slave mode, it is connected with a DRQ input line 8257. In Master mode, it is connected
with HOLD input of the CPU.
HLDA
It is the hold acknowledgement signal which indicates the DMA controller that the bus
has been granted to the requesting peripheral by the CPU when it is set to 1.
MEMR
It is the low memory read signal, which is used to read the data from the addressed
memory locations during DMA read cycles.
MEMW
It is the active-low three state signal which is used to write the data to the addressed
memory location during DMA write operation.
ADSTB
This signal is used to convert the higher byte of the memory address generated by the
DMA controller into the latches.
AEN
This signal is used to disable the address bus/data bus.
TC
It stands for ‘Terminal Count’, which indicates the present DMA cycle to the present
peripheral devices.
MARK
The mark will be activated after each 128 cycles or integral multiples of it from the
beginning. It indicates the current DMA cycle is the 128th cycle since the previous
MARK output to the selected peripheral device.
Vcc
It is the power signal which is required for the operation of the circuit.

Block Diagram
Data Bus Buffer:
It is a tri-state, bi-directional, eight bit buffer which interfaces the 8257 to the system
data bus. In the slave mode, it is used to transfer data between microprocessor and
internal registers of 8257. In master mode, it is used to send higher byte address (A 8-A15)
on the data bus.
Read/Write logic:
When the CPU is programming or reading one of the internal registers of 8257 Pin
Diagram (i.e, when the 8257 is in the slave mode), the Read/Write logic accepts the I/O
Read (IOR) or I/O Write (IOW) signal, decodes the the least significant four addiess bits
(A0 – A3) and either writes the contents of the data bus into the addressed register (if
IOW is low) or places the contents of the addressed register onto the data bus (if IOR is
low).
During DMA cycles (i.e. when the 8257 is in the master mode) the Read/Write logic
generates the I/O read and memory write (DMA write cycle ) or I/O write and memory
read (DMA read cycle) signals which control the data transfer between peripheral and
memory device.

The 8257 Pin Diagram provides four identical channels, labeled CH 0 to CH3. Each channel
has two sixteen bit registers:
1. A DMA address register, and
2. A terminal count register.
DMA address register : Fig. 14.63 shows the format of DMA address register. It specifies
the address of the first memory location to be accessed. It is necessary to load valid
memory address in the DMA address register before channel is enabled.

Terminal Count Register : Fig. 14.64 shows the format of Terminal Count register.

Note : N is number of bytes to be transferred.

The value loaded into the low order 14 bits (C 13 — C0) of the terminal count register
specifies the number of DMA cycles minus one before the terminal count (TC) output is
activated. Therefore, for N number of desired DMA cycles it is necessary to load the
value N-1 into the low order 14-bits of the terminal count register. The most significant
2 bits of the terminal count register specifies the type of DMA operation to be
performed. It is necessary to load count for DMA cycles and operational code for valid
DMA cycle in the terminal count register before channel is enabled.
Control logic:
It controls the sequence of operations during all DMA cycles (DMA read, DMA write,
DMA verify) by generating the appropriate control signals and the 16-bit address that
specifies the memory location to be accessed. It consists of mode set register and status
register. Mode set register is programmed by the CPU to configure 8257 whereas the
status register is read by CPU to check which channels have reached a terminal count
condition and status of update flag.

The 8257 Pin Diagram provides four identical channels, labeled CH 0 to CH3. Each channel
has two sixteen bit registers:
1. A DMA address register, and
2. A terminal count register.
DMA address register : Fig. 14.63 shows the format of DMA address register. It specifies
the address of the first memory location to be accessed. It is necessary to load valid
memory address in the DMA address register before channel is enabled.

Terminal Count Register : Fig. 14.64 shows the format of Terminal Count
register.
Note : N is number of bytes to be transferred.
The value loaded into the low order 14 bits (C 13 — C0) of the terminal count register
specifies the number of DMA cycles minus one before the terminal count (TC) output is
activated. Therefore, for N number of desired DMA cycles it is necessary to load the
value N-1 into the low order 14-bits of the terminal count register. The most significant
2 bits of the terminal count register specifies the type of DMA operation to be
performed. It is necessary to load count for DMA cycles and operational code for valid
DMA cycle in the terminal count register before channel is enabled.
Control logic:
It controls the sequence of operations during all DMA cycles (DMA read, DMA write,
DMA verify) by generating the appropriate control signals and the 16-bit address that
specifies the memory location to be accessed. It consists of mode set register and status
register. Mode set register is programmed by the CPU to configure 8257 whereas the
status register is read by CPU to check which channels have reached a terminal count
condition and status of update flag.
Priority Resolver:
It resolves the peripherals requests. It can be programmed to work in two modes, either
in fixed mode or rotating priority mode.
Mode Set Register:
Fig. 14.65 gives the format of mode set register. Least significant four bits of mode set
register, when set, enable each of the four DMA channels. Most significant four bits
allow four different options for the 8257 Pin Diagram.
It is normally programmed by the CPU after initializing the DMA address registers and
terminal count registers. It is cleared by the RESET input, thus disabling all options,
inhibiting all channels, and preventing bus conflicts on power-up.

Status Register:
Fig. 14.66 shows the status register format. As said earlier, it indicates which channels
have reached a terminal count condition and includes the update flag described
previously.

The TC status bit, if one, indicates terminal count has been reached for that channel. TC
bit remains set until the status register is read or the 8257 is reset. The update flag,
however, is not affected by a status read operation.
The update flag bit, if one, indicates CPU that 8257 is executing update cycle. In update
cycle 8257 loads parameters in channel 3 to channel 2.
Interfacing of Devices to the Microprocessor
Connecting any devices to the microprocessor and establishing the data transfer.

Types of Addressing the Input / Output devices:

1. Memory mapped I/O
2. I/O mapped I/O
S.No Memory Mapped I/O I/O mapped I/O
1 Each I/O device treated as memory Each I/O device treated as distinct I/O
location. devices.
2 Entire address range is shared Separate address range is assigned for
among memory and I/O devices memory and I/O devices.
3. Instructions meant for data transfer Separate instructions are used for I/O
with memory devices are used for devices. IN, OUT
I/O devices.
4. Control signals such as MRD/MWR Control signals such as IOWR/IORD are
are used. used.

Programmable Interrupt Controller 8259

Features
1. supports 8 interrupts inputs from the peripherals and issues as a single interrupt signal
to the CPU.
2. cascading of 8 no’s of 8259- 64 interrupt sources can be availed.
3. Edge triggering or level triggering.
Signal Description:
Block diagram

The Block Diagram consists of 8 blocks which are – Data Bus Buffer, Read/Write Logic,
Cascade Buffer Comparator, Control Logic, Priority Resolver and 3 registers- ISR, IRR,
IMR.
1. Data bus buffer –
This Block is used as a mediator between 8259 and 8085/8086 microprocessor by
acting as a buffer. It takes the control word from the 8085 (let say) microprocessor
and transfer it to the control logic of 8259 microprocessor. Also, after selection of
Interrupt by 8259 microprocessor, it transfer the opcode of the selected Interrupt and
address of the Interrupt service sub routine to the other connected microprocessor.
The data bus buffer consists of 8 bits represented as D0-D7 in the block diagram.
Thus, shows that a maximum of 8 bits data can be transferred at a time.
2. Read/Write logic –
This block works only when the value of pin CS is low (as this pin is active low).
This block is responsible for the flow of data depending upon the inputs of RD and
WR. These two pins are active low pins used for read and write operations.
3. Control logic –
It is the centre of the microprocessor and controls the functioning of every block. It
has pin INTR which is connected with other microprocessor for taking interrupt
 request and pin INT for giving the output. If 8259 is enabled, and the other
microprocessor Interrupt flag is high then this causes the value of the output INT pin
high and in this way 8259 responds to the request made by other microprocessor.
4. Interrupt request register (IRR) –
It stores all the interrupt level which are requesting for Interrupt services.
5. Interrupt service register (ISR) –
It stores the interrupt level which are currently being executed.
6. Interrupt mask register (IMR) –
It stores the interrupt level which have to be masked by storing the masking bits of
the interrupt level.
7. Priority resolver –
It examines all the three registers and set the priority of interrupts and according to
the priority of the interrupts, interrupt with highest priority is set in ISR register.
Also, it reset the interrupt level which is already been serviced in IRR.
8. Cascade buffer –
To increase the Interrupt handling capability, we can further cascade more number
of pins by using cascade buffer. So, during increment of interrupt capability, CSA
lines are used to control multiple interrupt structure.
SP/EN (Slave program/Enable buffer) pin is when set to high, works in master mode else
in slave mode. In Non Buffered mode, SP/EN pin is used to specify whether 8259 work
as master or slave and in Buffered mode, SP/EN pin is used as an output to enable data
bus.
Command words
Initialization Command Words (ICW) and Operation Command Words(OCW)
ICW1
ICW2

ICW 3

ICW 4
Operation Control Word (OCW)
OCW1

OCW2
Interfacing ADC with 8086
Resolution = Vref / 2N - 1
V ref= 5V, 8 bit ADC
Resolution = 5 / 255 = 19.6mv
0V – 0000 0000 - 00H; 0000 0010
2.5V – 0111 1111 – 7F H
3V – 1001 1001 – 99H
5- 1111 1111 – FFH
Interfacing DAC 0800 with 8086

V ref = 5V ; 2.5K, Iref= Vref/2.5K = 2mA

The analog output voltage is Iout x Rf
Iout = [(Digital Input) 10 / 256 ] x Iref
Binary input = 0000 0100=4
= 4/256 = .0156x2mA= .000312
Analog output voltage = Iout x Rf
= .000312 x 2.5K = .078V
For example , 0111 1111 – 7F -127
= 2.48V
1111 1111 – FF

00H- 0v—FFh-5v