EC8691 - MICROPROCESSORS AND

MICROCONTROLLERS

U Vinothkumar
Asst Prof
Dept of ECE
Dr.N.G.P.Institute of Technology
Coimbatore.
UNIT III - I/O INTERFACING (9Hrs)

Memory Interfacing and I/O interfacing - Parallel communication

interface – Serial communication interface – D/A and A/D
Interface - Timer – Keyboard /display controller – Interrupt
controller – DMA controller – Programming and applications Case
studies: Traffic Light control, LED display , LCD display, Keyboard
display interface and Alarm Controller.

2
Memory mapped I/O:

• It is a way to exchange data and instructions between a CPU and

peripheral devices attached to it.

• Memory mapped IO is one where the processor and the IO device

share the same memory location(memory), i.e., the processor and
IO devices are mapped using the memory address.

I/O mapped I/O:

 I/O mapped I/Os have a separate address space from the

memory. So, total addressed capacity is the number of I/Os
connected and a memory connected.

 Separate I/O-related instructions are used to access I/Os. A

separate signal is used for addressing an I/O device.

3
Difference Between Memory mapped I/O and I/O mapped I/O

4
 8255 (PPI)
Parallel Communication Interface

5
 8255 – Parallel Communication Interface

The Features of 8255 PPI are namely,

1. The 8255A is a widely used, programmable, parallel I/O device.

2. It can be programmed to transfer data under various conditions,

from simple I/O to interrupt I/O.

3. It operates on +5v power supply. It is compatible with all Intel

and most other microprocessors.

4. It is completely TTL compatible.

5. It has three 8-bit ports : Port A, Port B, and Port C, which are

arranged in two groups of 12 pins.

6
 Features cont……
6. PA and PCU are called Group A ports and PB and PCL are called
Group B ports. (i.e. port c is divided in to two, 4 bit ports PCU
and PCL)

7. Each port has an unique address, and data can be read from or
written to a port.

8. In addition to the address assigned to the three ports, another

address is assigned to the control register into which control
words are written for programming the 8255 to operate in
various modes.

9. It Operates in 2 modes i) BSR mode ii) I/O mode.

10. Bit set/reset mode allows setting and resetting of individual bits
of Port C.

7
 Features cont……

11. I/O mode is further divided into 3 modes.

(i) Mode 0 : Simple I/O mode.

(ii) Mode 1 : I/O with Handshake.

(iii) Mode 2 : Bi-directional I/O data transfer.

12. All I/O pins of 8255 has 2.5 mA DC driving capacity (i.e. sourcing
current of 2.5 mA).

8
9
Data Bus Buffer:
It is also called as tri-state bi-directional buffer

It is used to interface the internal data bus of Pin Diagram of

8255 Microprocessor to the system data bus.

Input or Output instructions executed by the CPU either Read

data from, or Write data into the buffer.

Output data from the CPU to the ports or control register, and
input data to the CPU from the ports or status register are all
passed through the buffer.

Read / Write Control Logic:

The control logic block accepts control bus signals as well as
inputs from the address bus, and issues commands to the
individual group control blocks (Group A control and Group B
control).

10
Read / Write Control Logic: Cont…..

It issues appropriate enabling signals to access the required

data/control words or status word.

The input pins for the control logic section are A1-A0, RD, WR,
CS.

11
Group A and Group B Controls: Cont…..

• Each of the Group A and Group B control blocks receives control

words from the CPU and issues appropriate commands to the
ports associated with it.
• The Group A control block controls Port A and PC7-PC4 while
the Group B control block controls Port B and PC3-PC0.

Port A : This has an 8-bit latched and buffered output and an 8-

bit input latch. It can be programmed in three modes: mode 0,
mode 1 and mode 2.

Port B : This has an 8-bit data I/O latch/ buffer and an 8-bit
data input buffer. It can be programmed in mode 0 and mode 1.

Port C : This has one 8-bit unlatched input buffer and an 8-bit
output latch/buffer. Port C can be splitted into two parts and each
can be used as control signals for ports A and B in the handshake
mode. It can be programmed for bit set/reset operation.

12
Pin Diagram of 8255

13
 Pin Diagram: cont……

D0-D7: It is used to transfer data and control word 8086 to 8255

and to receive data or status word from 8255 to 8086.

PA0-PA7 & PB0-PB7: It is an 8bit bidirectional I/O pins used to

send data to output device or receive data from input device. It
functions as 8bit data output latch/buffer when used in output mode
and 8bit data input buffer when used in input mode.

PC0-PC7: It is an 8bit bidirectional I/O pins divided into 2 groups

PCL (PC0-PC3) and PCU (PC4-PC7). These pins can be used
individually for data transfer or used as handshake signals.

RD (Read): When this signal is low, CPU can read the data in the
ports or status word, through the data bus buffer.

WR (Write): When this signal is low, CPU can write data on the
ports or in the control register, through the data bus buffer.

CS (Chip select): This is an active low signal which enables the data
transfer operation between 8086 and 8255.
14
 Pin Diagram: cont……

RESET: This is an active high signal used to reset 8255.

(When this RESET input is high, the control register is cleared and all
the ports are set to the input mode.)

A1-A0 (Addr. Lines): These input signals along with RD and WR

inputs control the selection of control and status word registers or
one of the 3 ports.

15
 OPERATING MODES OF 8255

• There are two basic operating modes of 8255:

– Bit Set Reset (BSR) Mode
– Input/ Output Mode

Bit Set-Reset (BSR) Mode:

16
Bit Set-Reset (BSR) Mode:

 The individual bits of Port C can be set or reset by sending out a

single OUT instruction to the control register.

 The eight possible combinations of the states of bits D3 –

D1 (B2 B1 B0) in the Bit Set-Reset format (BSR) determine
particular bit in PC0 – PC7 being set or reset as per the status of
bit D0.

 The BSR word can also be used for enabling or disabling interrupt
signals generated by Port C when the Pin Diagram of 8255
Microprocessor is programmed for Mode 1 or 2 operation.

17
I/O Modes:

18
I/O Modes:

 The control words for both modes are loaded into the same
control register, with bit D7 used for specifying whether the word
loaded into the control register is a I/O mode or Bit Set-Reset
mode.

 Mode 0 (Simple input/output):

In this mode, Ports A, B and C can be configured as simple input
or output ports by writing the appropriate control word in the
control word register.
The input/output features in Mode 0 are as follows :
 Outputs are latched.
 Inputs are buffered, not latched.
 Ports do not have handshake or interrupt capability.
For example in mode 0, if Port A and Port B are to operate as
output ports with Port C lower as input, and Port C upper as
output, the control word that will have to be loaded into the
control register will be as follows.

19
 Cont…

 Mode 1 (Input / Output With Handshake):

In this mode, input or output data transfer is controlled by
handshaking signals.
Handshaking signals are used to transfer data between devices .
whose data transfer speeds are not same.
For example, computer can send data to the printer with large
speed but printer can’t accept data and print data with this rate.
So computer has to send data with the speed with which printer
can accept. This type of data transfer is achieved by using
handshaking signals along-with data signals.

20
 Cont…
Mode 1 which supports handshaking has following features.
• Two ports (A and B) function as 8-bit I/O ports. They, can be
configured either as input or output ports.
• Each port uses three lines from Port C as handshake signals.
• The remaining two lines of Port C can be used for simple I/O
functions.
• Input and output data are latched.
• Interrupt logic is supported.

Mode 1 Input Control Signals :

21
 Cont…
STB (Strobe Input) : This is an active low input signal which
indicates CPU that the data to be read is already sent on the port
lines of 8255 port.

IBF (Input Buffer Full) : This is an active high output signal which
indicates to the input device that the input buffer is full and it is
not ready to accept next byte from the input device.

INTR (Interrupt Request) : This is an active high output signal

generated by 8255. A ‘high’ on this output can be used to
interrupt the CPU when an input device is requesting service.

INTE (Interrupt Enable) : It is used to enable or disable INTR

(Interrupt request) signal. If INTE flip-flop is set, the interrupt
request is generated depending on the status of STB and IBF
signals. If INTE flip flop is reset, the interrupt request is not
generated, allowing masking facility for the interrupt.

22
Cont…

23
 Cont…
Mode 1 Output Control Signals :

OBF (Output Buffer Full) : This is an active low output signal, which
indicates the output device that data is available on the output port.
ACK (Acknowledge Input): This is an active low input signal, which
indicates 8255 that the data from port A or Port B has been accepted.
INTR (Interrupt Request) : This is an active high output signal
generated by 8255 A ‘high’ on this output can be used to interrupt the
CPU when an output device has accepted data transmitted by the
CPU.
INTE (Interrupt Enable) : It is used to enable or disable INTR
(Interrupt Request) signal. If INTE flip flop is set, the interrupt
request is generated depending on the status of ACK and OBF signals.
If INTE flip flop is reset, the interrupt request is not generated,
allowing masking facility for the interrupt.
24
 Cont…
 Mode 2 (Bi-directional I/O data transfer):
This mode allows bi-directional data transfer (transmission and
reception) over a single 8-bit data bus using handshaking signals.

This feature is available only in Group A with Port A as the 8-bit

bidirectional data bus; and PC3 – PC7 are used for handshaking
purpose.

In this mode, both inputs and outputs are latched.

Due to use of a single 8-bit data bus for bi-directional data

transfer, the data sent out by the CPU through Port A appears on
the bus connecting it to the peripheral, only when the peripheral
requests it.

The remaining lines of Port C i.e. PC0-PC2 can be used for simple
I/O functions.

25
Cont…

26
 8251 (USART)
Serial Communication Interface

27
 8251 – Serial Communication Interface
Features of 8251 (USART):
1. The Intel 8251A is an universal synchronous and asynchronous
receiver and transmitter.
2. It supports standard synchronous and asynchronous protocol with
5 to 8 Bit character format.
3. It has built in baud rate generator.
4. It allows full duplex transmission and reception.
5. It provides double buffering of data both in the transmission
section and in the receiver section.
6. It provides error detection logic, which detects parity, overrun and
framing errors.
7. It has Modem Control Logic, which supports basic data set control
signals.

28
 Cont…

8. It provides separate clock inputs for receiver and transmitter

sections, thus providing an option of fixing different baud rates for
the transmitter and receiver section.

9. It is compatible with an extended range of Intel microprocessors.

10. It is fabricated in 28 pin DIP package and its all inputs and
outputs are TTL compatible.

11. It is available in standard as well as extended temperature

range.

29
BLOCK DIAGRAM OF 8251

30
 Cont…
Data Bus Buffer :
This tri-state, bi-directional, 8-bit buffer is used to interface Block
Diagram of 8251 Microcontroller to the system data bus. Along with
the data, control word, command words and status information are
also transferred through the Data Bus Buffer.

Read/Write control logic :

This functional block accepts inputs from the system control bus and
generates control signals for overall device operation. It decodes
control signals on the 8086 control bus into signals which controls
the internal and external I/O bus. It contains the control word
register and command word register that stores the various control
formats for the device functional definition.

31
 Cont…
Transmit Buffer :
The transmit buffer accepts parallel data from the CPU, adds the
appropriate framing information, serializes it, and transmits it on the
TxD pin on the falling edge of TxC.
It has two registers : A buffer register to hold eight bits and an
output register to convert eight bits into a stream of serial bits. The
CPU writes a byte in the buffer register, Which is transferred to the
output register when it is empty. The output register then transmits
serial data on the TxD pin.
In the asynchronous mode the transmitter always adds START bit;
depending on how the unit is programmed, it also adds an optional
even or odd parity bit, and either 1, 1 1/2, or 2 STOP bits.
In synchronous mode no extra bits (other than parity, if enable) are
generated by the transmitter.

32
 Cont…
Transmit Control :
It manages all activities associated with the transmission of serial
data. It accepts and issues signals both externally and internally to
accomplish this function.
TxRDY (Transmit Ready ) : This output signal indicates CPU that
buffer register is empty and the USART is ready to accept a data
character. It can be used as an interrupt to the system or, for polled
operation, the CPU can ‘check TxRDY using the status read operation.
This signal is reset when a data byte is loaded into the buffer
register.
TxE (Transmitter Empty) : This is an output signal. A high on this
line indicates that the output buffer is empty. In the synchronous
mode, if the CPU has failed to load a new character in time, TxE will
go high momentarily as SYN characters are loaded into the
transmitter to fill the gap in transmission.
33
 Cont…
TxC (Transmitter Clock) : This clock controls the rate at which
characters are transmitted by USART. In the synchronous mode TxC
is equivalent to the ‘baud rate, and is supplied by the modem. In
asynchronous mode TxC is 1, 16, or 64 times the baud rate. The
clock division is programmable. It can be programmed by writing
proper mode word in the mode set register.

Receiver Buffer:

The receiver accepts serial data on the RxD line, converts this serial
data to parallel format, checks for bits or characters that are unique
to the communication technique and sends an “assembled” character
to the CPU.

34
 Cont…
When 8251 is in the asynchronous mode and it is ready to accept a
character, it looks for a low level on the RxD line. When it receives
the low level, it assumes that it is a START bit and enables an
internal counter, At a count equivalent to one-half of a bit time, the
RxD line is sampled again.

If the line is still low, a valid START bit is detected and the 8251A
proceeds to assemble the character. After successful reception of a
START bit the 8251A receives data, parity and STOP bits, and then
transfers the data on the receiver input register. The data is then
transferred into the receiver buffer register.

In the synchronous mode the receiver simply receives the specified

number of data bits and transfers them to the receiver input register
and then to the receiver buffer register.

35
 Cont…
Receiver Control:
It manages all receiver-related activities. Along with data reception,
it does false start bit detection, parity error detection, framing error
detection, sync detection and break detection.
RxRDY (Receiver Ready) : This is an output signal. It goes high
(active), when the USART has a character in the buffer register and
is ready to transfer it to the CPU. This line can be used either to
indicate the status in the status register or to interrupt the CPU. This
signal is reset when a data byte from receiver buffer is read by the
CPU.
RxC (Receiver Clock) :
This clock controls the rate at which the character is to be received
by USART in the synchronous mode. RxC is equivalent to the baud
rate, and is supplied by the modem.
36
 Cont…
In asynchronous mode RxC is 1, 16, or 64 times the baud rate. The
clock division is programmable. It can be programmed by writing
proper mode word in the mode set register.

Modem Control: The Block Diagram of 8251 has a set of control

inputs and output’s that can be used to simplify the interface to
almost any modem. It provides control circuitry for the generation of
RTS and DTR and the reception of CTS and DSR. In addition, a
general purpose inverted output and a general purpose input are
provided. The output is labeled DTR and the input is labeled DSR.
DTR can be asserted by setting bit 2 of the command instruction;
DSR can be sensed as bit 7 of the status register. When used as a
modem control signal DTR indicates that the terminal is ready to
communicate and DSR indicates that it is ready for communication.

37
Pin Diagram of 8251 (USART)

38
 Cont….
Data Bus (D0-D7) : Bi-directional, tri-state, 8-bit Data Bus. This pin
allow transfer of bytes between the CPU and the 8251.

RD (Read) : A low on this input allows the CPU to read data or

status bytes from 8251.

WR (Write) : A low on this input allows the CPU to write data or

command word to the 8251.

CLK (Clock) : The CLK input is used to generate internal device

timing. The frequency of CLK must be greater than 30 times the
receiver or transmitter data bit rates.

RESET : A high on this input forces the 8251 into an “Idle” mode.
The device will remain at “Idle” until a new set of control words is
written into 8251.

39
 Cont…

C/D (Control /Data) : This input in conjuction with the WR and RD

inputs, informs the 8251A that the word on the Data Bus is either a
data character control word or status information as shown in table.

CS (Chip Select) : A low on this input allows communication

between CPU and 8251.

40
 Cont…
Modem Control Signals:
The Pin Diagram of 8251 Microcontroller has a set of control inputs
and outputs that can be used to simplify the interface to almost any
modem.

DSR (Data Set Ready) : This input signal is used to test modem
conditions such as Data Set Ready.

DTR (Data Terminal Ready) : This output signal is used to tell

modem that Data Terminal is ready.

RTS (Request to Send ) : This output signal is asserted to begin

transmission.

CTS (Clear to Send) : A low on this input enables the 8251A to

transmit serial data if the TxE bit in the command byte is set to a
“one”.

41
 Cont…
Transmitter Signals:
TxD : Transmit data : This output signal outputs a composite serial
stream of data on the falling edge of TxC.

TxRDY (Transmitter Ready) : This output signal indicates the CPU

that the transmitter is ready to accept a data character.

TxE (Transmitter Empty) : This output signal indicates that the

transmitter has no character to transmit.

TxC (Transmitter Clock) : This clock input controls the rate at

which the character is to be transmitted.

42
 Cont…
Receiver Signals:
RxD (Receiver data) : This input receives a composite serial
stream of data on the rising edge of RxC.

RxRDY (Receiver Ready) : This output indicates that the Pin

Diagram of 8251 Microcontroller contains a character that is ready to
be input to the CPU.

RxC (Receiver Clock) :This clock input controls the rate at which
the character is to be received.

SYNDET (Sync Detect)/ BRKDET (Break Detect):

This pin is used in synchronous mode for detection of synchronous
characters and may be used as either input or output.

In asynchronous mode this pin goes high if receiver line stays low for
more than 2 character times. It then indicates a break in the data
stream.
43
D/A and A/D Interface

44
 ADC (Analog to Digital Converter)

What is A/D conversion?

• The process of converting Analog signal to Digital signal is called

as Analog to Digital conversion.

• Since computers only process digital information, they require

digital input. Therefore, if an analog input is sent to a computer,
an analog-to-digital converter (ADC) is required.

• This device can take an analog signal, such as an electrical

current, and digitize it into a binary format that the computer can
understand.

45
 ADC 0808/0809

The ADC0808/0809 are monolithic CMOS devices with an 8-

channel multiplexer. These devices are also designed to operate from
common microprocessor control buses, with tri-state output latches
driving the data bus. It is the fastest technique.

The main features of ADC0808 are :

• 8-bit successive approximation ADC.
• 8-channel multiplexer with address logic.
• The Conversion delay time is 100 μs at a clock frequency of 640
kHz, which is quite low as compared to other converters.
• It eliminates the need for external zero and full-scale
adjustments.
• Easy to interface to all microprocessors.
• It operates on single 5V power supply.
• Output meet TTL voltage level specifications.

46
 Cont….
Pin Diagram of ADC 0808/0809:

47
 Cont….
Operation of ADC0808:
ADC 0808/0809 has eight input channels.

They are able to convert only positive analog input voltages to their
digital equivalents.

This chip do not contain any internal sample & hold circuit.

To select desired input channel, it is necessary to send 3-bit address

on A, B and C inputs.

48
 Cont….
The address of the desired channel is sent to the multiplexer
address inputs through port pins.

After at least 50 ns, this address must be latched: This can be

achieved by sending ALE signal.

After another 2.5 μs, the start of conversion (SOC) signal must be
sent high and then low to start the conversion process.

To indicate end of conversion ADC 0808/0809 activates EOC signal.

 The microprocessor system can read converted digital word through

data bus by enabling the output enable signal after EOC is activated.

49
Cont….

50
Cont….

51
 Cont….
8255 Control Word: D7 D6 D5 D4 D3 D2 D1 D0
1 0 0 1 1 0 0 0 = 98H
Program:
MOV AL,98H ; Initialize 8255, send AL to control word (CWR)
OUT CWR, AL
MOV AL, 02H ; Select I/P2 as analog I/P
OUT Port B, AL ; Port B as output
MOV AL, 00H ; Give start of conversion pulse to the ADC
OUT Port C, AL
MOV AL, 01H
OUT Port C, AL
MOV AL, 00H
OUT Port C, AL
WAIT: IN AL, Port C ; check for EOC by reading Port C upper &
RCL ; rotating AL content through carry.
JNC WAIT
IN AL, Port A ; if EOC, read digital equivalent in AL
MOV BX,1100 ; Initialize the memory location to store data
MOV [BX],AL ; Store the data
HLT ; stop.

52
Cont….

53
 DAC (Digital to Analog Converter)

What is D/A conversion?

• The process of converting Digital signal to Analog signal is called

Digital to Analog Conversion.

• Since computers only recognize digital information, the output

produced by computers is typically in digital format.

• However, some output devices only accept analog input, which

means a digital-to-analog converter, or DAC, must be used.

• To convert a digital signal to analog signal, it is necessary to treat

each bit in weighted value of current or voltage.

54
 DAC 1408/0808

DAC0808 is a D/A converter IC and is used for converting 8 bit

digital data input to analog signal output. It is a monolithic IC
featuring a full scale output current settling time of 150 ns while
dissipating only 33 mW with ±5V supplies. The chip accuracy of
conversion is good and power consumption is low.

Features of DAC0808:
• 8 bit parallel digital data input
• Fast settling time (typical value): 150 ns
• Relative accuracy at ±0.19% maximum error
• Full scale current match: ±1 LSB
• Non-inverting digital inputs are TTL and CMOS compatible
• High speed multiplying input slew rate: 8 mA/μs
• Power supply voltage range: ±4.5V to ±18V
• Low power consumption: 33 mW@ ±5V
• Maximum Power dissipation: 1000 mW
• Operating temperature range: 0ºC to +75ºC

55
 DAC – 1408/0808 Cont…

Pin Diagram of DAC 1408/0808:

56
 Cont…

Operation of DAC 1408/0808:

• For working of device DAC0808 we need two voltage sources +5V and
-15V as shown in diagram. This is a major drawback which is
eliminated in modern DAC to make them work from a single power
source.
• Eight digital inputs are given to the chip and are supposed to be in
order from MSB to LSB.
• A +10V power source is connected as reference voltage for the device
and the negative reference is grounded.
• The device takes in parallel 8 bit data from a microcontroller or
microprocessor and converts that data in to analog signal at the
output.
• the analog output from DAC is a current quantity and this needed to
be converted in to voltage parameter for using in application easily.

57
 Cont…

• So to convert the current parameter in to voltage parameter we

will use op-amp circuit as shown in circuit diagram. This op-amp
circuit is called current-to-voltage converter.

• The output analog voltage from op-amp is in linear relation with

input digital value and hence DAC conversion with DAC0808 is
achieved.

58
 Cont…

Interfacing of DAC 0808 to 8086 through 8255

59
 Cont…
8255 Control Word: D7 D6 D5 D4 D3 D2 D1 D0
1 0 0 0 0 0 0 0 = 80H
Program (Triangular Wave):

MOV AL,80H ; Initialize 8255, send AL to control word (CWR)

OUT CWR, AL

START: MOV AL, 00H ; Start rising ramp from 0v by sending 00H to DAC

BACK: OUT Port A, AL ; Port A as output

INC AL ; Increment AL till 5V i.e. FFH

JNZ BACK

MOV AL, FFH ; Start falling ramp from 5v by sending FFH to DAC

BACK1: OUT Port A, AL ; Port A as output

DEC AL ; Decrement AL till 0V i.e. 00H

JNZ BACK1

JMP START

60
 Cont…
8255 Control Word: D7 D6 D5 D4 D3 D2 D1 D0
1 0 0 0 0 0 0 0 = 80H
Program (Sawtooth Wave):

MOV AL,80H ; Initialize 8255, send AL to control word (CWR)

OUT CWR, AL

START: MOV AL, 00H ; Start rising ramp from 0v by sending 00H to DAC

BACK: OUT Port A, AL ; Port A as output

INC AL ; Increment AL till 5V i.e. FFH

JNZ BACK

JMP START

61
 Cont…

8255 Control Word: D7 D6 D5 D4 D3 D2 D1 D0

1 0 0 0 0 0 0 0 = 80H
Program (Square Wave):
MOV AL,80H ; Initialize 8255, send AL to control word (CWR)
OUT CWR, AL
START: MOV AL, 00H ; Send the digital data 00H to DAC
OUT Port A, AL ; Port A as output
CALL DELAY ; Wait for specified time
MOV AL, FFH ; Send the digital data FFH to DAC
OUT Port A, AL ; Port A as output
CALL DELAY ; Wait for specified time
JMP START

Delay program:
DELAY: MVI BX,0FFFH
BACK: DEC BX
JNZ BACK
RET

62
 8253/54
Programmable Interval Timer

63
 8253/54 – Programmable Interval Timer

Features of 8253 / 54 :
1. It has three independent 16-bit down counters.

2. 8254 can handle inputs from DC to 10 MHz and 8253 can handle
inputs from DC to 2 MHz.

3. These three counters can be programmed for either binary or BCD

count.

4. Counter can be programmed in six different modes.

5. It is compatible with almost all microprocessors.

6. 8254 has a powerful command called READ BACK command,

which allows the user to check the count value, the programmed
mode, the current mode, and the current status of the counter.

64
BLOCK DIAGRAM OF 8253/54 Timer

65
Pin diagram of 8253 Timer

66
 Cont….
Data Bus Buffer:
• It is a tri-state, bi-directional, 8-bit buffer, which is used to interface
the 8253/54 to the system data bus. It has three basic functions −
• Programming the modes of 8253/54.
• Loading the count registers.
• Reading the count values.

Read/Write Logic:
• It includes 5 signals, i.e. RD, WR, CS, and the address lines A0 & A1.
In the peripheral I/O mode, the RD and WR signals are connected to
IOR and IOW, respectively. In the memory mapped I/O mode, these
are connected to MEMR and MEMW.
• Address lines A0 & A1 of the CPU are connected to lines A0 and A1 of
the 8253/54, and CS is tied to a decoded address. The control word
register and counters are selected according to the signals on lines
A0 & A1 .
67
 Cont…

A1 A0 FUNCTION
0 0 Counter 0
0 1 Counter 1
1 0 Counter 2
1 1 Control Word Register
X X No selection

Control word register:

•It contains the programmed information that is sent to the device
from the microprocessor.

•This register is accessed when lines A0 & A1 are at logic 1.

•It is used to write a command word, which specifies the counter to

be used, its mode of operation, and either a read or write operation.

68
 Cont…
Following table shows the result for various control inputs,
Selection
A1 A0 RD WR CS Function
Mode

Counter 0 0 0 1 0 0 Write Counter 0

Selected
0 0 0 1 0 Read Counter 0

Counter 1 0 1 1 0 0 Write Counter 1

Selected
0 1 0 1 0 Read Counter 1

Counter 2 1 0 1 0 0 Write Counter 2

Selected
1 0 0 1 0 Read Counter 2

Control word
1 1 1 0 0 Write Control Word
register

69
 Cont…

Counters:

• These three functional blocks are identical in operation.

• Each counter consists of a single, 16 bit, pre-settable, down

counter.
• The counter can be operated in either binary or BCD.

• Its input and output is configured by the selection of modes

stored in the control word register.

• The programmer can read the contents of any of the three

counters without disturbing the actual count in process.

• Each counter has 3 logical lines CLK, Gate and OUT. Clock and
Gate are input lines and OUT is the output signal.

70
 Operating Modes of 8253 Timer

8253 Timer can be operated in six different operating modes. These

six different modes are denoted as mode0, mode1, mode2, mode3,
mode4 and mode5. These modes are described as follows,

MODE 0 - Interrupt on Terminal Count

•The output will be initially low after the mode set operation.
•Once the count value is loaded into the selected count register the
output will remain low and the counter will starts counting down.
•When the counter reaches 0 the output will go high and remain high
until the selected counter is reloaded with new value or the same
value.
•Gate has no effect on OUT.

71
 Cont…

MODE 1 - Programmable One-Shot or Retriggerable One-Shot

•The output will be initially high.
•Once the counter has been loaded, the output will go low following
the rising edge at the Gate input.
•Once terminal count has been reached the output will go high and
remain high until the next rising edge at the Gate input.

72
 Cont…
MODE 2 - Rate Generator
•It is a standard divide-by-N counter.
•The output will be initially high.
•The output will go low for one clock pulse before the terminal count.
•The output then goes high, the counter reloads the initial count and
the process is repeated.

73
 Cont…
MODE 3 - Square Wave Generator
•Initially the output is high.
•Mode 3 is similar to mode 2, except that the output will be high for
one half of the count and then low for the other half if the count is
even.
•If the count is ODD, the output will be high for (n+1)/2 and low for
(n-1)/2 counts.

74
 Cont…
MODE 4 - Software Triggered Strobe
•After the mode is set the output will be high.
•Once the count is loaded it will start counting, and once terminal
count is reached (i.e.) when counter equals to ‘0’.
•The output will go to a logical ‘0’ for one clock period and then
returns to a logical ‘1’.

75
 Cont…
MODE 5 - Hardware Triggered Strobe
•This mode is similar to mode 4.
•After the mode is set the output will be high.
•It will wait for a hardware trigger signal (i.e.) rising edge of the Gate
input before starting to count.
•Modes 1 and 5 require the 8253 gate pin to go ‘high’ in order to
start counting.
•Once terminal count is reached the output will go to a logical ‘0’ for
one clock period and then returns to a logical ‘1’.

76
 Cont…

Control word format of 8253 Timer

77
 8279
Keyboard/Display Controller

78
 8279 Keyboard/Display Controller

Features of 8279:

1. It provides a scanned interface to a 64-contact key matrix, with

two more keys CONTROL and SHIFT.

2. It provides three input modes for keyboard interface,

• Scanned Keyboard Mode

• Scanned Sensor Matrix Mode.

• Strobed Input Mode.

3. It has built-in hardware to provide key debounce.

4. It allows key depressions in 2 key lockout or N-key rollover mode,

which eliminates software required to implement 2 key lockout and
N-key rollover

5. The interrupt output of 8279 can be used to tell CPU that the
keypress is detected. This eliminates the need of software polling.
79
 Cont…
6. It provides 8 byte FIFO RAM to store keycodes. This allows to store 8
key board inputs when CPU is busy in performing his own
computation.
7. It provides multiplexed display interface with blanking and inhibit
options.
8. It provides sixteen byte display RAM to store display codes for 16
digits, allowing to interface 16 digits.
9. In auto increment mode, address of display RAM and FIFO RAM is
incremented automatically which eliminates extra command after
each read/write operation to access successive locations of display
RAM and FIFO.
10. It provides two output modes for display interface. Left Entry
(typewriter type) Right Entry (calculator type).
11. Simultaneous keyboard and display operation facility allows to
interleave keyboard and display software.

80
BLOCK DIAGRAM OF 8279 Keyboard/Display Controller

81
 Cont….
It consists of four main sections,
1. CPU interface and control section
2. Scan section
3. Keyboard section
4. Display section.

1. CPU interface and control section:

Data Buffers:
The data buffers are 8-bit bi-directional buffers that connect the
internal data bus to the external data bus.

I/O Control:
The I/O control section uses the A0, CS, RD and WR signals to
control data flow to and from the various internal registers and
buffers.
The data flow to and from the 8279 is enabled only when CS = 0;
otherwise the 8279 signals are in a high impedance state.
When A0 is logic 0 data is transferred and when A0 is logic 1
command word or status word is transferred. RD and WR determine -
the direction of data flow through the data buffers.
82
 Cont…

Control and Timing Registers:

The control and timing registers store the keyboard and display
modes and other operating conditions programmed by the CPU.
The modes are programmed by sending the proper command on the
data lines with A0 = 1.
The command is latched on the rising edge of WR.
The command is then decoded and the appropriate mode/function is
set.

83
 Cont…
Timing Control:
The timing control consists of the basic timing counter chain.
The first counter is divided by N prescaler that can be programmed
to give an internal frequency of 100 kHz.
The other counters divide down the basic internal frequency, to
provide the proper keyscan, row scan, keyboard matrix scan, and
display scan times.
The internal frequency of 100 KHz gives the internal timings as
shown in the table below.

84
 Cont…
2. Scan Section (Scan counter):
The scan section has a scan counter which has two modes :
Encoded mode and decoded mode.
Encoded Mode: In the encoded mode, the scan counter provides a
binary count from 0000 to 1111 on the four scan lines (SC3 — SC0) with
active high outputs. This binary count must be externally decoded to
provide 16 scan lines. Display can use all 16 scan lines to interface 16
digit 7-segment display, but keyboard can use only 8 scan lines out of 16
scan lines.
Decoded Mode: In the decoded mode, the internal decoder decodes the
least significant 2 bits of binary count and provides four possible
combinations on the scan lines (SC3 — SC0) :1110, 1101, 1011 and
0111. Thus the output of decoded scan is active low. These four active
low output lines can be used directly to interface 4 digit 7 segment
display, 8 x 4 matrix keyboard, eliminating the external decoder.

85
 Cont…

3. Keyboard Section:

This section consists of return buffers, keyboard debounce and control,

FIFO/sensor RAM and FIFO/sensor RAM status.
These functions depend on selected keyboard mode out of three keyboard
input modes : scanned keyboard, sensor matrix and strobed input.

Return buffers: The 8 return lines (RL7 — RL0) are buffered and latched by
the return buffers during each row scan in scanned keyboard or sensor matrix
mode. In strobed input mode, the contents of the return lines are transferred
to the FIFO RAM on the rising edge of the CNTL/STB line pulse.

Keyboard debounce and control: Keyboard and debounce control is

enabled only when scanned keyboard mode is selected. In the scanned
keyboard mode, return lines are scanned, looking for key closures in that row.
If the debounce circuit detects a close switch, it waits about 10 msec to check
if the switch remains closed. If it does, the address of the switch in the matrix
plus the status of SHIFT and CONTROL keys are transferred to the FIFO RAM.

86
 Cont…
FIFO/Sensor RAM: This is a dual function 8 x 8 RAM. In scanned
keyboard and strobed input modes, it is a FIFO. Each new entry is
written into successive RAM positions and then read in order of entry. In
sensor matrix mode, the memory is referred to as sensor RAM. Each row
of the sensor RAM is loaded with the status of the corresponding row of
sensor in the sensor matrix.

FIFO/sensor RAM status: FIFO RAM status keeps track of the number
of characters in the FIFO and whether it is full or empty. The status logic
also makes IRQ signal high when the FIFO is not empty, which can be
used to interrupt CPU telling that key press is detected and keycode is
available in FIFO RAM.

4. Display section:
The display section consists of display RAM, display address registers and
display registers.

87
 Cont…

Display RAM: It is 16 x 8 RAM, which stores the display codes for 16

digits. It can be accessed directly by CPU. In decoded mode, 8279 uses
only first four locations of display RAM. In encoded mode, Block Diagram
of 8279 uses first eight locations for 8 digit display and all 16 locations
for 16 digits display.

Display address registers: The display address registers hold the

address of the byte currently being written or read by the CPU and scan
count value. The read/write addresses are programmed by CPU
command. If set in auto increment mode, address in the address register
is incremented for each read or write.

Display registers: Display registers are two 4-bit registers A and B.

They hold the bit pattern of character to be displayed. The contents of
display registers A and B can be blanked and inhibited individually.

88
Pin diagram of 8279 Keyboard/Display Controller

89
 Cont…

Data Bus Lines, DB0 - DB7 - These are 8 bidirectional data bus lines
used to transfer the data to/from the CPU.

CLK - The clock input is used to generate internal timings required

by the microprocessor.

RESET - As the name suggests this pin is used to reset the

microprocessor.

CS Chip Select - When this pin is set to low, it allows read/write

operations, else this pin should be set to high.

A0 - This pin indicates the transfer of command/status information.

When it is low, it indicates the transfer of data.

RD, WR - This Read/Write pin enables the data buffer to

send/receive data over the data bus.

90
 Cont…

IRQ - This interrupt output line goes high when there is data in the
FIFO sensor RAM. The interrupt line goes low with each FIFO RAM
read operation. However, if the FIFO RAM further contains any key-
code entry to be read by the CPU, this pin again goes high to
generate an interrupt to the CPU.

Vss, Vcc - These are the ground and power supply lines of the
microprocessor.

SL0 − SL3 - These are the scan lines used to scan the keyboard
matrix and display the digits. These lines can be programmed as
encoded or decoded, using the mode control register.

RL0 − RL7 - These are the Return Lines which are connected to one
terminal of keys, while the other terminal of the keys is connected to
the decoded scan lines. These lines are set to 0 when any key is
pressed.

SHIFT - The Shift input line status is stored along with every key
code in FIFO in the scanned keyboard mode. Till it is pulled low with
a key closure, it is pulled up internally to keep it high

91
 Cont…
CNTL/STB - CONTROL/STROBED I/P Mode - In the keyboard
mode, this line is used as a control input and stored in FIFO on a key
closure. The line is a strobe line that enters the data into FIFO RAM,
in the strobed input mode. It has an internal pull up. The line is
pulled down with a key closure.

BD - It stands for blank display. It is used to blank the display during

digit switching.

OUTA0 – OUTA3 and OUTB0 – OUTB3 - These are the output ports
for two 16x4 or one 16x8 internal display refresh registers. The data
from these lines is synchronized with the scan lines to scan the
display and the keyboard.

92
 8259
Programmable interrupt
controller

93
 8259 – Programmable interrupt controller
Features:
1. It can manage eight priority interrupts. This is equivalent to providing
eight interrupt pins on the processor in place of INTR pin.
2. It is possible to locate vector table for these additional interrupts any
where in the memory map. However, all eight interrupts are spaced at
the interval of either four or eight locations.
3. By cascading nine 8259s it is possible to get 64 priority interrupts.
4. Interrupt mask register makes it possible to mask individual interrupt
request.
5. The 8259A can be programmed to accept either the level triggered or
the edge triggered interrupt request.
6. With the help of 8259A user can get the information of pending
interrupts, in-service interrupts and masked interrupts.
7. The 8259A is designed to minimize the software and real time
overhead in handling multi-level priority interrupts.

94
BLOCK DIAGRAM OF 8259

95
 Cont….
Data Bus Buffer: The data bus buffer allows the 8086 to send
control words to the 8259A and read a status word from the Block
Diagram of 8259 Programmable Interrupt Controller. The 8-bit data
bus buffer also allows the 8259A to send interrupt opcode and
address of the interrupt service subroutine to the 8086.

Read/Write Logic: The RD and WR inputs control the data flow on

the data bus when the device is selected by asserting its chip select
(CS) input low.

Control Logic: This block has an input and an output line. If the
8259A is properly enabled, the interrupt request will cause the
8259A to assert its INT output pin high. If this pin is connected to
the INTR pin of an 8086 and if the 8086 Interrupt Enable (IE) flag is
set, then this high signal will cause the 8086 to respond INTR as
explained earlier.

96
 Cont…
Interrupt Request Register (IRR): The IRR is used to store all the
interrupt levels which are requesting the service. The eight interrupt
inputs set corresponding bits of the Interrupt Request Register upon
service request.

Interrupt Service Register (ISR): The Interrupt Service Register

(ISR) stores all the levels that are currently being serviced.

Interrupt Mask Register (IMR): Interrupt Mask Register (IMR)

stores the masking bits of the interrupt lines to be masked. This
register can be programmed by an Operation Command Word
(OCW). An interrupt which is masked by software will not be
recognized and serviced even if it sets the corresponding bits in
the IRR.

Priority Resolver: The priority resolver determines the priorities

of the bits set in the IRR. The bit corresponding to the highest
priority interrupt input is set in the ISR during the INTA input.

97
 Cont…
Cascade Buffer Comparator: This section generates control signals
necessary for cascade operations. It also generates Buffer-Enable
signals. As stated earlier, the Block Diagram of 8259 Programmable
Interrupt Controller can be cascaded with other 8259s in order to
expand the interrupt handling capacity to sixty-four levels. In such a
case, the former is called a master, and the latter are called slaves.
The 8259 can be set up as a master or a slave by the SP/EN pin.

CAS0— CAS2: For a master 8259, the CAS0-CAS2 pins are output
pins, and for slave 8259, these are input pins. When the 8259 is a
master (that is, when it accepts interrupt requests from other
8259s), the CALL opcode is generated by the Master in response to
the first INTA. The vector address must be released by the slave
8259.
The master sends an identification code of three-bits to select one
out of the eight possible slave 8259s on the CAS0-CAS2 lines. The
slave 8259s accept these three signals as inputs (on their CAS0 –
CAS2 pins) and compare the code sent by the master with the codes
assigned to them during initialization. The slave thus selected (which
had originally placed an interrupt request to the master 8259) then
puts the address of the interrupt service routine during the second
and third INTA pulses from the CPU.

98
 Cont…
SP / EN (Slave Program /Enable Buffer): The SP/EN signal is
tied high for the master. However it is grounded for the slave.

In large systems where buffers are used to drive the data bus, the
data sent by the 8259 in response to INTA cannot be accessed by the
CPU (due to the data bus buffer being disabled).

If an 8259 is used in the buffered mode (buffered or non-buffered

modes of operation can be specified at the time of initializing the
8259), the SP/EN pin is used as an output which can be used to
enable the system data bus buffer whenever the data bus outputs of
8259 are enabled (i.e. when it is ready to send data).

Thus, in non-buffered mode, the SP/EN pin of an 8259 is used to

specify whether the 8259 is to operate as a master or as a slave, and
in the buffered mode, the SP/EN pin is used as an output to enable
the data bus buffer of the system.

99
8257 DMA Controller

100
 8257 DMA Controller

 DMA stands for Direct Memory Access.

 It is designed by Intel to transfer data at the fastest rate.

 It allows the device to transfer the data directly to/from memory

without any interference of the CPU.
 Using a DMA controller, the device requests the CPU to hold its
data, address and control bus, so the device is free to transfer
data directly to/from the memory.

 The DMA data transfer is initiated only after receiving HLDA signal
from the CPU.

101
 8257 DMA Controller

How DMA Operations are Performed?

Following is the sequence of operations performed by a DMA −

• Initially, when any device has to send data between the device and
the memory, the device has to send DMA request (DRQ) to DMA
controller.

• The DMA controller sends Hold request (HRQ) to the CPU and waits
for the CPU to assert the HLDA.

• Then the microprocessor tri-states all the data bus, address bus,
and control bus. The CPU leaves the control over bus and
acknowledges the HOLD request through HLDA signal.

• Now the CPU is in HOLD state and the DMA controller has to
manage the operations over buses between the CPU, memory, and
I/O devices.
102
 Cont…
Features of 8257:
Here is a list of some of the prominent features of 8257 −
• It has four channels which can be used over four I/O devices.
• Each channel has 16-bit address and 14-bit counter.
• Each channel can transfer data up to 64kb.
• Each channel can be programmed independently.
• Each channel can perform read transfer, write transfer and verify
transfer operations.
• It generates MARK signal to the peripheral device that 128 bytes
have been transferred.
• It requires a single phase clock.
• Its frequency ranges from 250Hz to 3MHz.
• It operates in 2 modes, i.e., Master mode and Slave mode.
103
BLOCK DIAGRAM OF 8257 DMA Controller

104
Pin diagram of 8257 DMA Controller

105
 Cont….
DRQ0−DRQ3
• These are the four individual channel DMA request inputs, which
are used by the peripheral devices for using DMA services. When
the fixed priority mode is selected, then DRQ0 has the highest
priority and DRQ3 has the lowest priority among them.

DACKo − DACK3
• These are the active-low DMA acknowledge lines, which updates
the requesting peripheral about the status of their request by the
CPU. These lines can also act as strobe lines for the requesting
devices.

Do − D7
• These are bidirectional, data lines which are used to interface the
system bus with the internal data bus of DMA controller. In the
Slave mode, it carries command words to 8257 and status word
from 8257. In the master mode, these lines are used to send
higher byte of the generated address to the latch. This address is
further latched using ADSTB signal.

106
 Cont…

IOR - It is an active-low bidirectional tri-state input line, which is

used by the CPU to read internal registers of 8257 in the Slave
mode. In the master mode, it is used to read data from the
peripheral devices during a memory write cycle.

IOW - It is an active low bi-direction tri-state line, which is used to

load the contents of the data bus to the 8-bit mode register or
upper/lower byte of a 16-bit DMA address register or terminal
count register. In the master mode, it is used to load the data to
the peripheral devices during DMA memory read cycle.

CLK - It is a clock frequency signal which is required for the internal

operation of 8257.

RESET - This signal is used to RESET the DMA controller by disabling

all the DMA channels.

107
 Cont…
IOR - It is an active-low bidirectional tri-state input line, which is
used by the CPU to read internal registers of 8257 in the Slave
mode. In the master mode, it is used to read data from the
peripheral devices during a memory write cycle.

IOW - It is an active low bi-direction tri-state line, which is used to

load the contents of the data bus to the 8-bit mode register or
upper/lower byte of a 16-bit DMA address register or terminal
count register. In the master mode, it is used to load the data to
the peripheral devices during DMA memory read cycle.

CLK - It is a clock frequency signal which is required for the internal

operation of 8257.

RESET - This signal is used to RESET the DMA controller by disabling

all the DMA channels.

108
 Cont…
Ao - A3 - These are the four least significant address lines. In the
slave mode, they act as an input, which selects one of the
registers to be read or written. In the master mode, they are the
four least significant memory address output lines generated by
8257.

CS - It is an active-low chip select line. In the Slave mode, it enables

the read/write operations to/from 8257. In the master mode, it
disables the read/write operations to/from 8257.

A4 - A7 - These are the higher nibble of the lower byte address

generated by DMA in the master mode.

READY - It is an active-high asynchronous input signal, which makes

DMA ready by inserting wait states.

109
 Cont…

HRQ - This signal is used to receive the hold request signal from the
output device. In the slave mode, it is connected with a DRQ input
line 8257. In Master mode, it is connected with HOLD input of the
CPU.

HLDA - It is the hold acknowledgement signal which indicates the

DMA controller that the bus has been granted to the requesting
peripheral by the CPU when it is set to 1.

MEMR - It is the low memory read signal, which is used to read the
data from the addressed memory locations during DMA read
cycles.

MEMW - It is the active-low three state signal which is used to write

the data to the addressed memory location during DMA write
operation.

ADST - This signal is used to convert the higher byte of the memory
address generated by the DMA controller into the latches.

110
 Cont…
AEN - This signal is used to disable the address bus/data bus.

TC - It stands for ‘Terminal Count’, which indicates the present DMA

cycle to the present peripheral devices.

MARK - The mark will be activated after each 128 cycles or integral
multiples of it from the beginning. It indicates the current DMA
cycle is the 128th cycle since the previous MARK output to the
selected peripheral device.

Vcc - It is the power signal which is required for the operation of the
circuit.

111