EC8691 - MICROPROCESSORS AND

MICROCONTROLLERS

U Vinothkumar
Asst Prof
Dept of ECE
Dr.N.G.P.Institute of Technology
Coimbatore.
UNIT V - INTERFACING MICROCONTROLLER (9Hrs)

Programming 8051 Timers - Serial Port Programming - Interrupts

Programming – LCD & Keyboard Interfacing - ADC, DAC & Sensor
Interfacing - External Memory Interface- Stepper Motor and
Waveform generation - Comparison of Microprocessor,
Microcontroller, PIC and ARM processors.

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8051 TIMER/COUNTERS

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 8051 TIMER/COUNTERS

8051 Machine Cycle Timing:

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 8051 TIMER/COUNTERS
Timer Mode:
• In the timer mode the timer register is incremented in every machine
cycle.
• Counting the number of machine cycles are done in the timer mode.
• Since a machine cycle consists of 12 clock periods, the counting is
1/12 of the oscillator frequency.
Counter mode:
• In the counter function, the register is incremented in response to 1
to 0 transition on the external input pin T0 or T1.
• T0 is the external input for counter 0 and T1 is for counter 1.
• T0 or T1 external inputs are sampled during S5 P2 of every machine
cycle. If it is high in one machine cycle and low in next machine cycle,
the count is incremented during S3 P1 of next machine cycle following
the one in which the valid transition (1 to 0) was detected.

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 8051 TIMER/COUNTERS
• Since, counter mode requires 2 machine cycles (24 clock periods)
to recognize a 1 to 0 transition, the maximum count rate is 1/24
of the oscillator frequency.

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8051 TIMER/COUNTERS

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8051 TIMER/COUNTERS

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8051 TIMER/COUNTERS

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 Cont…
Operating Modes of Timer/Counter in 8051 Microcontroller

Mode 0 ( 13-bit TIMER/COUNTER MODE):

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 Cont…

Mode 0 ( 13-bit TIMER/COUNTER MODE):

• In mode 0, timer register is configured as 13 bit register. The
same operation is valid for timer 1 also with slight modifications in
the registers.
• The 13-bit register consists of all the 8 bits of TH0 (or TH1) and
the lower 5 bits of TL0 (or TL1), if timer 0 or timer 1 is used in
this mode.
• The 13-bit timer register can hold values between 0000H to
1FFFH in 8 bits of TH0 and 5 bits of TL0.
• Whenever the timer/counter0, rolls over from all 1’s to all 0’s, it
sets the timer interrupt flag TF0.
• The counted input is enabled into timer only if timer 0 run bit
(TR0)=1 and either GATE =0 or INT=1. TR0 is the control bit in
the TCON register. GATE bit is in TMOD register.
• Mode 0 operation is the same for timer 1 also. Substitute
TR1,TF1,TL1,TH1 and INT1 for the corresponding timer 1 signals
(instead of TR0,TF0,TL0,TH0 and INT0).

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 Cont…

Mode 1 ( 16-bit TIMER/COUNTER MODE):

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 Cont…

Mode 1 ( 16-bit TIMER/COUNTER MODE):

• Mode 1 operation is same as that of mode 0 operation, except the
timer register is being programmed as 16 bit register.

• Both TH0 and TL0 are considered as 8 bit registers. Therefore, it

allows values of 0000H to FFFFH.

• Whenever the timer roll over from all 1’s (FFFFH) to all 0’s
(0000H), timer interrupt flag TF0 is set.

• Mode 1 operation is applicable for timer 1 also.

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 Cont…

Mode 2 ( Auto Reload MODE):

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 Cont…
Mode 2 ( Auto Reload MODE):
• Mode 2 configures the timer register as an 8 bit register and
allows values of 00H to FFH to be loaded in to timer register TH0.
• After TH0 is loaded with a 8 bit initial value, the 8051 controller
copies the content of TH0 in to TL0.
• Once timer is started, the TL0 content is incremented each time
during counting operation. TL0 counts up until it reaches its
maximum limit of FFH.
• Whenever TL0 rolls over from FFH to 00H, TL0 sets TF0 flag and
also reloads TL0 with the content of TH0.
• Thus TL0 (8-bit register) is reloaded automatically with the initial
value kept in the TH0 register and repeat the process.
• Reload operation does not change the TH0 value. Mode 2
operation is same for timer/counter 1 also.
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 Cont…
Mode 3 (Two 8-Bit counters):

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 Cont…

Mode 3 (Two 8-Bit counters):

• In mode 0, 1 and 2, timer 0 and 1 can be programmed independently
in the similar mode as that of the another timer. But this is not valid
for mode 3 operation.
• Mode 3 is only for timer 0. In mode 3, TR1 control bit of timer 1 and
the timer 1 interrupt flag bit TF1 are used by timer 0. because of
these flags of timer1, when timer 0 is operated under mode 3, timer 1
should not be operated in any other mode.(Mode0 through2).

• Timer 0 in mode 3 is programmed as two separate 8 bit timers TL0

and TH0. the operation of timer 0, under mode 3 is shown in figure.

• TL0 uses the timer 0 control bits: C/T, GATE, TR0, INT0 and TF0.

• TH0 uses the timer1 run bit (TR1) and timer 1 interrupt flag (TF1) of
timer 1. Thus TH0 controls the timer 1 interrupt.

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 Serial Communication Interface

• Serial communication is used for transferring data between two

computer systems.

• In serial communication a single data line can be used instead of 8-Bit

data lines as that of parallel communication. This makes the serial
communication much cheaper.
• Serial communication uses either asynchronous data transfer or
synchronous data transfer method.

• In synchronous method a block of data is transferred at a time.

• While in asynchronous method a single byte is transferred at a time.

• Serial transmission and reception can be easily achieved by UART

devices.
• For serial communication 8051 controller has a built in UART with
three special function registers SBUF, SCON and PCON.

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 Cont…
• SBUF register is used to hold the data for transmission and reception.
• SCON register is used to control the serial data communication and
PCON register is used to control the data rates of serial
communication.
• RXD and TXD lines are used for reception and transmission of serial
data. In 8051 controller Port3.0 acts as RXD pin and port 3.1 acts as
TXD pin.
• SBUF register is physically two register. One register is write only and
it is used to hold data during transmission through TXD pin. The other
register is read only and it holds received data from external devices
through RXD pin.
• The serial port of 8051 microcontroller supports FULL DUPLEX
communication (i.e.) it can simultaneously Transmit or receive data
from an external device.
• Serial port can be programmed in 4 types of operating modes termed
as mode 0, mode 1, mode 2 and mode 3.
• In MODE 0 and 2 , the baud rate of serial communication is fixed. In
MODE 1 and 3 , the baud rate of serial communication is variable and
depends on the value loaded in TIMER 1 [TH1] .

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 Cont…
SCON Register:

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 Cont…
PCON Register:

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 Cont…
Mode 0 (Simple shit register mode):
• In mode 0, serial data transmission and reception both the
functions are done through RXD pin.
• TXD pin acts as a shift register clock and the rising edge of the
clock is considered as the active clock edge.
• Baud rate of mode 0 is fixed to 1/12 of oscillator frequency
(Fosc/12).
• 8-Bits of data are transmitted or received with LSB first.
• Shift register is a synchronous mode.
• Reception is initiated only if RI=0 and REN=1.
• Timing diagram for Mode 0 – Shift register mode is shown below.

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 Cont…

Mode 1 (Standard UART):

• Mode1 is a standard asynchronous serial communication mode.
• 10-Bits are transmitted through TXD or received through RXD.
• Each frame consists of 10-bits. With in 10-bits frame, 8-bits are
data bits with a stop bit (1) and a start bit (0).
• Start bit is active (one bit period) low signal and a stop bit is a
active high signal (one bit period).
• The mode 1 data frame format is shown below.

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 Cont…

• TXD pin transmits all data (10-bits) and RXD pin receives the data.
SBUF register becomes a 10-bit full duplex receiver/transmitter that
may receive and transmit data at the same time.
• Interrupt flag TI is set once if all the 10-bits have been transmitted.
• On transmission, the user write 8-bit data into SBUF register. The
serial logic loads 1 in to the 9th bit position of the transmit shift
register. i.e., stop bit is attached to the user data.
• Reception is triggered by the falling edge of the start bit if REN=1 and
continues until it receives the stop bit (0 level). Received data bits is
loaded into SBUF only if RI=0 and SM2 bit is 0.
• RI set to 0 implies that the program has read the previous data byte
and is ready to receive the next data.
• On reception of the original 10-bits, the start bit is discarded , the
eight data bit to SBUF register and the stop bit is passed to RB8 bit of
SCON register. RI is made to 1, indicating a new byte has been
received.

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 Cont…

Mode 2 (Multiprocessor mode):

• Mode 2 supports asynchronous serial data transfer method. 11-
bits are transmitted through TXD or received through RXD.
• Mode 2 is similar to mode 1, except 11-bits are transmitted per
frame. 11-bits frame consists of one start bit (0), 8-data bits,
programmable 9th bit and a stop bit (1).
• On transmission, the programmable 9th bit can be assigned the
value of either 0 or 1 and the 8-data bit is loaded into SBUF by
the programmer.
• The 9th data bit is copied from TB8 in SCON register. TB8 can also
be a copy of parity bit of PSW.
• On reception, the 9th bit goes into RB8 of SCON register of SFR.
Start and stop bits are discarded.

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 Cont…

• The 11-bits asynchronous data frame format is shown below.

• Mode 2, baud rate is programmed to either 1/32 or 1/64 of

oscillator frequency. Baud rate in mode 2 depends on the value of
bit SMOD in PCON register. If SMO=0, the baud rate is 1/64 the
oscillator frequency. If SMOD=1, the baud rate is 1/32 the
oscillator frequency.

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 Cont…

Mode 3 :
• Mode 3 is same as mode 2 in all aspects except the baud rate.
Mode3 supports variable baud rate.

• Baud rate for mode 3 is calculated similar to the baud rate

calculation of mode 1 using timer 1.
• 11-bits are transmitted through TXD or received through RXD. 11
bits consists of a start bit (0), 8-data bits (LSB first), a
programmable 9th bit and a stop bit (1).

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 Interrupts of 8051
• The 8051 microcontroller supports five interrupts sources. With in
these 5 interrupt sources, two are external interrupts and three are
internal interrupts(on chip resources).

• Internal interrupts are Timer 0 interrupt, Timer 1 interrupt and Serial

port interrupt.
• External interrupts are INT 0 and INT 1.

• Any interrupt can cause the 8051 to perform a Hardware call to an

interrupt service routine (ISR) that is located at the predetermined
absolute address in program memory.

• The 8051 interrupts and its vector address locations are shown below,

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 Cont…
• The external interrupt 0 (INT 0) has a total of 8 bytes from location
0003H to 000AH for its ISR.
• Similarly, a total of 8 bytes from location 000BH to 0012H is reserved
for Timer 0 interrupt (TF0). In the same way, 8 bytes are assigned for
each ISR in the program memory.
• If the ISR is short enough to fit in the memory space allocated to it,
then it is placed in those location with the starting address pointed by
the interrupt vector table.
• If the ISR is too lengthy to fit in assigned 8 bytes then LJMP
instruction is placed in the vector table address to point to the
starting address of the ISR.

Activation of the Interrupt:

• The microcontroller finishes the current instruction execution and
saves the next instruction address (PC content) on the stack.
• It also saves the current status of all the interrupts internally.
• Then it jumps to a fixed location in the memory called the interrupt
vector table that holds the address of the interrupt service routine.

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 Cont…
• The microcontroller gets the address of the ISR from vector table
and jumps to that location and it starts the execution of ISR
instruction until it reaches the last instruction of the ISR which is
RETI (return from interrupt).
• Upon executing the RETI instruction, the microcontroller returns
to the place where it was interrupted in the main program.
• First it gets the program counter (PC) address from the stack by
popping the top 2 bytes of the stack into the PC and then it starts
to execute from that location.

Timer Flag interrupts:

• When the timer/counter overflows, the corresponding timer flag
TF0 or TF1 is set to 1.
• The flag is cleared to 0, when the resulting interrupt generates a
program call to the appropriate timer subroutine in memory.

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 Cont…
Serial port interrupt:
• In the serial port of 8051, if a data byte is received or if a data
byte is transmitted an interrupt bit R1 is set or T1 is set in SCON
register.
• Both RI and TI ORed together to provide a single interrupt to the
processor.
• RI interrupt is used for serial reception and TI is used for serial
transmission.
• RI and TI are not cleared when the interrupt generated program
call is made by the processor.
• The program that handles serial data communication must reset
RI or TI to enable the next data communication operation.

External Interrupts:
• Pins INT0 and INT1 are used by external circuitry.
• Inputs on these pins can set the interrupt flags IE0 and IE1 in the
TCON register to 1 by two different methods.

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 Cont…
• The IEx flags may be set when the INTx pin signal reaches a low
level or the flags may be set, when high to low transition takes
place on the INTx pin.
• Bits IT0 and IT1 in TCON register program the INTx pins for low
level interrupt when set to 0 and program the INTx pins for
transition type, when it is set to 1.
• Flags IEx will be reset when the transition generated interrupt is
accepted by the controller and the ISR is accessed.

Reset:
• When the reset pin is activated, the 8051 jumps to address
location 0000H. This is called as power on reset.
• Reset pin can be considered as a sixth interrupt source of 8051
controller.
• Reset may be directed to any RAM space by placing appropriate
LJMP instruction at location 0000H.

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 Cont…
Interrupt Structure of 8051 Microcontroller:
The 8051 interrupt structure with all the five interrupts sources,
IE register, IP register and the Polling sequence is shown below.

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 Cont…
• The external interrupts INT0 and INT1 can be either Level - activated or
transition activated, depending on bit status IT0 and IT1 in TCON
register.
• If IT0 or IT1 bit is 0, then the corresponding external interrupt is low
level activated and if IT0 or IT1 bit is 1, the corresponding external
interrupt is transition activated (1 to 0 is valid transition).
• When an external interrupt is generated and when service routine is
vectored, the flag (IEx) that actually generates the external interrupts
must be cleared by the on chip hardware automatically if the interrupt is
transition activated.
• If the interrupt was level activated, then the external requesting source
is needed to clear the IE flag rather than on chip hardware.
• Timer 0 and Timer 1 are actually generated by TF0 and TF1 flags of
TCON register.
• The TF0 and TF1 flags are set, when the corresponding Timer 0 and
Timer 1 roll over's from all zero’s to all one’s.
• When the timer interrupt is generated the flags that generates these
interrupt is cleared by the on chip hardware automatically.
• Serial port interrupt is generated for each transmission and reception of
serial data. It is generated by the logical OR of RI and TI flags of SCON
register.

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 Cont…
Interrupt Enable (IE) Register:
This register is responsible for enabling and disabling the
interrupt. It is a bit addressable register in which EA must be set to one
for enabling interrupts. The corresponding bit in this register enables
particular interrupt like timer, external and serial inputs. In the below IE
register, bit corresponding to 1 activates the interrupt and 0 disables the
interrupt.

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 Cont…
Interrupt Priority (IP) Register:
It is also possible to change the priority levels of the interrupts
by setting or clearing the corresponding bit in the Interrupt priority (IP)
register as shown in the figure. This allows the low priority interrupt to
interrupt the high-priority interrupt, but prohibits the interruption by
another low-priority interrupt. Similarly, the high-priority interrupt cannot
be interrupted. If these interrupt priorities are not programmed, the
microcontroller executes in predefined manner and its order is INT0, TF0,
INT1, TF1, and SI.

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