EC8691 - MICROPROCESSORS AND

MICROCONTROLLERS

U Vinothkumar
Asst Prof
Dept of ECE
Dr.N.G.P.Institute of Technology
Coimbatore.
UNIT II 8086 SYSTEM BUS STRUCTURE (9Hrs)
8086 signals – Basic configurations – System bus timing –
System design using 8086 – I/O programming – Introduction to
Multiprogramming – System Bus Structure – Multiprocessor
configurations – Coprocessor, Closely coupled and loosely
Coupled configurations – Introduction to advanced processors.

2
8086 Pin
Diagram

(MIN
MODE)
(MAX MODE)

3
8086 Microprocessor
Pins and Signals Common signals

AD0-AD15 (Bidirectional)
Address/Data bus
Low order address bus; these are
multiplexed with data.

AD0-AD15 Acts as address bus during 1st

part of the machine cycle and data bus
for the remaining part of the machine
cycle.

When AD lines are used to transmit

memory address the symbol A is used
instead of AD, for example A0-A15.

When data are transmitted over AD lines

the symbol D is used in place of AD, for
example D0-D7, D8-D15 or D0-D15.

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8086 Microprocessor
Pins and Signals Common signals

A16/S3, A17/S4, A18/S5, A19/S6

High order address bus. These are
multiplexed with status signals.

During 1st part of the machine cycle

these are used to output upper 4 bits of
address. During the remaining part of the
machine cycle these are used to output
status.

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8086 Microprocessor
Pins and Signals Common signals

BHE (Active Low)/S7 (Output)

Bus High Enable/Status

It is used to enable data onto the most

significant half of data bus, D8-D15. 8-bit
device connected to upper half of the
data bus use BHE (Active Low) signal. It
is multiplexed with status signal S7.

MN/ MX

MINIMUM / MAXIMUM

This pin signal indicates what mode the

processor is to operate in.

RD (Read) (Active Low)

The signal is used for read operation.

It is an output signal.
It is active when low.
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8086 Microprocessor
Pins and Signals Common signals

TEST

𝐓𝐄𝐒𝐓 input is tested by the ‘WAIT’

instruction.

8086 will enter a wait state after

execution of the WAIT instruction and
will resume execution only when the
𝐓𝐄𝐒𝐓 is made low by an active hardware.

This is used to synchronize an external

activity to the processor internal
operation.

READY

This is the acknowledgement from the

slow device or memory that they have
completed the data transfer.

The signal made available by the devices

is synchronized by the 8284A clock
generator to provide ready input to the
8086.

The signal is active high. 7

8086 Microprocessor
Pins and Signals Common signals

RESET (Input)
Causes the processor to immediately
terminate its present activity.

The signal must be active HIGH for at

least four clock cycles.

CLK
The clock input provides the basic timing
for processor operation and bus control
activity. Its an asymmetric square wave
with 33% duty cycle.

INTR Interrupt Request

This is a triggered input. This is sampled
during the last clock cycles of each
instruction to determine the availability
of the request. If any interrupt request is
pending, the processor enters the
interrupt acknowledge cycle.

This signal is active high and internally

synchronized.

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8086 Microprocessor
Pins and Signals Min/ Max Pins

The 8086 microprocessor can work in two

modes of operations : Minimum mode and
Maximum mode.

In the minimum mode of operation the

microprocessor do not associate with any
co-processors and can not be used for
multiprocessor systems.

In the maximum mode the 8086 can work

in multi-processor or co-processor
configuration.

Minimum or maximum mode operations

are decided by the pin MN/ MX(Active low).

When this pin is high 8086 operates in

minimum mode otherwise it operates in
Maximum mode.

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8086 Microprocessor
Pins and Signals Minimum mode signals

Pins 24 -31

For minimum mode operation, the MN/ 𝐌𝐗 is tied

to VCC (logic high)

8086 itself generates all the bus control signals

DT/𝐑 (Data Transmit/ Receive) Output signal from the

processor to control the direction of data flow
through the data transceivers

𝐃𝐄𝐍 (Data Enable) Output signal from the processor

used as out put enable for the transceivers

ALE (Address Latch Enable) Used to demultiplex the

address and data lines using external latches

M/𝐈𝐎 Used to differentiate memory access and I/O

access. For memory reference instructions, it is
high. For IN and OUT instructions, it is low.

Write control signal; asserted low Whenever

processor writes data to memory or I/O port

𝐈𝐍𝐓𝐀 (Interrupt Acknowledge) When the interrupt

request is accepted by the processor, the output is
low on this line.
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8086 Microprocessor
Pins and Signals Minimum mode signals

Pins 24 -31

For minimum mode operation, the MN/ 𝐌𝐗 is tied

to VCC (logic high)

8086 itself generates all the bus control signals

HOLD Input signal to the processor form the bus masters

as a request to grant the control of the bus.

Usually used by the DMA controller to get the

control of the bus.

HLDA (Hold Acknowledge) Acknowledge signal by the

processor to the bus master requesting the control
of the bus through HOLD.

The acknowledge is asserted high, when the

processor accepts HOLD.

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8086 Microprocessor
Pins and Signals Maximum mode signals

During maximum mode operation, the MN/ 𝐌𝐗 is

grounded (logic low)

Pins 24 -31 are reassigned

𝑺𝟎 , 𝑺𝟏 , 𝑺𝟐 Status signals; used by the 8086 bus controller to

generate bus timing and control signals. These are
decoded as shown.

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8086 Microprocessor
Pins and Signals Maximum mode signals

During maximum mode operation, the MN/ 𝐌𝐗 is

grounded (logic low)

Pins 24 -31 are reassigned

𝑸𝑺𝟎, 𝑸𝑺𝟏 (Queue Status) The processor provides the status

of queue in these lines.

The queue status can be used by external device to

track the internal status of the queue in 8086.

The output on QS0 and QS1 can be interpreted as

shown in the table.

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8086 Microprocessor
Pins and Signals Maximum mode signals

During maximum mode operation, the MN/ 𝐌𝐗 is

grounded (logic low)

Pins 24 -31 are reassigned

𝐑𝐐/𝐆𝐓𝟎, (Bus Request/ Bus Grant) These requests are used

𝐑𝐐/𝐆𝐓𝟏 by other local bus masters to force the processor
to release the local bus at the end of the
processor’s current bus cycle.

These pins are bidirectional.

The request on𝐆𝐓𝟎 will have higher priority than𝐆𝐓𝟏

𝐋𝐎𝐂𝐊 An output signal activated by the LOCK prefix

instruction.

Remains active until the completion of the

instruction prefixed by LOCK.

The 8086 output low on the 𝐋𝐎𝐂𝐊 pin while

executing an instruction prefixed by LOCK to
prevent other bus masters from gaining control of
the system bus.

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Minimum Mode Configuration of 8086

15
8284 Clock generator – Pin diagram

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Timing Diagram - Read operation

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Timing Diagram – Write operation

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Maximum Mode Configuration of 8086

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 Maximum Mode Configuration of 8086
• MRDC (Memory Read Command) : It instructs the memory to put the
contents of the addressed location on the data bus.

• MWTC (Memory Write Command) : It instructs the memory to accept the

data on the data bus and load the data into the addressed memory location.

• IORC (I/O Read Command) : It instructs an I/O device to put the data
contained in the addressed port on the data bus.

• IOWC (I/0 Write Command) : It instructs an I/O device to accept the data
on the data bus and load the data into the addressed port.

• MCE/PDEN (Master Cascade Enable/Peripheral Data Enable) : It controls

the mode of operation of 8259. It selects cascade operation for 8259 (interrupt
controller) if IOB signal is grounded and enables the I/O bus transceivers if IOB
is tied high.

• AEN, IOB and CEN : These pins are used in multiprocessor system. With a
single processor in the system, AEN and IOB are grounded and CEN is tied
high. AEN causes the 8288 to enable the memory control signals. IOB (I/O bus
mode) signal selects either the I/O bus mode or system bus mode operation.
CEN (control enable) input enables the command output pins on the 8288.

• AIOWC/AMWC (Advance I/O Write Command/Advance Memory Write

Command) : These signals are similar to IOWC and MWTC except that they
are activated one clock pulse earlier. This gives slow interfaces an extra clock
cycle to prepare to input the data.
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Maximum Mode
Timing Diagram – Read operation

21
Maximum Mode
Timing Diagram – Write operation

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 Multiprocessor configurations

• Speed of any microprocessor depends upon the operating clk

frequency, among other factors such as Pipelining in EU and on-
chip cache.

Example: when bulk I/O data transfer is done under the control of
Microprocessor alone, the processor have to spend most of the time
idle due to slow operating speed of the peripherals.

A single processor has an upper limit on the processing capability.

For further enhancement of the speed of operation, an appropriate

system with several processors using a certain topology may provide
the solution. Such a system is called multiprocessor system.

System having more than one processor may require lesser time to
complete a task as compared to the system having single processor.

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 Multiprocessor configurations

• The Simplest type of multiprocessor system consists of CPU

(8086) and a numeric data processor(NDP) or I/O processor (IOP)

• The NDP is an independent processor that is capable of

performing complex numeric calculations in lesser time than a
8086 microprocessor.

• The IOP takes care of the I/O activities of the 8086–based

system and thus saves the time of the main processor to
complete specific task.

• The NDP and IOP works in synchronism with the main processor
to complete specific task are called Coprocessors.

• Coprocessors do not work independently, as they cannot fetch the

data from the memory. They work under the control of the main
processor.

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 Multiprocessor configurations

In order to coordinate the activities of all Multiprocessor additional

hardware such as bus controller is required.

In general, If a system includes two or more processors that can

executes instructions simultaneously is called a multiprocessor
system.

Need for Multiprocessor Systems :

Due to limited data width and lack of floating point arithmetic
instructions, 8086 requires many instructions for computing even
single floating point operation.

Features of multiprocessor system:

• The modularity of a multiprocessor system provides means for
expansion.
• Avoiding the expense of the unnecessary capabilities of a single
complex processor.
• As task are divided among the processor if a failure occurs it is
easier and cheaper to find and replace the malfunctioning
processor.
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 Multiprocessor configurations

 The maximum mode operation of 8086 is specifically designed to

implement multiprocessor systems.

 There are three basic multiprocessor configurations.

 Coprocessor configuration

 Closely coupled configuration

 Loosely coupled configuration

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 1. Coprocessor Configuration

 A Coprocessor is a specially designed circuit on microprocessor

chip which can perform the same task very quickly, which the
microprocessor performs.

 It reduces the work load of the main processor.

The coprocessor shares the same memory, IO system, bus control

logic and clock generator.

The coprocessor handles specialized tasks like mathematical

calculations, graphical display on screen, etc.

The 8086 and 8088 can perform most of the operations but their
instruction set is not able to perform complex mathematical
operations, so in these cases the microprocessor requires the math
coprocessor like Intel 8087 math coprocessor, which can easily
perform these operations very quickly.

8087 numeric data processor is also known as Math co-

processor, Numeric processor extension and Floating point
unit. 27
 1. Coprocessor Configuration

Block Diagram of Coprocessor Configuration:

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 1. Coprocessor Configuration

How is the coprocessor and the processor connected?

•The coprocessor and the processor is connected via TEST, RQ/GT

and QS0 & QS1 signals.

•The TEST signal is connected to BUSY pin of coprocessor and the

remaining 3 pins are connected to the coprocessor’s 3 pins of the
same name.

•TEST signal takes care of the coprocessor’s activity, i.e. the

coprocessor is busy or idle.

•The RT-/GT-is used for bus arbitration.

•The coprocessor uses QS0 & QS1 to track the status of the queue of
the host processor.

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 2. Closely Coupled Configuration

Closely coupled configuration is similar to the coprocessor

configuration, i.e. both share the same memory, I/O system bus,
control logic, and control generator with the host processor.

 However, the coprocessor and the host processor fetches and

executes their own instructions.

The system bus is controlled by the coprocessor and the host

processor independently.

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 2. Closely Coupled Configuration

Block Diagram of Closely Coupled Configuration:

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 2. Closely Coupled Configuration

How is the processor and the independent processor

connected?

Communication between the host and the independent processor is

done through memory space.

None of the instructions are used for communication, like WAIT,

ESC, etc.

The host processor manages the memory and wakes up the

independent processor by sending commands to one of its ports.

Then the independent processor accesses the memory to execute

the task.

After completion of the task, it sends an acknowledgement to the

host processor by using the status signal or an interrupt request.

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2. Closely Coupled Configuration

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 3. Loosely Coupled Configuration

 Loosely coupled configuration consists of the number of modules of

the microprocessor based systems, which are connected through a
common system bus.

 Each module consists of their own clock generator, memory, I/O

devices and are connected through a local bus.

Advantages:

Having more than one processor results in increased efficiency.

Each of the processors have their own local bus to access the local
memory/I/O devices. This makes it easy to achieve parallel
processing.

The system structure is flexible, i.e. the failure of one module

doesn’t affect the whole system failure; faulty module can be
replaced later.

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 3. Loosely Coupled Configuration

Block Diagram of Loosely Coupled Configuration:

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 Contention problems in multiprocessor
configuration

The need for memory access by different processor give rise

to contention which cause loss in performance.

Eg: The processor that wait to complete their memory cycle waste
time in busy waiting. This results in loss of performance

3 types of contention:

Memory Contention

Communication Contention

Hot Spot Contention

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 Contention problems in multiprocessor
configuration

Memory Contention:

Several processor request the same memory module causes

memory contention.
Resolved by using bus arbiter.

Communication Contention:

It occurs due to limitation of interconnection network.

The bandwidth of interconnection network must be proportional
to the number of processor to avoid communication contention.

Hot Spot Contention:

Several processor repeatedly access the same memory location

causes Hot Spot contention.
This contention is created in memory module or interconnection
network that gets overloaded with the requests and create a
bottle neck for system performance.

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 Bus Arbitation

In multiprocessor system, there are more than one processors,

which requires control of the system bus at the same time.

Hence an appropriate priority resolving mechanism is required, to

decide which processor should get control of bus.

The Mechanism which decides the selection of current master to

access system bus is known as bus arbitration.

Following three methods are commonly used for bus arbitration.

1. Daisy chaining

2. Polling method

3. Independent priority

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 1. Daisy Chaining

All bus master use the same line for bus request.

If the bus busy line is inactive, the bus controller gives the bus
grant signal.

Bus grant signal is propagated serially through all masters starting

from nearest one.

The bus master which requires system bus, stops this signal,
activates the bus busy line and takes control of system bus.

There fore other requesting module will not receive the grant signal
and hence cannot get the bus access.
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 1. Daisy Chaining

Advantages:

a) Simple design and cheaper method.

b) Requires Less no. of control lines.

Disadvantages:

a) Priority depends on the physical location of master.

b) Propagation delay due to serially granting of bus.

c) Failure of one of the devices may fail entire system.

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 2. Polling Method

All bus masters use the same line for bus request.

Here controller generate binary address for the master. (To connect
8 bus master we need 3 address lines 2^3 = 8).

In response to a bus request, the controller “polls” the bus masters
by sending a sequence of bus master address on address lines.

When requesting master recognizes its address, it activates the bus

busy lines and takes control of the bus.
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 2. Polling Method

Advantages:

a) Priority flexible. (It can be altered by changing the polling

sequence stored in the controller)

b) One module fails, entire system does not fail.

Disadvantage:

a) Adding bus masters increases the number of address lines of the

circuit.

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 3. Independent Priority

All bus masters have their individual bus request and bus grant
lines.

The controller thus knows which master has requested, so bus is

granted for that master.

Priorities of the masters are predefined so on simultaneous bus

requests, the bus is granted based on the priority, provided the bus
busy line is not active.

The controller consists of Priority decoder to select the priorities. 43

 3. Independent Priority

Advantages:

a) Bus arbitration is fast due to separate pairs of bus request and

bus grant signals.

b) Speed is independent of no. of devices connected.

Disadvantages:

a) No. of control lines required is more (2 x n signals for n modules).

Hence connecting a large number of bus masters is difficult.

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