UNIT-I

8086-16 BIT MICROPROCESSOR Marks-14

1.1 8086 Microprocessor: Salient features, Pin descriptions

1.2 Architecture of 8086: Functional Block diagram, Register organization
1.3 Concepts of pipelining
1.4 Memory segmentation, Physical memory addresses generation

1.1 8086 MICROPROCESSOR: SALIENT FEATURES, PIN DESCRIPTIONS

Q. List any four features of 8086.
(MSBTE-S-14, W-16, S-17, W-17) 2 Marks
Q. List any four advantages of 8086 microprocessor.
Q. State any eight features of 8086.
Q. List any four features of 8086.

1. The Intel 8086 16-bit processor, which is fabricated using HMOS(High-speed Metal Oxide
Semiconductor) technology and it has 40 pins, packaged in DIP (Dual Inline Package).
2. 8086 has a 20 bit address bus can access up to 220 memory locations (1MB).
3. It has multiplexed address and data bus AD0-AD15 and A16 – A19
4. It can support up to 64K I/O ports.
5. The 8086 provides fourteen 16-bit registers.
6. The 8086 requires clock with a 33% duty cycle to provide optimized internal.
7. The 8086 microprocessor available in three clock rates: Operating clock frequencies 5MHz,
8MHz, 10MHz.
8. The Intel 8086 is designed to operate in two modes: minimum mode and maximum mode.
9. An interesting feature of the 8086 is that it fetches up to 6 instruction bytes from memory and
queue stores them in order to speed up instruction execution.
10. It requires +5V single power supply.

PIN DESCRIPTIONS
8086 PIN Diagram:
Q. Draw the pin diagram of 8086. (4M)
Pin description of 8086 Microprocessor

Q. State the functions of following pins of 8086 microprocessor:

(Per pin description – 1 Mark)

VCC – Pin number 40 – At this pin, the external power supply of + 5V is provided to the processor.

VSS – Pin number 1 and 20 – These two pins acts as the ground. This pin directs the extra current of
the microprocessor to ground.

AD0 – AD15 – Pin number 2 to 16 and 39 – These are the multiplexed address and data bus.
We know that the 8086 microprocessor has 20-bit address bus and 16-bit data bus. So, the 16 lines of
the address and data bus are multiplexed together so as to reduce the number of lines inside the IC.

We are aware of the fact that at a time either address or data will be transmitted by the bus. So, at a
particular time only either the address or the data bus will be enabled from the multiplexed buses.

A16/S3, A17/S4, A18/S5 and A19S6 – Pin number 35 to 38 – Out of 20 address bits, 4 are present in the
multiplexed form with the status signals. In the case of memory operations, these pins act as an address
bus and contain the memory address of any particular instruction or data.
However, from I/O operations these pins are low that shows the status of the processor.

Basically, the signal at S3 and S4 show that which segment is currently accessed by the microprocessor
among the four segments present in it.

The table below will show the encoding of S3 and S4:

A17/S4 A16/S3 Status

0 0 Extra segment access
0 1 Stack segment access
1 0 Code segment access
1 1 Data segment access

Also, S5, when enabled, shows the presence of an interrupts in the microprocessor. So, basically, it
serves as an interrupt flag.
The signal at S6 shows the status of the bus master for the current operation. More simply we can say,
whether the 8086 is the bus master or any other proficient device is acting as the bus master.
When 0 is present as the signal at this pin then it indicates the 8086 is holding the access of the bus
otherwise it is high i.e., 1.

BHE / S7 – Pin number 34 – BHE is an acronym for Bus High Enable. The combination of the BHE
signal and S7 status informs about the existence of the data on the bus. Also, different combinations
show whether the bus is containing overall 16 bit, upper byte or lower byte of the data.
The table below represents the status for the signal at this pin:

̅̅̅̅̅BHE S7 Indication
0 0 Whole word (16-bits)
0 1 High byte to/from odd address
1 0 Low byte to/from even address
1 1 No selection
MN/MX – Pin number 33 –The status at this particular pin shows whether the processor is operating
in the minimum mode or maximum mode.
A signal 0 at this pin informs that the 8086 is operating in maximum mode i.e., multiple processors.
While signal 1 shows the operation under minimum mode i.e., single processor.

RD – Pin number 32 – An active low signal at this pin shows that the microprocessor is performing
read operation with either memory or I/O devices.

CLK – Pin number 19 – A signal at this pin provides the timing to the internal operations that are
being executed inside the microprocessor.

NMI – Pin number 17 – NMI is Non-maskable interrupt. These are basically uncontrollable interrupts
generated inside the processor. When an NMI occurs, then an interrupt service routine is generated by
the interrupt vector table.

TEST – Pin number 23 – This input is examined by the Wait instruction. If this is low, execution
continues otherwise processor waits in idle state.

INTR – Pin number 18 – INTR stands for an interrupt request. The processor after each clock cycle
samples the INTR and if the signal at this pin is found to be high then the processor controls that
interrupts internally.

READY – Pin number 22 – This signal is used by the peripherals and memory devices in order to
show the readiness for the next operation.

RESET – Pin number 21 – Whenever this pin is enabled then it resets the processor and other devices
connected to the system by immediately terminating the recent task.

PINS IN MINIMUM MODE

INTA – Pin number 24 – It is an interrupt acknowledge pin. Whenever an INTR signal is generated,
then the microprocessor generates INTA signal, as a response to that interrupt.

ALE – Pin number 25 – ALE is an abbreviation for address latch enable. Whenever an address is
present in the multiplexed address and data bus, then the microprocessor enables this pin.
This is done to inform the peripherals and memory devices about fetching of the data or instruction at
that memory location.

DEN – Pin number 26 – DEN is used for data enable. This is an active low pin that means whenever a
0 is present at this pin then the transceiver gets enabled and it separates the data from the multiplexed
address and data bus.

DT/R – Pin number 27 – This pin is used to show whether the data is getting transmitted or is
received. It is used to control the direction of data flow through the transceiver 8286 or 74LS245.When
the processor sends the data out, this signal is high and when this signal is low the data is received.

M/IO – Pin number 28 – This pin indicates whether the processor is performing an operation with
memory or I/O devices. Whenever a high is present at this pin then it shows the operation is carried out
through the memory. While a low signal shows operation through I/O devices.

WR – Pin number 29 – An active low signal at this pin indicates that the processor is performing write
operation from either memory or I/O devices.
HOLD – Pin number 31 – When an external device enables this pin then the processor stops accessing
the buses immediately after the recent task get over.

HLDA – Pin number 30 – This pin is used as a response pin for the hold request. Once request for
accessing the buses is produced by an external entity. Then the microprocessor acknowledges the
device that its request will be considered once it gets over by the current operation.

PINS IN MAXIMUM MODE

Q. State all the control signals generated by S0, S1, S2 with their functions.

S0 , S1 and S2 – Pin number 26 to 28 – These are basically 3 status pins and they are active low. This
means that if the status at all the 3 pins is 0 then it shows that multiple interrupts are to be handled in
maximum mode.
The table below is representing the status of the processor in different combinations:
Status
S0 ̅̅̅̅̅S1 ̅̅̅̅̅S2
0 0 0 INTA
0 0 1 I/O Read
0 1 0 I/O Write
0 1 1 Halt
1 0 0 Opcode Fetch
1 0 1 Memory Read
1 1 0 Memory Write
1 1 1 Passive/None

QS0 and QS1 – Pin number 24 and 25 – These two pins indicate the status of the 6-byte pre-fetch
queue present in the architecture of 8086.
QSI QS0 Status

0 0 No Operation

0 1 First Byte of Op Code from Queue

1 0 Empty the Queue

1 1 Subsequent Byte from Queue

LOCK – Pin number 29 –This pin is involved in maximum mode operation. So, basically, when a
single processor is accessing the buses and peripherals then it locks the resources being used by it. So,
that no other entity can access it until the recent processor frees it.

RQ / GT0 and RQ / GT1 – Pin number 30 and 31 – Due to the involvement of multiple processors,
these pins indicate the request and grant permission for accessing the buses, memory and peripherals.
This is all about the pin diagram and description of the 8086 microprocessor.

Q. Explain maskable and non maskable interrupt used in 8086.

( Maskable any two points : 2Marks; non maskable any two points : 2Marks)
Ans:
Non-Maskable interrupt:
o 8086 has a non-maskable interrupt input pin (NMI) that has highest priority among the
external interrupts.
 o The NMI is not maskable internally by software.
 o TRAP (single step-type1) is an internal interrupt having highest priority amongst all
the interrupts except Divide by Zero (Type 0) exception.
 o The NMI is activated on a positive transition (low to high voltage).
o The NMI pin should remain high for at least two clock cycles and need not
synchronized with the clock for being sensed.
Maskable interrupt:
o 8086 also provides a INTR pin, that has lower priority as compared to NMI.
 o The INTR signal is level triggered and can be masked by resetting the interrupt flag.
 o It is internally synchronized with the high transition of the CLK.
o For the INTR signal, to be responded to in the next instruction cycle; it must go high in
the last clock cycle of the current instruction or before that.

1.2 ARCHITECTURE OF 8086: FUNCTIONAL BLOCK DIAGRAM, REGISTER

ORGANIZATION

Q. Draw functional block diagram of 8086 microprocessor. (Block diagram 4 M)

Q. Draw architectural block diagram of 8086 and describe its register organization.

(List of Register :1M, Any 4 registers explanation : ½ M each)

Q. Write any four important functions of any two units of 8086 microprocessor.
(Any four functions from BIU and EU may be considered, Each Function - ½
Marks) [Note: Any other function related to individual unit can be considered]
Ans:
8086 has two blocks BIU (Bus Interface Unit) and EU (Execution Unit).
Functions of Bus Interface Unit
• The BIU performs all bus operations such as instruction fetching, reading and writing
operands for memory and calculating the addresses of the memory operands.
• The instruction bytes are transferred to the instruction queue.

• BIU contains Instruction queue, Segment registers, Instruction pointer, and Address adder.

• BIU controls the address, data and control buses.

• It provides a full 16 bit bidirectional data bus and 20 bit address bus.

• The bus interface unit is responsible for performing all external bus operations.

• Instruction fetch, Instruction queuing, Operand fetch and storage, Address relocation and Bus
control are the operations performed by BIU

• The BIU uses a mechanism known as an instruction stream queue to implement a pipeline
architecture.

Functions of Execution Unit

• EU executes instructions from the instruction system byte queue.
• Both units operate asynchronously to give the 8086 an overlapping instruction fetch and
execution mechanism which is called as Pipelining. This results in efficient use of the system bus
and system performance.
• EU contains Control circuitry, Instruction decoder, ALU, Pointer and Index register, Flag
register.
• The Execution unit is responsible for decoding and executing all instructions.
• The EU extracts instructions from the top of the queue in the BIU, decodes them, generates
operands if necessary, passes them to the BIU and requests it to perform the read or write bys
cycles to memory or I/O and perform the operation specified by the instruction on the operands.
• During the execution of the instruction, the EU tests the status and control flags and updates
them based on the results of executing the instruction.
• If the queue is empty, the EU waits for the next instruction byte to be fetched and shifted to top
of the queue.
• When the EU executes a branch or jump instruction, it transfers control to a location
corresponding to another set of sequential instructions.
• Whenever this happens, the BIU automatically resets the queue and then begins to fetch
instructions from this new location to refill the queue.
• EU has a 16 bit ALU, which can perform arithmetic and logical operations on 8 bit as well as
16 bit data.
REGISTER ORGANIZATION OF 8086
AX - Accumulator register (divided into AH / AL)
AX – This is the accumulator. It is of 16 bits and is divided into two 8-bit registers AH and AL to
also perform 8-bit instructions.
It is generally used for arithmetical and logical instructions.
Example:
ADD AX, AX (AX = AX + AX)

BX - Base address register (divided into BH / BL)

BX – This is the base register. It is of 16 bits and is divided into two 8-bit registers BH and BL to
also perform 8-bit instructions.
It is used to hold the offset address or data.
Example:
MOV BL, [500] (BL = 500H)

CX - Count register (divided into CH / CL)

CX – This is the counter register. It is of 16 bits and is divided into two 8-bit registers CH and CL
to also perform 8-bit instructions.
It is used in looping and rotation.
Example:
MOV CX, 0005
LOOP

DX - Data register (divided into DH / DL)

DX – This is the data register. It is of 16 bits and is divided into two 8-bit registers DH and DL to
also perform 8-bit instructions.
It is used in multiplication an input/output port addressing.
Example:
MUL BX (DX, AX = AX * BX)

Pointer and Index Group Registers : There are two 16 bit pointer registers:
Stack Pointer (SP) and Base Pointer (BP)
BP – Base Pointer
BP – This is the base pointer. It is of 16 bits.
It is primary used in accessing parameters passed by the stack. It’s offset address relative to stack
segment.
SP – Stack Pointer
SP – This is the stack pointer. It is of 16 bits.
It points to the topmost item of the stack. Contains the offset of the top of the stack. It’s offset
address relative to stack segment.

SI and DI : During the execution of string related instructions, register SI is used to store the offset of
source data/string in data segment while the register DI is used to store the offset of destination in
Data/Extra Segment.

1. SI – Source Index register.

SI – This is the source index register. It is of 16 bits.
It is used in the pointer addressing of data and as a source in some string related operations. It’s
offset is relative to data segment.
 2. DI – Destination Index – acts as the destination for string movement instructions
DI – This is the destination index register. It is of 16 bits.
It is used in string movement instructions. The pointer addressing of data and as a destination in
some string related operations. The source string is pointed to by the SI register. It’s offset is
relative to extra segment.

IP Instruction Pointer – Instruction Pointer – contains the offset of the next instruction to be executed.
The Instruction Pointer always points to the next instruction to be carried out from the program
memory. It is 16-bit register.

Flag Register – Individual bit positions within register show status of CPU or results of arithmetic
operations.
The 16-bit flag register of 8086 contains 9 active flags (six conditional & 3 control), other 7
flags are undefined.
Conditional Flags: indicate certain condition that arises during the execution. They are
controlled by the processor.
Control Flags: control certain operations of the processor. They are deliberately set/reset by the
user.

Other Registers:
Segment Registers- SS, DS, CS and ES, the pointer and index registers -BP, SP, SI and DI.
CS – Code Segment – holds base address for all executable instructions in a program
SS - Base address of the stack
DS – Data Segment – default base address for variables
ES – Extra Segment – additional base address for memory variables in extra segment.

ALU:- ALU is used to perform arithmetic and logical operations

Address generator: - This unit is used to generate 20 bit physical address by adding 16 bit logical
address displacement with base address.

Instruction Decoder:- This unit is used convert or decode the instructions and provides signals to
various units in the EU.

The Instruction Queue:

To implement any instruction first it is to be fetched, then decoded and then executed. The fetching of
an instruction involves its address to be sent out to the system memory and then the memory sending
back the instruction.
While the EU is busy decoding or executing certain instructions which do not need the buses, the BIU
fetches next six instruction bytes and stores them in a first-in-first-out (FIFO) register set called queue.
The processor doesn't have to wait for the next instruction to be fetched as it is already made available
in the queue registers. Thus, the speed of operation is enhanced.
This prefetching of next instruction while another instruction is still being executed is known as
pipelining.

Q. State the names of segment registers in 8086 microprocessor (4M)

Segment Registers:
BIU has 4 segment registers of 16 bits each i.e CS, DS, SS and ES
-The memory pointers are used to point/address particular memory location in memory.
Code Segment (CS): CS register is used to address a memory location in the code segment of the
memory where opcode of program is stored.
Data Segment(DS) : DS register points to the data segment of the memory where the data is stored.
Extra Segment (ES): ES register is used to address the segment which is additional data segment
Stack Segment (SS) : SS Register is used to point Stack location in stack segment of the memory and
used to store data temporarily on the stack such as the contents of the CPU Registers which will be
required later stage of execution. The default segment base and offset pair registers are CS: IP and SS:
SP
Q. State the names of segment registers in 8086 microprocessor.
(For each register - ½ Marks)
Ans: Segment registers in 8086 microprocessor:
o Code Segment register(CS)
o Data Segment register(DS)
o Stack Segment register(SS)
o Extra Segment register(ES)

FLAG REGISTER
Q. List the names of flags in flag register of 8085 microprocessor.
(All Correct – 2 Marks)
Ans: Zero (Z), Carry (CY), Sign (S), Parity (P), and Auxiliary Carry (AC) flags.

Q. Draw the flag register format of microprocessor 8086 and explain any two flags. Ans.: (2
Mark for format, 2 Mark for explanation)

Q. Draw the neat labeled architecture of flag register of 8086 microprocessor.

(Labeled diagram – 4 Marks)
Ans: The 8086 microprocessor has a 16 bit register for flag register. In this register 9 bits are active
for flags. This register has 9 flags which are divided into two parts that are as follows

Flag register of 8086

1. Carry flag: This flag is set when there is a carry out of MSB in case of addition or a borrow in
case of subtraction.
2. Parity flag: This flag is set to 1if the lower byte of the result contains even numbers of 1s
3. Auxiliary carry flag : this is set if there is a carry from the lowest nibble, i.e. bit three during
addition or borrow for the lowest nibble i.e. bit three during subtraction.
 4. Zero flag: This flag is set if the result of the computation or comparison performed by previous
instruction is zero.
5. Sign flag: This flag is set when the result of any computation is negative. For signed
computations the sign flag equals the MSB of the result.
6. Trap flag: If this flag is set the processor enters the single step execution mode.
7. Interrupt flag: If this flag is set the maskable interrupts are recognized by the cpu, otherwise
they are ignored.
8. Direction flag: This flag is used by string manipulation instructions. If this flag bit is ‘0’ the
string is processed beginning from the lowest address to the highest address, otherwise the
string is processed from the highest address towards lowest address.
9. Overflow flag: This flag is set if an overflow occurs.

1.3 CONCEPTS OF PIPELINING

Q. State the concept of pipelining of 8086. (2 Marks)
Q. Explain the pipelining in 8086 microprocessor. How is queuing useful in speeding up the
operation of 8086 microprocessor. (4 Marks)
Q. What is pipelining? State its need and how it is done in 8086? (4 Marks)
Q. What is pipelining? How it is implemented in 8086 microprocessor. (2 Marks)
Q. Explain the concept of pipelining in 8086 microprocessor with diagram. (4 Marks)
Q. Describe concept of pipelining in 8086. (4 Marks)
Q. State the advantages of pipeline architecture. (4 Marks)

Q. State the concept of pipelining of 8086.( 2 Mark)

Ans.: concept of pipeline:
In
 pipelined processor, fetch, decode and execute operation are performed simultaneously or in parallel.
When first instruction is being decoded, same time next instruction’s code is fetches. When first instruction is
getting executed, second one’s is decoded and third instruction code is fetches from memory. This process is
known as pipelining. It improves speed of operation to great extent.

Q. Define pipelining. What is the size of instruction prefetch queue in 8086 microprocessor?
(Definition -1 Mark, prefetch queue size – 1 Mark)
Ans: In 8086, pipelining is the technique of overlapping instruction fetch and execution mechanism.
o This will speed up the execution of program.
o The size of instruction preftech queue in 8086 is 6 bytes.
- The technique used to enable an instruction to complete with each clock cycle is called as
Pipelining
- Normally, on a non-pipelined processor, nine clock cycles are required for fetch, decode and
execute cycles for the 3 instructions (a)
- But on a pipelined processor, the fetch, decode and execute operations are performed in parallel
only five clock cycles are required to execute the same 3 instructions (b)
Pipelined execution of three instructions

- Feature of fetching the next instruction while the current instruction is executing is called
pipelining which will reduce the execution time. So pipelining improves the execution speed of
the processor.
- In pipelined processor fetch, decode and execute operation are performed simultaneously or in
parallel.
- In 8086, pipelining is implemented by providing 6 byte queue where 6 one byte instructions
can be stored well in advance and then one by one instruction goes for decoding and execution.
- In this way 8086 perform fetch, decode and execute operation in parallel.
Advantages of Pipelining:
1) Pipelining enables many instructions to be executed at the same time
2) It allows execution to be done in fewer cycles.
3) Speed up the execution speed of the processor.
4) More efficient use of Processor.

Q. What is pipelining? How it improves the processing speed.

 In 8086, pipelining is the technique of overlapping instruction fetch and execution mechanism.
 To speed up program execution, the BIU fetches as many as six instruction bytes ahead of time
from memory. The size of instruction prefetching queue in 8086 is 6 bytes. 
 While executing one instruction other instruction can be fetched. Thus it avoids the waiting time
 for execution unit to receive other instruction.
 BIU stores the fetched instructions in a 6 level deep FIFO . The BIU can be fetching instructions
bytes while the EU is decoding an instruction or executing an instruction which does not require
 use of the buses.
 When the EU is ready for its next instruction, it simply reads the instruction from the queue in the
 BIU.
 This is much faster than sending out an address to the system memory and waiting for memory to
 send back the next instruction byte or bytes.
 This improves overall speed of the processor
Q. What is pipelining? How it is implemented in 8086 microprocessor.
Ans: (Definition -1 Mark, Description -1 Mark)

Definition:
 Process of fetching the next instruction while the current instruction is executing is called
pipelining which will reduce the execution time.
 In 8086, pipelining is the technique of overlapping instruction fetch and execution mechanism.
 To speed up program execution, the BIU fetches as many as six instruction bytes ahead of time
 frommemory. The size of instruction prefetch queue in 8086 is 6 bytes.
 While executing one instruction other instruction can be fetched. Thus it avoids the waiting time
for execution unit to receive other instruction.
 BIU stores the fetched instructions in a 6 byte FIFO queue. The BIU can be fetching
instructions bytes while the EU is decoding an instruction or executing an instruction which
 does not require use of the buses.
 When the EU is ready for its next instruction, it simply reads the instruction from the queue in
 the BIU.
 This is much faster than sending out an address to the system memory and waiting for memory
 to send back the next instruction byte or bytes.
 This improves overall speed of the processor.

1.4 MEMORY SEGMENTATION, PHYSICAL MEMORY ADDRESSES GENERATION

MEMORY SEGMENTATION IN 8086 MICROPROCESSOR
Q. State the maximum size of memory which can be interface to 8086. Why?
Ans.: In 8086 microprocessor the total memory addressing capability is 1 mega bytes. For representing 1 MB
there are minimum 4 hex digits are required i.e., 20 bits. but 8086 has fourteen 16-bit registers. That is there are
no registers for representing 20 bit address. So, the total memory is divided into 16 logical segments and each
segment capacity is 64 KB (kilo bytes). That is 16*64kb=1 MB. So, for representing 64 kb only 16 bit register is
sufficient.

Q. Describe memory segmentation in 8086 microprocessor and list its four advantages.
(Description: 2 Marks, Any 4 Advantages : ½ Mark each)
Q. Explain memory segmentation in 8086 and list its advantages.(any two)
(Explanation: 2 Marks, Any 2 Advantages : 2 Mark)
Ans :

Memory Segmentation: In 8086 available memory space is 1MByte.

The memory in 8086 based system is organized as segmented memory. The physical memory is
divided into 4 segments namely,-
Data segment, Code Segment, Stack Segment and Extra Segment.
8086 can access 1Mbyte memory which is divided into number of logical segments. Each
segment is 64KB in size and addressed by one of the segment register. The 4 segment register
in BIU hold the 16-bit starting address of 4 segments. CS holds program instruction code. Stack
segment stores interrupt & subroutine address. Data segment stores data for program. Extra
segment is used for string data. There are four segments.
 Advantages of segmentation
o The size of address bus of 8086 is 20 and is able to address 1 Mbytes ( ) of physical
memory.
o The compete 1 Mbytes memory can be divided into 16 segments, each of 64 Kbytes size.
o It allows memory addressing capability to be 1 MB.
o It gives separate space for Data, Code, Stack and Additional Data segment as Extra
segment size.
o The addresses of the segment may be assigned as 0000H to F000H respectively.
o The offset values are from 00000H to FFFFFH
o Segmentation is used to increase the execution speed of computer system so that processor
can able to fetch and execute the data from memory easily and fast.

Description:
- Data segment is used to hold data, Code segment for the executable program, Extra segment
also holds data specifically in strings and stack segment is used to store stack data.
- Each segment is 64Kbytes & addressed by one segment register.
- The 16 bit segment register holds the starting address of the segment.
- The offset address to this segment address is specified as a 16-bit displacement (offset) between
0000H - FFFFH.
- Since the memory size of 8086 is 1Mbytes, total 16 segments are possible with each having
64Kbytes.
PHYSICAL MEMORY ADDRESS GENERATION
- The address associated with any instruction or data byte is only 16-bit called as Effective
Address /Offset/Displacement/Logical Address.
- The logical addresses are used to calculate physical address
- The address generated by BIU is 20-bit called as Physical address

Q. Describe the physical memory address generation process in 8086 microprocessor. If, CS =
69FAH & IP = 834CH, calculate the physical address generated.
(Description – 2 Marks, Calculation - 2 Marks)
Ans: The 8086 addresses a segmented memory. The complete physical address which is 20-bits long
is generated using segment and offset registers each of the size 16-bit.The content of a segment
register also called as segment address, and content of an offset register also called as offset
address. To get total physical address, put the lower nibble 0H to segment address and add
offset address. The figure shows formation of 20-bit physical address.

Physical address formation

0110 1001 1111 1010 0000

+
1000 0011 0100 1100

0111 0010 0010 1110 1100

7 2 2 E C

= 722EC H

Q. Define logical and effective address. Describe physical address generation process in 8086. If
DS=345AH and SI=13DCH. Calculate physical address.
(Define each Term :1M. Physical Address Generation. Description: 2 M & Calculation 2 M)
Ans: A logical address is the address at which an item (memory cell, storage element) appears to
reside from the perspective of an executing application program. A logical address may be different
from the physical address due to the operation of an address translator or mapping function.
Effective Address or Offset Address: The offset for a memory operand is called the operand's
effective address or EA. It is an unassigned 16 bit number that expresses the operand's distance in bytes
from the beginning of the segment in which it resides. In 8086 we have base registers and index
registers.
Generation of 20 bit physical address in 8086:-
- Segment registers carry 16 bit data, which is also known as base address.
- BIU appends four 0 bits to LSB of the base address. This address becomes 20-bit address.
- Any base/pointer or index register carries 16 bit offset.

- Offset address is added into 20-bit base address which finally forms 20 bit physical address of
memory location

DS=345AH and SI=13DCH

Physical adress = DS*10H + SI
= 345AH * 10H + 13DCH

= 345A0+13DC
= 3597CH

Q. Explain how 20-bit physical address is generated by 8086 microprocessor. Calculate the
physical address if CS=2308H and IP=76A9H
Ans: (Description: 2 Marks, Example: 2 Marks)

Generation of a physical address in 8086:-

Segment registers carry 16 bit data, which is also known as base address. BIU attaches four 0 bits to
LSB of the base address. So now this address becomes 20-bit address. Any base/pointer or index
register carry 16 bit offset. Offset address is added into 20-bit base address which finally forms 20
bit physical address of memory location.
Example:- Given : CS = 2308H, IP = 76A9H
CS : 23080H ……...0 added by BIU(or Hardwired 0)
+ IP : 76A9H
-------------------------
2A729H

Q. Calculate physical address in the following cases: (2M

each)
 i) CS: 1200H, IP:DE00H
ii) DS: 1F00, BX:1A00 for MOV AX,[BX]

Ans.:

1) Segment address ---- 1200H ------  0001 0010 0000 0000
 
Offset address ------ DE00H ----- 1101 1110 0000 0000

Segment address shifted by 4 bit position- 0001 0010 0000 0000 0000
+ 1101 1110 0000 0000

-----------------------------------------------------------


Physical address----- 0001 1111 1110 0000 0000
1 F E 0 0

 
2) Segment address ---- 1F00H ------ 0001 1111 0000 0000
 
Offset address ------ 1A00H ----- 0001 1010 0000 0000

Segment address shifted by 4 bit position- 0001 1111 0000 0000 0000
+ 0001 1010 0000 0000

-----------------------------------------------------------


Physical address ----- 0010 0000 1010 0000 0000
2 0 A 0 0

Q. Describe how 20 bit physical address is generated in 8086 microprocessor. Give one example.
(Description – 2 Marks , Example – 2 Marks)
Ans: Formation of a physical address:- Segment registers carry 16 bit data, which is also
known as base address. BIU attaches 0 as LSB of the base address. So now this address
becomes 20-bit address. Any base/pointer or index register carry 16 bit offset. Offset address is
added into 20-bit base address which finally forms 20 bit physical address of memory location.

Example:- Assume DS= 2632H, SI=4567H

DS : 26320H ……...0 added by BIU(or Hardwired 0)
SI : 4567H
--------------------
2A887H
( OR Any Same Type of Example can be considered)
Q. Compare maximum and minimum mode configuration of 8086. (4 Marks)
Q. Differentiate between minimum mode and maximum mode of 8086 microprocessor