* First 32-bit microprocessor.

*Intel introduced this microprocessor in October 1985.

*It has two versions

* 80386DX

* 80386SX

* The original 80386 is 80386DX

* version SX was introduced in 1988 as low cost

alternative.

* The internal architecture of both SX &DX are same

80386DX
* 32 bit address bus

* 32 bit data bus

* Packaged in 132 pin PGA

* Address 4GB of memory

As it is a 32-bit microprocessor. Thus has 32-bit ALU.
80386 has data bus of 32-bit.
It holds address bus of 32 bit.
It supports physical memory addressability of 4 GB and
virtual memory addressability of 64 TB.
80386 supports variety of operating clock frequency, which
are 16 MHz, 20 MHz, 25 MHz and 33 MHz.
It offers 3 stage pipeline: fetch, decode and execute. As it
supports simultaneous fetching, decoding and execution
inside the system.
*Which is the Microprocessor Comprises:
A.Register section
B.one or more ALU
C.Control unit
D.All of these
80386 has Three operating modes

* Real address mode

* Protected mode

* Virtual 8086 mode

 Real address mode:
The real address mode the instruction use real
addresses (similar to 80286).
Protected mode :
The entire instruction set and features are available.
Major features are paging , multitasking and memory
protection.
Virtual 8086 mode (V86 mode) :
This is a special mode within protected mode. This
mode recommend protection and memory management
Basically it has 6 functional units which are as
follows:
Bus Interface Unit
Code Fetch Unit
Instruction Decode Unit
Execution Unit
Memory Management Unit
16
1. Bus Interface Unit
The bus interface unit or BIU holds a 32-bit bidirectional data bus as well as
32-bit address bus. Whenever a need for an instruction or a data fetch is
generated by the system then the BIU generates signals (according to the
priority) for activating the data and address bus in order to fetch the data
from the desired address.
The BIU connects the peripheral devices through the memory unit and also
controls the interfacing of external buses with the coprocessors.
2. Code Prefetch Unit
This unit fetches the instructions stored in the memory by making use of
system buses. Whenever the system generates a need for an instruction then
the code prefetch unit fetches that instruction from the memory and stores it
in 16-byte prefetch queue.
So to speed up*the operation this unit fetches the instructions in advance and
the queue stores these instructions.
3. Instruction Decode Unit
Instructions in the memory are stored in the form of bits. So, this unit
decodes the instructions stored in the prefetch queue. Basically the decoder
changes the machine language code into assembly language and transfers it
to the processor for further execution.

4. Execution Unit
The decoded instructions are stored in the decoded instruction queue. So,
these instructions are provided to the execution unit in order to execute the
instructions.
The execution unit controls the execution of the decoded instructions. This
unit has a 32-bit ALU, that performs the operation over 32-bit data in one
cycle. Also, it consists of 8 general purpose as well as 8 special purpose
registers. These* are used for data handling and calculation of offset address.
5.Memory Management Unit
This unit has two separate units within it. These are
Segmentation Unit and
Paging Unit
Segmentation unit: The segmentation unit plays a vital role in the 80836
microprocessor. It offers protection mechanism in order to protect the code
or data present in the memory from application programs.
It gives 4 level protection to the data or code present in the memory. Every
information in the memory is assigned a privilege level from PL0 to PL3.
Here, PL0 holds the highest priority and PL3 holds the lowest priority.
Paging Unit: The paging unit operates only in protected mode and it changes
the linear address into physical address. As the programmer only provides
the virtual address and not the physical address.
Basic Programming Model

The basic programming model consists of these

aspects:
● Memory organization and segmentation

● Data types

● Registers

● Instruction format

● Operand selection

● Interrupts and exceptions

*
Memory Organization and Segmentation
The physical memory of an 80386 system is organized as a
sequence of 8-bit Bytes.
Each byte is assigned a unique address that ranges from zero
to a maximum of 2 32 -1 (4 gigabytes)

The "Flat" Model: In a "flat" model of memory organization,

the applications programmer sees a single array of up to 2 32
bytes (4 gigabytes). While the physical memory can contain
up to 4 gigabytes, it is usually much smaller; the processor
maps the 4 gigabyte flat space onto the physical address space
by the address translation mechanisms

*
Memory Organization and Segmentation
The Segmented Model:
A segment is a unit of contiguous address space. Segment
sizes may range from one byte upto a maximum of 2 32 bytes
(4 gigabytes).
In a segmented model of memory organization, the address
space as viewed by an applications program (called the logical
address space) is a much larger space of up to 2 46 bytes (64
terabytes).
The processor maps the 64 terabyte logical address space onto
the physical address space (up to 4 gigabytes) by the address
translation mechanisms

*
Data Types
Bytes, words, and doublewords are the fundamental data
types.
A byte is eight contiguous bits starting at any logical
address. The bits are numbered 0 through 7; bit zero is the
least significant bit.
A word thus contains 16 bits. The bits of a word are numbered
from 0 through 15; bit 0is the least significant bit. The byte
containing bit 0 of the word iscalled the low byte; the byte
containing bit 15 is called the high byte.
A doubleword thus contains 32 bits. The bits of a doubleword
are numbered from 0 through 31; bit 0 is the least significant
bit. The word containing bit 0
of the doubleword is called the low word; the word containing
*
bit 31 is called the high word.
Memory Organization and Segmentation
The Segmented Model:
A segment is a unit of contiguous address space. Segment
sizes may range from one byte upto a maximum of 2 32 bytes
(4 gigabytes).
In a segmented model of memory organization, the address
space as viewed by an applications program (called the logical
address space) is a much larger space of up to 2 46 bytes (64
terabytes).
The processor maps the 64 terabyte logical address space onto
the physical address space (up to 4 gigabytes) by the address
translation mechanisms

*
Data Types

Bit
Bit Field: A group of at the most 32 bits (4bytes)
Bit String: A string of contiguous bits of maximum 4Gbytes in length.
Signed Byte: Signed byte data
Unsigned Byte: Unsigned byte data.
Integer word: Signed 16-bit data.
Long Integer: 32-bit signed data represented in 2's complement form.
Unsigned Integer Word: Unsigned 16-bit data
Unsigned Long Integer: Unsigned 32-bit data
Signed Quad Word: A signed 64-bit data or four word data.
Unsigned Quad Word: An unsigned 64-bit data.
Offset: 16/32-bit displacement that points a memory location using any of the
addressing modes.
Pointer: This consists of a pair of 16-bit selector and 16/32-bit offset.
Character: An ASCII equivalent to any of the alphanumeric or control characters.
Strings: These are the sequences of bytes, words or double words. A string may contain
minimum one byte and maximum 4 Gigabytes.
BCD: Decimal digits from 0-9 represented by unpacked bytes.
Packed BCD: This represents two packed BCD digits using a byte, i.e. from 00 to 99.
*
80386 has 32 registers which are grouped to 7 types

* General Purpose Registers

* Segment Registers

* Instruction Pointer and Flags

* Control Registers

* System Address Registers

* Debug Registers

* Test Registers
General Purpose Registers:
These eight 32-bit general-purpose registers are
used primarily to contain operands for arithmetic and logical
Operations.
Eight 32 - bit general purpose registers which may be used
as either 8 bit or 16 bit registers.
A 32 - bit register known as an extended register, is
represented by the register name with prefix E.
Example : A 32 bit register corresponding to AX is EAX,
similarly BX is EBX etc.
Example : A 32 bit register corresponding to AX is EAX,
similarly BX is EBX etc.
The 16 bit registers BP, SP, SI and DI in 8086 are now
available with their extended size of 32 bit and are names as
EBP,ESP,ESI and EDI.
80386 has 32 registers which are grouped to 7 types
General Purpose Registers:
These eight 32-bit general-purpose registers are
used primarily to contain operands for arithmetic and logical
Operations.
Segment registers:
● These six registers determine, at any given time,
which segments of memory are currently addressable.
● The six segment registers available in 80386 are CS, SS, DS,
ES, FS and GS.
● The CS and SS are the code and the stack segment registers
respectively, while DS, ES, FS, GS are 4 data segment
registers.
● A 16 bit instruction pointer IP is available along with 32 bit
counterpart EIP.
Flag registers:
● The flags register is a 32-bit register named EFLAGS.

● A Flag is just a flip flop in the CPU that is SET(1) or RESET(0)

depending on the condition produced by an instruction.

● The low-order 16 bits of EFLAGS is named FLAGS and can be

treated as a unit.
● This feature is useful when executing 8086 and 80286 code,
because this part of EFLAGS is identical to the FLAGS register
of the 8086 and the 80286.
● The flags may be considered in three groups: the status flags,
the control flags, and the systems flags.
Flag registers:
●

●
Flag registers:
● Status Flags:The status flags of the EFLAGS register allow the
results of one instruction to influence later instructions.
● The arithmetic instructions use OF, SF, ZF, AF, PF, and CF.
● The SCAS (Scan String), CMPS (Compare String), and LOOP instructions
use ZF to signal that their operations are complete.
● There are instructions to set, clear, and complement CF before execution
● of an arithmetic instruction.
Flag registers:
Status Flags' Functions
● CF Carry Flag -- Set on high-order bit carry or borrow; cleared
otherwise
● Parity Flag -- Set if low-order eight bits of result contain
an even number of 1 bits; cleared otherwise.

● AF Adjust flag -- Set on carry from or borrow to the low order

four bits of AL; cleared otherwise. Used for decimal
arithmetic.
● ZF Zero Flag -- Set if result is zero; cleared otherwise.
● SF Sign Flag -- Set equal to high-order bit of result (0 is
positive, 1 if negative).
● OF Overflow Flag -- Set if result is too large a positive number
or too small a negative number (excluding sign-bit) to fit in
destination operand; cleared otherwise.
 Control Flag:
● The control flag DF of the EFLAGS register controls string instructions.
DF (Direction Flag, bit 10) Setting DF causes string instructions
to auto-decrement; that is, to process strings from high addresses
to low addresses. Clearing DF causes string instructions to auto-increment,
or to process strings from low addresses to high addresses.
System Flags:
● Interrupt Enable: When set the processor recognizes external interrupts.

● I/O Privilage level: Used in protected mode to generate 4 levels of security.

● Nested Task Flag: Used in protected mode

when set, it indicates that one system task has invoked another
via a call instructions rather than a Jmp.

● Resume Flag: Used by the debug register DR6 and DR7.

It enables yotu to turn off certain exceptions while debugging code.

● Virtual 8086 mode flag: Prmits 80386 to behave like high speed 8086
 Instruction pointer:
The instruction pointer register (EIP) contains the offset address,
relative to the start of the current code segment, of the next sequential
instruction to be executed.
● The instruction pointer is not directly visible to the programmer;
It is controlled implicitly by control-transfer instructions, interrupts,
and exceptions.
● Figure shows, the low-order 16 bits of EIP is named IP and can be used
by the processor as a unit.
This feature is useful when executing instructions designed for the
8086 and 80286 processors.
 Instruction format:
● The information encoded in an 80386 instruction includes a specification
of the operation to be performed, the type of the operands to be manipulated
and the location of these operands
● If an operand is located in memory, the instruction must also select,
explicitly or implicitly, which of the currently addressable segments
contains the operand..
● 80386 instructions are composed of various elements and have various
formats.
● the elements of instructions are described below.
Of these instruction elements, only one, the opcode, is always present.
● The other elements may or may not be present, depending on the particular
● operation involved and on the location and type of the operands.
● The elements of an instruction, in order of occurrence are as follows:
 Instruction format:
● Prefixes -- one or more bytes preceding an instruction that modify the
operation of the instruction. The following types of prefixes can be used
by applications programs:
1.Segment override -- explicitly specifies which segment register an instruct
should use, thereby overriding the default segment-register selection used
by the 80386 for that instruction.
2.Address size -- switches between 32-bit and 16-bit address generation.
3.Operand size -- switches between 32-bit and 16-bit operands.
4.Repeat -- used with a string instruction to cause the instruction to act on
each element of the string.
● Opcode -- specifies the operation performed by the instruction.
Some operations have several different opcodes, each specifying a different
variant of the operation.
● Register specifier -- an instruction may specify one or two register operands.
Register specifiers may occur either in the same byte as the opcode or in
the same byte as the addressing-mode specifier.
Instruction format:
● Addressing-mode specifier -- when present, specifies whether an operand
is a register or memory location; if in memory, specifies whether a
displacement, a base register, an index register, and scaling are to be used.
● SIB (scale, index, base) byte -- when the addressing-mode specifier
indicates that an index register will be used to compute the address
of an operand, an SIB byte is included in the instruction to encode the
base register, the index register, and a scaling factor.
● Displacement -- when the addressing-mode specifier indicates that a
displacement will be used to compute the address of an operand, the
displacement is encoded in the instruction. A displacement is a signed
integer of 32, 16, or eight bits.
eight-bit form is used in the common case when the displacement
is sufficiently small. The processor extends an eight-bit displacement to
16 or 32 bits, taking into account the sign.
● Immediate operand -- when present, directly provides the value of an
operand of the instruction. Immediate operands may be 8, 16, or 32 bits
wide. In cases where an eight-bit immediate operand is combined in
some way with a 16- or 32-bit operand, the processor automatically
● extends the size of the eight-bit operand, taking into account the sign.
Instruction format:
● One Byte Instruction:

● Two byte Instruction:

● Three byte Instruction

1.One Byte Instruction::

● In one byte instruction generally the opcode and operand are of 8 bit or 1 b
● Only 1 byte of memoory location are required
Format : opcode

eg. MOV B,C

Instruction format:
1.Two Byte Instruction::
● In two byte instruction first byte specifies opcode and second byte

specifies operand or dtata

● Format : 1st byte--->opcode
2nd byte---> operand

For this we require two successive memory location

eg. MVI B,57H
Instruction format:
1.Three Byte Instruction::
● In three byte instruction first byte specifies opcode

● second and third byte specifies operand.

specifies operand or dtata

● Format : 1st byte--->opcode
2nd & 3rd byte---> operand

In this type of instruction we generally used 16 bit data or 16 bit

memory location.
● Second byte store lower 8-bit of 16 bit oprand
● Third byte stores the higher order 8 bit of 16 bit operand
eg. STA 5600H
 Operand Selection:
● An instruction can act on zero or more operands, which are the data
manipulated by the instruction. An example of a zero-operand instruction is
NOP (no operation). An operand can be in any of these locations:
An operand can be in any of these locations:
● In the instruction itself (an immediate operand)

● In a register (EAX, EBX, ECX, EDX, ESI, EDI, ESP, or EBP in the case

of 32-bit operands; AX, BX, CX, DX, SI, DI, SP, or BP in the case of
16-bit operands; AH, AL, BH, BL, CH, CL, DH, or DL in the case of 8-bit
operands; the segment registers; or the EFLAGS register for flag
operations)
● In memory

● At an I/O port

Immediate operands and operands in registers can be accessed more rapidly

than operands in memory since memory operands must be fetched from me
Register operands are available in the CPU. Immediate operands are also
available in the CPU, because they are prefetched as part of the
instruction.
 Operand Selection:
● Of the instructions that have operands, some specify operands implicitly;
others specify operands explicitly; still others use a combination of
implicit and explicit specification; for example:
● Implicit operand means that the instruction by definition has some specific
operands .
● Implicit operand: AAM
By definition, AAM (ASCII adjust for multiplication) operates on the
contents of the AX register.
● Explicit operand means that instruction operates on the operand specified
by the programmer.
● Explicit operand: XCHG EAX, EBX
The operands to be exchanged are encoded in the instruction after the
opcode.
● Implicit and explicit operands: PUSH COUNTER
The memory variable COUNTER (the explicit operand) is copied to the
top of the stack (the implicit operand).
● An 80386 instruction can explicitly reference one or two operands.
Two-operand instructions, such as MOV, ADD, XOR, etc.
 Operand Selection:
● For most instructions, one of the two explicitly specified operands──either
the source or the destination──can be either in a register or in memory.
The other operand must be in a register or be an immediate source operand.
Thus, the explicit two-operand instructions of the 80386 permit operations
of the following kinds:

● Register-to-memory
● Memory-to-register
● Immediate-to-register
● Immediate-to-memory

● Certain string instructions and stack manipulation instructions, however,

transfer data from memory to memory. Both operands of some string
instructions are in memory and are implicitly specified. Push and pop stack
operations allow transfer between memory operands and the memory-based
stack
 Immediate Operands:
● Certain instructions use data from the instruction itself as one (and
sometimes two) of the operands. Such an operand is called an immediate
operand. The operand may be 32-, 16-, or 8-bits long. For example:
For example:
SHR PATTERN, 2
● One byte of the instruction holds the value 2, the number of bits by which
to shift the variable PATTERN.
 Register Operands
● Operands may be located in one of the 32-bit general registers (EAX, EBX
ECX, EDX, ESI, EDI, ESP, or EBP), in one of the 16-bit general registers
(AX, BX, CX, DX, SI, DI, SP, or BP), or in one of the 8-bit general
registers (AH, BH, CH, DH, AL, BL, CL,or DL).
● The 80386 has instructions for referencing the segment registers (CS, DS,
ES, SS, FS, GS).
● The 80386 also has instructions for referring to the flag register. The
flags may be stored on the stack and restored from the stack.
 Memory Operands
● Data-manipulation instructions that address operands in memory must
specify (either directly or indirectly) the segment that contains the
operand and the offset of the operand within the segment.
● In the memory the source and the destination operands can be
addressed by using an offset and segment selector.
● The offset indicate the linear or effective address of the operand.They
can be of 16 bits or 32 bits.
● The segment selectors point to the segment consisting the operand.
● To access these different types of operands, 80386 has to address
memory or I/O device.The address of memory and I/O can be calculated
in several different ways,referred as “Addressing modes”.
 Interrupts and Exceptions
● The 80386 has two mechanisms for interrupting program execution:
1. Exceptions are synchronous events that are the responses of the CPU
to certain conditions detected during the execution of an instruction.
2. Interrupts are asynchronous events typically triggered by external
devices needing attention.

● Interrupts and exceptions are alike in that both cause the processor to
temporarily suspend its present program execution in order to execute a
program of higher priority.
● An exception is always reproducible by re-executing with the program
and data that caused the exception, whereas an interrupt is generally
independent of the currently executing program.
Interrupts and Exceptions
Interrupt Function
number
0 Divide Error
1 Debug Exceptions
2 NMI Interrupt
3 Breakpoint
4 INTO Detected Overflow
5 BOUND Range Exceeded
6 Invalid Opcode
7 Coprocessor Not Available
8 Double Exception
9 Coprocessor Segment Overrun
10 Invalid Task State Segmen11
11 Segment Not Present
12 Fault
13 General Protection
14 Page Fault
15 (reserved)
16 Coprocessor Err
17-32 (reserved)