Unit-I

80386 introduction

Sr.
No.

Topic

No of
Lectures

Introduction to assembly language

programming, ALP tools- Assembler, linker,
loader, debugger, emulator concepts,

Assembler directives, far and near procedures,

macros

80386 - Features and Architecture, Register Set

80386 Real mode Segmentation, Instruction

format

addressing modes, Instruction set

16/32 bit processor 80x86

The various processors in the Intel 80x86
family are 8080, 8086, 8088, 80186, 80286,
80386, Pentium I, Pentium II, Pentium III,
Pentium IV.
They are summarized in tabular form as
shown next.
In this unit we shall study the Intel 80386
microprocessor.
3

Compare 8086 with 80386

Sr.
no.

8086

80386

8086 is 16 bit processor.

80386 is 32 bit processor

It has 16 bit data bus and 20

bit address bus

It has 32bit data and address

bus.

Instruction set less than 80386. More instruction set.

It has two modes max and min

mode

It has three modes real

,protected and virtual mode.

It has less memory .(1MB)

It has more memory (upto 64

TB)

Multitasking is not possible

Multitasking is possible.

Protection is not available in

8086

protection is available in
80386.

Paging is not available.

Paging is available.

Less addressing modes are

available.

More addressing modes are

available.
5

FEATURES OF 80386:
Two versions of 80386 are commonly available:
1) 80386DX
2)80386SX
80386DX
80386SX
1) 32 bit address bus
address bus 32bit data bus
16 bit data bus
2) Packaged in 132 pin ceramic
flat
pin grid array(PGA)
package
3) Address 4GB of memory

1) 24 bit
2) 100 pin

3) 16 MB of
6

Features of 80386
The Intel 386 DX Microprocessor is an entry-level 32-bit
microprocessor designed for single-user applications and operating
systems such as MS-DOS and Windows.
It has 132-pins.
It contains more than 200 instructions.
It is designed using high-speed CHMOS IV technology.
The processor addresses up to 4GB (Gigabyte) of Physical memory.
It has 64TB (Terabyte) of Virtual memory.
Maximum size of each segment is 4(GB) Gigabyte.
It has eight 32-bit general purpose registers.
Its Object Code Compatible with All 8086 Family Microprocessors.
It is operate with a minimum frequency of 16MHz.
It can handle 8/16/32-bit data types.

Features of 80386

It has 32-bit data bus.

It has 32-bit address bus.
It has six 16-bit segment registers.
It has a 32-bit Instruction Pointer.
It has a flag register.
The integrated memory management and protection architecture
includes address translation registers, multitasking hardware and a
protection mechanism to support operating systems.
Instruction pipelining, on-chip address translation, ensure short
average instruction execution times and maximum system throughput.
Testability features include a self-test and direct access to the page
translation cache. Four new breakpoint registers provide breakpoint
traps on code execution or data accesses, for powerful debugging of
even ROM-based systems

Architecture of 80386
All members of 8086 family employ parallel
processing.
The Internal Architecture of 80386 is divided into
6 functional units:
1) Bus interface unit
2) Pre-fetch unit
3) Decode unit
4) Execution unit
5) Segment unit
6) Page unit
The execution unit and the instruction unit when
combined is
known as the central processing unit.
The segment unit and the paging unit when
combined is
9

10

Data Unit:
Data unit is responsible for performing different operations
on data. For that it is divided its work into three units:
Barrel Shifter Adder Unit.
Multiply/Divide Unit.
Register file.

Barrel Shifter Unit:

64-bit barrel shifter used to increase speed of all shift,
rotate operations.
Multiply/Divide Unit:
The multiply and divide logic uses a 1-bit per cycle
algorithm. The multiply algorithm stops the iteration
when the most significant bits of multiplier are all zero.
Register File:
Register file contains the eight 32-bit general purpose
register which are used for both address calculation and

Architecture of 80386
The architecture of 80386DX consist three functional units:
A] Central Processing Unit.
B] Memory Management Unit.
C] Bus Interface Unit.

A] Central Processing Unit:

Central processing unit is responsible for handling all instructions it receives from
hardware and software running on the computer. Central processing unit consists of:
1. Instruction Decoder.
2. Execution Unit.

Instruction Decoder:
Instruction decoder decodes the instruction opcode bytes received from 16-byte
instruction queue into 3-decoded instruction for immediate use by the execution unit.

Execution Unit:
Execution unit reads instruction from instruction queue and execute it. For executing
an instruction it has three subunits:
Data unit
Control unit
Test protection unit

Execution Unit

13

Control Unit:
Control unit directs all of the processor operations for which
it extracts instruction from memory, then decodes &
executes by generating timing and control signals. Control
unit has two sub units:
Control ROM
Decode and sequencing

Control ROM:
It is an intermediate level to execute computer program
instructions. Micro programs were organized as a
sequence of microinstruction and stored in special control
memory. It manages the translation of instruction of
micro- instruction.
Decode and Sequencing:
It manages scheduling of the micro- instruction between the
various execution units and deals with results coming

Paging Unit:
The paging unit translates the linear address space into physical address
space. Each segment is divided into one or more 4k byte pages.
Adder:
In adder the selectors linear base address is added to the offset to from the
physical address.
Page cache:
A cache is a small amount of memory which operates more quickly than
main memory. Data is moved from main memory to the cache so that it
can be accessed faster. Page cache tool allows the user to limit the
amount of page cache used by applications. Each page cache is of 4kb.
Control and attributes PLA:
Control and attribute PLA checks the privileges at the page level. Each of
the pages maintains the paging information of the task.

C] Bus interface unit:

To facilitate high performance system hardware designs, the intel 386DX
bus interface offers address pipelining, dynamic data sizing, and direct
byte enable signals for each of the data bus. Bus interface unit
responsible for interfacing the 80386DX processor with external memory
and I/O devices.

 The bus unit is the 80386 processors interface to the

outside world.
It provides a 32-bit data bus, a 32-bit address bus &
the signals needed to control transfers over the bus.
The buses are de-multiplexed.
This unit also contains the latches & drivers for the
address bus, transceivers for the data bus & control
logic for signaling whether a memory, I/O or interrupt
acknowledge bus cycle is being performed.
As shown in figure, it gets the address of the storage
location from either the MMU or pre-fetch unit.
16

Bus Interface
Unit

17

Register Set
The 80386 has eight 32 - bit general purpose registers
which may be used as either 8 bit or 16 bit registers.
A 32 - bit register known as an extended register, is
represented by the register name with prefix E.
Example : A 32 bit register corresponding to AX is
EAX, similarly BX is EBX etc.
The 16 bit registers BP, SP, SI and DI in 8086 are now
available with their extended size of 32 bit and are
named as EBP, ESP, ESI and EDI.
AX represents the lower 16 bit of the 32 bit register
EAX.
18

 REGISTER Organization of 80386DX:

The register of 80386DX has comes under following
categories:
General Purpose Registers
Segment Registers
Instruction Pointer and Flags
Control Registers
System Address Registers
Debug Registers
Test Registers

 General Purpose Registers:

80386DX has an eight 32-bit general purpose registers
named as EAX, EBX, ECX, EDX, ESI, EDI, EBP and ESP.
It is used to hold instruction operand.
Operand may be a data or address.
The lower 16 bits of the 32-bit registers can be accessed
separately. This is done by using the 16-bit names of the
registers AX, BX, CX, DX, SI, DI, BP and SP.
When accessed as a 16-bit operand, the upper 16 bits of
the register are neither used nor changed.
Finally 8-bit operations can individually access the lowest
byte (i.e. bits 0 to 7) and the higher byte (i.e. bits 8 to 15)
of general purpose registers AX, BX, CX and DX.
The lowest bytes are named AL, BL, CL and DL (each of 8bit) respectively.
The higher bytes are named AH, BH, CH and DH (each of 8bit) respectively.

 A) Instruction Pointer:
The instruction pointer is a 32-bit register named EIP.
EIP holds the offset of the next instruction to be
executed.
The offset is always relative to the base of the code
segment (CS).
The lower 16 bits (bits 0 to 15) of EIP contain the 16bit instruction pointer named IP, which is used for 16bit addressing.

 B) Flags Register
80386DX has a 32-bit Flags Register named EFLAGS.
The defined bits and bit fields within EFLAGS are shown in Figure
on next slide,
It is used to control certain operations of 80386DX and to indicate
the status of the 80386 DX.
It contains information about the result of the recent arithmetic or
logical operation
the state of the processor
the state of the current task
The lower 16 bits (bit 0 to 15) of EFLAGS contain the 16-bit flag
register named FLAGS, which is most useful when executing 8086
and 80286 code.

Eflags Register

 VM (Virtual 8086 Mode, bit 17)

VM bit is set when processor is working in virtual mode.

The 80386 supports execution of one or more 8086, 8088, 80186, or 80188
programs.
When the processor 80386 runs in a real mode where address is of 20-bit and
offset is of 16-bit.
Where processor runs in a protected mode where address is of 32-bit and offset is
of 16/32-bit.
When processor run in 80386 protected modes but run/simulates program of
8086 real mode at that time processor switched to virtual mode and VM bit is set.
A processor is switched to virtual mode when running a DOS application under
Windows operating system.

RF (Resume Flag, bit 16)

The RF flag is used with the debug register breakpoints.
A breakpoint is a special marker that tells the debugger to stop execution of the
program at the breakpoint when running in debug mode.
It is checked at the starting of every instruction cycle. By setting RF to 1, a
potential breakpoint on the next instruction will be ignored.
The RF is automatically reset after successful execution of every instruction.
Related to registers DR6 and DR7.

NT (Nested Task, bit 14)

This flag applies to Protected Mode.
NT is set to indicate that the execution of this task is
nested within another task.
If set, it indicates that the current nested task's Task State
Segment (TSS) has a valid back link to the previous task's
TSS.
This bit is set or reset by control transfers to other tasks.

IOPL (Input/output Privilege Level, bits 12-13)

These two-bit fields are used in protected mode to
generate four levels of security from 0 to 3 at which your
code must be running in order to execute any I/O related
instructions.
IOPL indicates the current privilege level value.

 OF (Overflow Flag, bit 11)

OF is set if the operation resulted in a signed overflow. Signed overflow
occurs when the operation resulted in carry/borrow into the sign bit (highorder bit) of the result.

DF (Direction Flag, bit 10)

DF is useful when manipulating a data array (string, vector etc.).
It is set by instructions in a program.
If DF is set to 0, the string instruction increments the index by the size of
the array entry and so progress is forward through memory (the string is
manipulated from the left to the right).
If DF is set to 1, the string instruction decrements the index and so progress
is backward through memory (the string is manipulated from the end to the
beginning).

IF (INTR Enable Flag, bit 9)

IF is set by instructions in a program.
If IF is set to 1, interruption to normal processor operation can be initiated
from devices (like keyboard, disc, modem). If IF is set to 0, external
interrupts are ignored.

TF (Trap Enable Flag, bit 8)

These flags are useful when debugging programs.
They are set by instructions in a program (debugger).
By setting TF to 1 the processor is forced to operate
in single step mode in which an internal interrupt is
generated after every instruction.

SF (Sign Flag, bit 7)

SF is set if the high-order bit of the result is set, it is
reset otherwise.
ZF (Zero Flag, bit 6)
ZF is set if all bits of the result are 0. Otherwise it is
reset.

 AF (Auxiliary Carry Flag, bit 4)

The Auxiliary Flag is used to simplify the addition
and subtraction of packed BCD quantities.
Otherwise AF is reset.

PF (Parity Flags, bit 2)
PF is set if the low-order eight bits of the operation
contains an even number of 1's'' (even parity). PF is
reset if the low-order eight bits have odd parity.

CF (Carry Flag, bit 0)
CF is set if the operation resulted in a carry out of
(addition), or a borrow into (subtraction) the highorder bit. Otherwise CF is reset. CF is set according
to carry/borrow at bit 7, 15 or 31, respectively.

 Protected mode Registers

System Address Register is special registers which are defined to
reference the tables or segments supported by the 80286CPU and
80386DX protection model.
These tables or segments are:
GDT (Global Descriptor Table)
IDT (Interrupt Descriptor Table)
LDT (Local Descriptor Table)
TSS (Task State Segment)
The addresses of these tables and segments are stored in special
registers called System Address Registers.
These four registers are named as GDTR, IDTR, LDTR and TR,
respectively.
GDTR and IDTR registers hold the 32-bit linear base address and 16-bit
limit of the GDT and IDT, respectively.
LDTR and TR registers hold the 16-bit selector for the LDT descriptor and
the TSS descriptor, respectively.

System Address Regesters

New Registers
Four categories (13 new reg.)
3
6
2
2

control registers
debug registers
test registers
segment registers

 Control Registers
The 80386 DX has three control registers of 32 bits, CR0,
CR2 and CR3, to hold machine state of a global nature
(not specific to an individual task).
CR1 has been left undefined by Intel & should not be
used. Generate exception 6 (invalid opcode)
These registers hold machine state that affects all tasks in
the system. To access the Control Registers, load and
store instructions are defined.
CR0: Machine Control Register (includes 80386
Machine Status Word)
CR0, shown in Figure below, contains 6 defined bits for
control and status purposes.
The low-order 16 bits of CR0 are also known as the
Machine Status Word, MSW, for compatibility with 80286
Protected Mode.

Control Register 0

 The defined CR0 bits are described below:

PG (Paging Enable, bit 31)
The PG bit is set to enable the paging unit. It is reset to disable the on-chip
paging unit. Usually not change in this bit more than once in a running system.

ET (extension type, bit 4)

Informs whether the numeric processor is an 80387.

TS (Task Switched, bit 3)

TS bit is set automatically every time by processor whenever a task switch
operation is performed. Never clear this bit by its own. CLTS

EM (Emulate Coprocessor, bit 2)

The Emulate coprocessor bit is set to generate a Coprocessor (device) not
available fault (i.e. exception 11) whenever it fetches floating point instruction.

MP (math present, bit 1)

The MP bit is used in conjunction with the TS bit. It is set to indicate that
arithmetic coprocessor is present in the system.

PE (Protection Enable, bit 0)

The PE bit is set to enable the Protected Mode. If PE is reset, the processor
operates in Real Mode. Similar to VM in EFLAGS

 CR1: reserved: CR1 is reserved for use in future Intel

processors.

CR2: Page Fault Linear Address

CR2, shown in Figure below, holds the 32-bit linear address
that caused the last page fault detected. The error code
pushed onto the page fault handler's stack when it is invoked
provides additional status information on this page fault.

CR3: Page Directory Base Address

CR3, shown in Figure contains the physical base address of
the page directory table (PDBR).

 Debug Registers :
The six programmer accessible debug registers provide on-chip support for
debugging.
Debug Registers DR0 to DR3 are used to specify the four linear
breakpoints. Compares with processors address generation logic on every
instruction & if match found, an exception 1 (debug fault) is generated.
The Debug Status Register DR6 displays the current state of the
breakpoints. Never cleared by the processor.
DR4 and DR5 are reserved by Intel which do not defined.
The Debug Control Register DR7 is used to set the breakpoints. Control the
operation of the four linear address breakpoints.

Test Registers
Test registers are used to control the testing of the RAM/CAM (Content
Addressable Memories) in the Translation Look aside Buffer portion of the
80386DX.
TR6 is the command test register.
TR7 is the data register which contains the data of the Translation Look
aside buffer test.

Debug registers

Debug Registers

 Segment Registers

There are six 16-bit registers name as CS, DS, ES, SS, FS, GS.
In real mode they contain the base address of a segment:
CS base address of the code segment
SS base address of the stack segment
DS base address of the data segment
ES, FS, GS base address of other data segments
CS and SS are initialized automatically by the operating system at
the moment of the program start.
The other segment registers are set by program instructions.
In protected mode the value in the register is an index into a table
of segment descriptors.
Each descriptor register holds a 32-bit segment base address, a
32-bit segment limit, and the other necessary segment attributes.
They are initialized automatically by the operating system.
The selector contains three fields. The lowest two bits (RPL) i.e.
Requestor Privilege level. The next bit is TL i.e. Table Indicator,
determines which table of descriptors defines the segment.

Segment Registers

MOD AND R/M BIT PATTERN:

MOD
->
R/M

00

01

10
For 16 bit

10
For 32 bit

11

000

[BX]+[SI]

[BX]+[SI]
+d8

[BX]+[SI]
+d16

DS:[EAX]
+d32

AL

AX

001

[BX]+[DI]

[BX]+[DI]
+d8

[BX]+[DI]
+d16

DS:[ECX]
+d32

Cl

CX

010

[BP]+[SI]

[BP]+[SI]
+d8

[BP]+[SI]
+d16

DS:[EDX]
+d32

Dl

DX

011

[BP]+[DI]

[BP]+[DI]
+d8

[BP]+[DI]
+d16

DS:[EBX]
+d32

Bl

BX

100

[SI]

[SI]+d8

[SI] +d16

Uses scaled AH
index byte

SP

101

[DI]

[DI]+d8

[DI] +d16

SS:[EBP]
+d32

CH

BP

DS:[ESI]
+d32
001XX110
DS:[EDI]

DH

SI

BH

DI

110
111

D16 direct [BP]+d8

[BP]+d16
add
For segment override prefix format is
[BX]
[BX]+d8
[BX]+d16

42

 BP, SP, SI, DI represents the lower 16 bit of

their 32 bit counterparts, and can be used as
independent 16 bit registers.
The six segment registers available in 80386
are CS, SS, DS, ES, FS and GS.
The CS and SS are the code and the stack
segment registers respectively, while DS,
ES,FS, GS are 4 data segment registers.
A 16 bit instruction pointer IP is available along
with 32 bit counterpart EIP.
43

Flag Register of 80386: The Flag register of

80386 is a 32 bit register. Out of the 32 bits, Intel
has reserved bits D18 to D31, D5 and D3, while D1
is always set at1.

44

Status Flags:
CF (CARRY FLAG):It is set by arthmetic
instruction that generate either a carry
and borrow.
PF (PARITY FLAG): IT is set when
generated output has even no of 1s.
AF (Auxiliary CARRY FLAG): It is set when
there is a carry or borrow after a nibble.
ZF (ZERO FLAG): Zero flag is set to 1 ,if
the result of an operation is zero.
SF(SIGN FLAG): Sign flag is set to 1 when
output of operation is negative.
45

 OF (OVERFLOW FLAG): This flag is set

if the result of a operation is too large
to fit in the destination operand.
CONTROL FLAG:
DF(DIRECTION FLAG): If this flag is
set then string operation perform in a
auto decrement mode otherwise in a
auto increment mode.
TF(TRAP FLAG): When this flag is set
then its provide single step
debugging for user.
IF(INTERRUPT FLAG): If this flag is set
then processor handles the interrupt.
46

SYSTEM FLAGS:
VM ( Virtual Mode Flag): If this flag is set, the 80386
enters the virtual 8086 mode within the protection mode.
This is to be set only when the 80386 is in protected mode.
In this mode, if any privileged instruction is executed an
exception 13 is generated. This bit can be set using IRET
instruction or any task switch operation only in the
protected mode.

RF- (Resume Flag): This flag is used with the debug register
breakpoints. It is checked at the starting of every
instruction cycle and if it is set, any debug fault is ignored
during the instruction cycle. The RF is automatically reset
after successful execution of every instruction, except for
IRET and POPF instructions
47

IOPL (I/O PRIVELLEGE LEVEL): the two

bits in the IOPL are used by the
processor to determine the access of
i/o facilities.
NT(Nested Flag): The flag is set when
one system task invokes another
task.

48

Real Address Mode of

80386
After reset, the 80386 starts from
memory location FFFFFFF0H under the
real address mode.
In the real mode, 80386 works as a fast
8086 with 32-bit registers and data types.
The 80386 will remain in this mode unless
it is switched to protected mode.
49

 In real mode, the default operand size is 16 bit

but 32- bit operands and addressing modes
may be used with the help of override
prefixes.
The segment size in real mode is 64k, hence
the 32-bit effective addressing must be less
than 0000FFFFFH.
The real mode initializes the 80386 and
prepares it for protected mode.

50

 The real mode software model of

80386 is as shown in figure.
There are 17 registers in this model.
Out of that, the 4 data registers
(EAX, EBX, ECX & EDX), the 2 index
registers (ESI & EDI) the 2 pointer
registers (ESP & EBP) are identical to
the corresponding registers in the
software model of 8086 except that
they are now all 32 bits in length.
51

 The flag register, the 4 segment base

registers (DS, ES, CS & SS) & the instruction
pointer (IP) register are identical to 8086
processor.
80386 has 2 new segment registers namely
FS & GS. Also the control register 0 (CR0).
Only LSB of CR0 is active in real mode
(protection enable bit). It is used to switch
the 80386 from real mode to protected mode.
Figure shows the dedicated & general use of
memory & I/O.
52

53

80386 Architecture

54

Addressing modes:
The 80386 supports overall addressing modes to facilitate
efficient execution of higher level language programs.
In case of all those modes, the 80386 can now have 32-bit
immediate or 32- bit register operands or displacements.
The 80386 has a family of scaled modes.
In case of scaled modes, any of the index register values
can be multiplied by a valid scale factor to obtain the
displacement.
The valid scale factor are 1, 2, 4 and 8.

.
55

The different scaled modes are as follows.

Scaled Indexed Mode: Contents of the an index
register are multiplied by a scale factor that may
be added further to get the operand offset.
EXAMPLE MOV EBX , SI* 4;
Based Scaled Indexed Mode: Contents of the
an index register are multiplied by a scale factor
and then added to base register to obtain the
offset.
EXAMPLE MOV EBX,[EAX][ESI*4];
Based
Scaled
Indexed
Mode
with
Displacement: The Contents of the an index
register are multiplied by a scaling factor and the
result is added to a base register and a
displacement to get the offset of an operand.
EXAMPLE MOV EBX,[EAX][ESI*4]+24; 56

Maeng Lect01-57

58

Memory
I/O

59

General Purpose Data

Registers
General Purpose Data
Registers
EAX

Accumulator (A): ASCII Adjust, ......

AX
AH

AL

Base (B) : table-lookup translations

Count (C): loop operations, repeat string operations, shift/rota

Data (D): indirect I/O, I/O string, Multi, Divide

Memory Addressing in
Real Mode

Real mode 80386 generates physical

addresses in the same manner as the
8086.
In the real mode, the 80386 can
address at the most 1Mbytes of
physical memory using address lines
A0-A19.
Paging unit is disabled in real
addressing mode, and hence the real
addresses are the same as the physical
61

 To form a PH
Physical memory address, appropriate
segment registers contents (16-bits) are
shifted left by four positions and then
added to the 16-bit offset address formed
using one of the addressing modes, in the
same way as in the 80386 real address
mode.
The segment in 80386 real mode can be
read, write or executed, i.e. no protection
is available.
62

 Any fetch or access past the end of the

segment limit generate exception 13 in
real address mode.
The segments in 80386 real mode may
be overlapped or non-overlapped.
The interrupt vector table of 80386 has
been allocated 1Kbyte space starting
from 00000H to 003FFH.

63

Physical Address Generation

64

x86 Instruction
Format

65

 Instruction format:
An instruction format defines the layout of the bits of
an instruction.
It includes the opcode
Zero or more operands
Addressing mode for each operand
The bit allocation can be determined by the
following factors:
Number of addressing modes
Number of operands
Number of CPU registers
Number of register sets
Address range
Address granularity(address can refer
byte,word or double word)

66

Pentium instruction format consist of six fields:

Instruction prefixes
Opcode
Mod R/M
SIB
Displacement
Immediate

67

 Instruction prefixes:
It is divided into 4 subfields
Instruction prefixes
Segment override
Operand size override
Address size override

68

 Instruction prefixes:
The instruction prefix if present consists of either LOCK
prefix or one of the repeat prefixes. The LOCK prefix is used
to ensure the exclusive use of shared memory in
multiprocessor environment
The repeat prefix specify repeated operation of string.
Segment override
the segment override specifies which segment register an
instruction should use rather than default segment register.
Operand size override:
Specifies which operand size an instruction should use

69

Address size override:

It specifies the address size the instruction should use to
access memory.
Opcode:
The opcode field is always present. It consists of one or two
byte opcode. If it is 1 byte the format is
Opcode

6 bits

D=0 from
D=1 To

W=0 byte
W=1 word/ double
word

MOD R/M:
MOD- The MOD field specifies whether one of the operand is
in memory or both operands are register.
REG/operand- The REG field identifies one of the register or it
can form the part of opcode.
R/M- If MOD field specifies register to register transfer then
R/M identifies the register else it specifies how the effective
address of the memory operand is to be calculated.
70

Instruction Set
New instructions introduced by
80186/80188 and 80286.
PUSH immediate data
Push all and pop all (PUSHA and
POPA)
Multiply immediate data
Shift and rotate by immediate
count
String I/O
ENTER and LEAVE
BOUND
71

 SIB:
Used to specify certain addressing modes such as
scaled,index and based. Scale(2 bits) specifies
scaling factor, Index(3 bits)specify index register,
base(3 bits) specify base register.
Displacement:
This field specifies an 8,16 or 32 bit displacement if
specified by the addressing mode.
Immediate:
This field provides the value of an 8,16, or 32 bit
operand.

72

New instructions
by 80386.

introduced

LSS, LFS, LGS instructions

Long-displacement conditional jumps
Single-bit instructions
Bit scan
Double-shift instructions
Byte set on condition
Move with sign/zero extension
Generalized multiply
MOV to and from control registers
MOV to and from test registers
MOV to and from debug registers
73

End of Unit-I

74