Architecture of 8086 Microprocessor

Evolution of Microprocessors:

 Intel introduced its first 4-bit microprocessor 4004 in 1971 and its 8-bit microprocessor
8008 in 1972. These microprocessors could not survive as general purpose microprocessors
due to their design and performance limitations.

 The first general purpose 8-bit microprocessor 8080 was launched in 1974 and later in
1977 an updated version of 8080, the 8085 microprocessor was introduced with more added
features which result in a functionally complete microprocessor.

 The main limitations of the 8-bit microprocessors were their

 low speed,
 low memory addressing capability,
 limited number of general purpose registers and
 less powerful instruction set.
In the family of 16-bit microprocessors, Intel’s 8086 was the first one to be launched in 1978.

4004 8008 8080 8085 8086

Year 1971 1972 1974 1977 1978

No. of Bits 4 8 8 8 16

Technology PMOS PMOS NMOS NMOS HCMOS

Memory 4KB 16KB 64KB 64KB 1MB

No. of 2300 3500 4500 6500 29,000

Transistors

Features of 8086 Microprocessor:

 It is a 40 pin DIP based on N-channel, depletion mode silicon gate technology (HCMOS).
 The term 16-bit means that it supports a 16-bit ALU, its internal registers and most of the
instructions are designed to work with 16 bit binary words.
 8086 is available at different clock speeds Viz, 5 MHz (8086); 8MHz (8086-2) and 10MHz
(8086-1).
 8086 microprocessor has a 16-bit data bus and 20-bit address bus. So, it can address any
one of 220 = 1048576 = 1 Megabyte (1MB) memory locations.
 The 8086 microprocessor can work in two modes of operations. They are Minimum mode
and Maximum mode. The minimum mode of operation means single processor system, but
in the maximum mode the 8086 can work in multi-processor or co-processor
configuration. These minimum or maximum operations are decided by the pin MN/ MX.
When this pin is high 8086 operates in minimum mode otherwise it operates in maximum
mode.

Architecture of 8086 Microprocessor:

 The architecture of 8086 microprocessor supports/provides

 a 16-bit ALU
 a set of 16-bit registers
 segmented memory addressing capability
 a rich instruction set
 powerful interrupt structure
 pre fetched instruction queue for overlapped fetching and execution etc.
To improve the performance by implementing the parallel processing concept the architecture
of the 8086 is divided into two independent sections.
 Bus Interface Unit (BIU) and
 Execution Unit (EU).
The BIU sends out addresses, fetches instructions, read data from ports and memory and writes
data to ports and memory. The BIU handles all transfers of data and addresses on the buses
required by the Execution Unit whereas the Execution Unit tells the BIU where to fetch
instructions or data from, decodes the instructions and executes the instructions.
 The BIU contains
 the circuit for physical address calculations
 a pre decoding instruction byte queue (6 bytes long)
 four 16-bit segment registers (ES, CS, SS, DS)
 16-bit instruction pointer (IP)
 The EU contains
 control circuitry, instruction decoder and ALU
 16-bit flag registers
 four 16-bit general purpose registers (AX, BX, CX, DX)
  16-bit pointer registers (SP, BP) and
 16-bit index registers (SI, DI)

Fig. 1.1. Internal Architecture of 8086 Microprocessor

Execution Unit:

Control Circuitry, Instruction Decoder and ALU:

 The EU contains control circuitry which directs internal operations.

 A decoder in the EU translates instructions fetched from memory into a series of actions
which the EU carries out.
 The EU has a 16-bit arithmetic logic unit which can add, subtract, AND, OR, XOR,
increment, decrement, complement, or shift binary numbers.
Flag Registers:

 The 8086 16-bit flag register contents indicate the results of computations in the ALU. It
also contains some flag bits to control the CPU operations.
 A flag is a flip-flop that indicates some condition produced by the execution of an
instruction or controls certain operations of the EU.
General Purpose Registers:

1. AX (Accumulator): This is 16-bit accumulator register. It gets used in arithmetic, logic

and data transfer instructions. In multiplication and division operations, one of the
operand must be in AX or AL.
2. BX (Base Register): BX register is 16-bit size and it is address register. It usually
contain a data pointer used for based, based indexed or register indirect addressing.
3. CX (Count Register): 16-bit register used as a counter in case of loop and string
instructions.
4. DX (Data Register): A 16-bit register used to hold the port address in case of indirect
addressing, and also used in multiplication and division operations.
5. SP (Stack Pointer): This is stack pointer register pointing to program stack. It is used
in conjunction with SS for accessing the stack segment.
6. BP (Base Pointer): This is base pointer register pointing to data in stack segment.
Unlike SP, we can use BP to access data in the other segments.
7. SI (Source Index): This is source index register which is used to point to memory
locations in the data segment addressed by DS. By incrementing the contents of SI one
can easily access consecutive memory locations.
8. DI (Destination Index): This is destination index register performs the same function
as SI.
9. ALU (Arithmetic & Logic Unit): This unit can perform various arithmetic and logical
operation, if required, based on the instruction to be executed. It can perform arithmetic
operations, such as add, subtract, increment, decrement, convert byte/word and
compare etc and logical operations, such as AND, OR, exclusive OR, shift/rotate and
test etc.

Bus Interface Unit: The BIU consists of a 6-byte long prefetch instruction Queue and four
stack segment registers (ES, CS, SS, DS), one Instruction Pointer (IP) and an adder circuit to
calculate the 20bit physical address of a location. This bus interface unit will perform all
external bus operations. They are fetching the instructions from the memory, read/write data
from/into memory or port and also supporting the instruction Queue etc. The BIU fetches up
to six instruction bytes from the memory and stores these pre-fetched bytes in a first –in first
out register set called Queue.

REGISTER ORGANISATION:

The 14 sixteen bit registers of 8086 microprocessor are categorized into four groups. They are
general purpose or data registers, Pointer & Index registers, Segment registers and Flag
register.

Fig. 1.2. Register Organization

Segment Registers: There are four 16-bit segment registers namely code segment register
(CS), Stack segment register (SS), Data segment register (DS) and Extra segment register (ES).
The code segment register is used for addressing the 64KB memory location in the code
segment of the memory ,where the code of the executable program is stored. Similarly the DS
register points to the data segment of the 64KB memory where the data is stored. The Extra
segment register also refers to essentially another data segment of the memory space. The SS
register is useful for addressing stack segment of memory.
Instruction Pointer Register: It is a 16-bit register which always points to the next instruction
to be executed within the currently executing code segment. So, this register contains the 16-
bit offset address pointing to the next instruction code within the 64KB of the code segment
area. Its content is automatically incremented as the execution of the next instruction takes
place.
Flag Register: This register is also called status register. It is a 16 bit register which contains
six status flags and three control flags. So, only nine bits of the 16 bit register are defined and
the remaining seven bits are undefined. Normally this status flag bits indicate the status of the
ALU after the arithmetic or logical operations.

CF- Carry Flag: This flag is set, when there is a carry out of MSB in case of addition or a
borrow in case of subtraction.
PF - Parity Flag: This flag is set to 1, if the lower byte of the result contains even number of
1’s else (for odd number of 1s ) set to zero.
AF- Auxiliary Carry Flag: This is set, if there is a carry out of lowest nibble.
ZF- Zero Flag: This flag is set, if the result of the computation or comparison performed by
the previous instruction is zero.
SF- Sign Flag: This flag is set, when the result of any computation is negative.
TF - Tarp Flag: If this flag is set, the processor enters the single step execution mode.
IF- Interrupt Flag: If this flag is set, the maskable interrupt INTR of 8086 is enabled and if it
is zero, the interrupt is disabled. It can be set by using the STI instruction and can be cleared
by executing CLI instruction.
DF- Direction Flag: This is used by string manipulation instructions. If this flag bit is ‘0’, the
string is processed beginning from the lowest address to the highest address, i.e., auto
incrementing mode. Otherwise, the string is processed from the highest address towards
the lowest address, i.e., auto decrementing mode.
OF- Over flow Flag: This flag is set, if an overflow occurs, i.e, if the result of a signed operation
is large enough to accommodate in a destination register. The result is of more than 7-bits
in size in case of 8-bit signed operation and more than 15-bits in size in case of 16-bit sign
operations, and then the overflow will be set.

PIN DESCRIPTIONS OF 8086 MICROPROCESSOR

Intel 8086 is a 16-bit HCMOS microprocessor. It is available as 40 pin DIP. It uses a 5V D C

supply for its operation. The 8086 uses 20-line address bus. It uses a 16-line data bus. The 20
lines of the address bus operate in multiplexed mode. The 16-low order address bus lines are
multiplexed with data and 4 high-order address bus lines are multiplexed with status signals.
The pin diagram of Intel 8086 is shown in figure 1.3.
AD0-AD15 (Bidirectional): Address/Data bus. These are low order address bus. They are
multiplexed with data. When AD lines are used to transmit memory address the symbol A is
used instead of AD, for example A0-A15. When data are transmitted over AD lines the symbol
D is used in place of AD, for example D0-D7, D8-D15 or D0-D15.
 Fig.1.3. Pin Diagram of 8086 Processor

A16/S3, A17/S4, A18/S5, A19/S6: The specified address lines are multiplexed with corresponding
status signals.

BHE (Active Low)/S7 (Output): Bus High Enable/Status. During T1 it is low. It is used to
enable data onto the most significant half of data bus, D8-D15. 8-bit device connected to upper
half of the data bus use BHE (Active Low) signal. It is multiplexed with status signal S7.

RD (Read) (Active Low): The signal is used for read operation. It is an output signal. It is
active when low.

READY: This is the acknowledgement from the slow device or memory that they have
completed the data transfer. The signal made available by the devices is synchronized by the
8284A clock generator to provide ready input to the 8086.

INTR-Interrupt Request: This is a level triggered interrupt input. This is sampled during
the last clock cycles of each instruction to determine the availability of the request. If any
interrupt request is pending, the processor enters in to the interrupt acknowledge cycle. This
can be internally masked by resulting the interrupt enable flag.
NMI (Input) NON-MASKABLE INTERRUPT: It is an edge triggered input which causes a
type 2 interrupt. A subroutine is vectored to via an interrupt vector lookup table located in
system memory. NMI is not maskable internally by software. A transition from LOW to HIGH
initiates the interrupt at the end of the current instruction.

INTA: INTA: Interrupt acknowledge. It is active LOW during T 2, T 3 and T w of each

interrupt acknowledge cycle.

MN/ MX MINIMUM / MAXIMUM: This pin decides the mode of 8086.

RQ/GT RQ/GT0: REQUEST/GRANT: These pins are used by other local bus masters to
force the processor to release the local bus at the end of the processor's current bus cycle. Each
pin is bidirectional with RQ/GT having higher priority than RQ /GT1.

LOCK: It indicates that other system bus masters are not to allow to gain control of the system
bus while LOCK is active LOW. The LOCK signal remains active until the completion of the
next instruction.

TEST: This input is examined by a ‘WAIT’ instruction. If the TEST pin goes low, execution
will continue, else the processor remains in an idle state.

CLK- Clock Input: The clock input provides the basic timing for processor operation and
bus control activity and an asymmetric square wave with 33% duty cycle.

RESET (Input) RESET: causes the processor to immediately terminate its present activity.
The signal must be active HIGH for at least four clock cycles.

Vcc – Power Supply (+5V D.C.)

GND – Ground

QS1, QS0 (Queue Status) These signals indicate the status of the internal 8086 instruction queue
according to the table shown below

QS1 QS0 Status

0 0 No Operation
 0 1 First Byte of Op Code from
Queue

1 0 Empty the Queue

1 1 Subsequent Byte from Queue

DT/R: DATA TRANSMIT/RECEIVE: It is used to control the direction of data flow

through the transceiver.

DEN: DATA ENABLE this pin is is active LOW during each memory and I/O access and for
INTA cycles.

HOLD/HLDA: HOLD indicates that another master is requesting a local bus .This is an active
HIGH. The processor receiving the ``hold'' request will issue HLDA (HIGH) as an
acknowledgement in the middle of a T 4 or T 1 clock cycle.

MEMORY ORGANIZATION:

The 8086 processor provides a 20-bit address to access any location of the 1 MB memory
space. The memory is organized as a linear array of 1 million bytes, addressed as 00000(H) to
FFFFF (H). The memory is logically divided into code, data, extra and stack segments of up to
64K bytes each. Physically, the memory is organized as a high bank (D15 - D8) and a low
bank (D7–D0) of 512 K 8-bitbytes addressed in parallel by the processor's address lines A19 -
A1. Byte data with even addresses is transferred on the D7 – D0 bus lines while odd addressed
byte data (A0 HIGH) is transferred on the D15-D8 bus lines. The processor provides two enable
signals, BHE and A0, to selectively allow reading from or writing into either an odd byte
location, even byte location, or both. The instruction stream is fetched from memory as words
and is addressed internally by the processor to the byte level as necessary.
 Fig. 1.4. Memory Organization

Minimum Mode 8086 System

 The microprocessor 8086 is operated in minimum mode by strapping its

MN/MX pin to logic1.
 In this mode, all the control signals are given out by the microprocessor itself.
There is a single microprocessor in the minimum mode system.
 The remaining components in the system are latches, transreceivers,
clock generator, memory and I/O devices.
 Latches are generally buffered output D-type flip-flops like 74LS373 or 8282.They are
used for Separating the valid address from the multiplexed address/data signals and are
controlled by the ALE signal generated by 8086.
 Fig. 1.5. Minimum mode 8086 configuration

 Transreceivers are the bidirectional buffers and they are called as data amplifiers. They
are required to separate the valid data from the time multiplexed address/data signals.
They are controlled by two signals namely, DEN and DT/R.
 The DEN signal indicates the direction of data, i.e. from or to the
processor.
 The opcode fetch and read cycles are similar. Hence the timing diagram can be
categorized in two parts, the first is the timing diagram for read cycle and the second is
the timing diagram for write cycle.
 The read cycle timing diagram is shown in figure 1.6.

Fig. 1.6. Read cycle timing diagram in minimum mode

 The read cycle begins inT1with the assertion of address latch enable (ALE) signal
and also M/IO signal. During the negative going edge of this signal, the valid
address is latched on the local bus.
The BHE and A0 signals address low, high or both bytes. From T1 to T4, the M/IO
signal indicates a memory or I/O operation.
 At T2, the address is removed from the local bus and is sent to the output. The
bus is then tristated. The read (RD) control signal is also activated in T2.
 The read (RD) signal causes the address device to enable its data bus drivers. After
RD goes low, the valid data is available on the data bus.
 The addressed device will drive the READY line high. When the processor returns
the read signal to high level, the addressed device will again tristate its bus drivers.
A write cycle also begins with the assertion of ALE and the emission of the address and is
shown in figure 1.7.
 The M/IO signal is again asserted to indicate a memory or I/O operation. In T2,
after sending the address in T1, the processor sends the data to be written to the
addressed location.
 The data remains on the bus until middle of T4state.TheWR becomes active at the
beginning of T2

 The BHE and A0 signals are used to select the proper byte or bytes of
memory or I/O word to be read or write.
 The M/IO, RD and WR signals indicate the type of data transfer.

Fig. 1.7. Write cycle timing diagram in minimum mode

Maximum Mode 8086 System

The 8086 microprocessor is operated in maximum mode by strapping MN/MX pin to ground
and is shown in figure 1.8
 Fig. 1.8. Maximum mode 8086 system
 In this mode, the processor derives the status signal S2, S1, S0. Another chip called bus
controller derives the control signal using this status information.
 In the maximum mode, there may be more than one microprocessor in the
system configuration.
 The components in the maximum mode system are bus controller chip IC8282
and the remaining components are same as in the minimum mode system.
 The basic function of the bus controller chip IC8288 is to derive control signals like
RD and WR (for memory and I/O devices), DEN, DT/R, ALE etc. using status lines.
 It derives the outputs ALE, DEN, DT/R, MRDC, MWTC, AMWC, IORC,
IOWC and AIOWC.
 The AEN, IOB and CEN pins are especially useful for multiprocessor
systems.
 AEN and IOB are generally grounded and CEN pin is usually tied to +5V.
 INTA pin used to issue two interrupt acknowledge pulses to the interrupt controller
or to an interrupting device.
 IORC, IOWC are I/O read command and I/O write command signals respectively.
These signals enable an IO interface to read or write the data from or to the addressed
port.
 The MRDC, MWTC are memory read command and memory write command
 signals respectively and may be used as memory read or write signals.
The read and write timing diagrams in maximum mode of 8086 microprocessor are
shown in figure 1.9 and 1.10 respectively.

Fig. 1.9. Read cycle timing diagram in maximum mode

Fig. 1.10. Write cycle timing diagram in maximum mode

 S0, S1, S2 are set at the beginning of bus cycle. 8288 bus controller will output a
pulse as on the ALE and apply a required signal to its DT/ R pin during T1.
 In T2, 8288 will set DEN=1 thus enabling transceivers, and for an input it will
activate MRDC or IORC. These signals are activated until T4.
  For an output, the AMWC or AIOWC is activated from T2 to T4 and MWTC or
IOWC is activated from T3 to T4.
 The status bit S0 to S2 remains active until T3 and become passive during T3
and T4.
 If reader input is not activated before T3, wait state will be inserted between
T3 and T4.

Instruction formats:
Instruction Definition: A command to the Microprocessor to perform some task.
Need of instruction: A MP is a multi purpose programmable device. It can perform the
required operation by giving commands to it. Without giving any command the microprocessor
is not a useful device. It is a machine, so the user will give commands with the help of
understandable language (Assembly language).
 The representation and size of an instruction is called instruction format.

An instruction can be coded with 1 to 6 bytes

• Byte 1 contains three kinds of information
Opcode field (6 bits) specifies the operation (add, subtract, move)
– Register Direction Bit (D bit) tells the register operand in REG field in byte 2 is source or
destination operand (1: destination, 0: source)
– Data Size Bit (W bit) specifies whether the operation will be performed on 8-bit or 16-bit
data (0: 8 bits, 1: 16 bits)
• Byte 2 has three fields – Mode field (MOD) – Register field (REG) used to identify the register
for the first operand – Register/memory field (R/M field)
Mod/Displacement (00 - If R/M is 110, Displacement (16 bits) is address; otherwise, no
displacement, 01 - Eight-bit displacement, sign-extended to 16 bits, 10 -16-bit displacement,
11 - r/m is treated as a second "reg" field)
The instruction format of 8086 has one or more number of fields associated with it.
a) One byte Instruction:
This format is only one byte long and may have the implied data or register operands.
The least significant 3 bits of the opcode are used for specifying the register operand, if any.
otherwise, all the eight bits form an opcode and the operands are implied.
For example:
CLC: clear carry 11111000 F 8H

This is an operation without any operand, which clear the carry flag bit.

10010 reg
b) Register to Register:
This format is 2 bytes long. The first byte of the code specifies the operation code and
the width of the operand specifies by w bit. The second byte of the opcode shows the register
operands and R/M field.
D7 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

OP CODE D W 11 REG R/M

The register represented by the REG field is one of the operands. The R/M field specifies
another register or memory location, ie., the other operand. The register specified by REG is a
source operand if D  0 , else it is a destination operand.
For example:
MOV : data transfer operation from Register to Register.
Op-code is 100010

100010 d w 1 1 R E G R/M

10001000 11 000 001 88H C1H

REG = 0 0 0 indicates Register AL

REG = 0 0 1 indicates Register CL
w  0 indicates it is a byte operation (8 bit)
d  0 indicates AL is a source register.
This instruction indicates MOV CL, AL, i.e CL  AL
C) Register to/from memory with no displacement:
This format is also 2 bytes long and similar to the register to register format except for
the MOD field.
D7 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

OP CODE d w MOD REG R/M

The MOD field shows the MOD of addressing. In case of no displacement MOD = 00
For example :
MOV: Data transfer Register/memory to/from register.

100010 d w mod reg r/m

This format is similar to register to register transfer. The difference is in mod field.
For register to register, mod = 11
For register to/from memory with no displacement, mod = 00.
When mod = 0 0, the r/m fields indicates the address to memory location.
As for example r/m = 1 1 1 indicates (Bx)
The instruction
1 0 0 0 0 1 0 1 0 0 0 0 0 0 1 1 1 indicates the instruction MOV AX, [BX]
In hexadecimal, the instruction is 8 AH O 7 H

Here the data is present in a memory location in DS whose offset address is in BX. The effective
address of the data is given as 10H  DS   BX 

There d  1 indicates AX is a destination register so it moves the data from memory to register.
d) Register to/from Memory with Displacement:
This type of instruction format contains one or two additional bytes for displacement
along with 2-byte the format of the register to/from memory without displacement.
D7 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D0 D7 D0

opcode MOD REG R/M Low byte of High byte of

displacement displacement

MOD = 0 1 indicates 8 bit displacement (instruction is of size 3 bytes)

MOD = 1 0 indicates 16 bit displacement (instruction is of size 4 bytes)
MOD = 1 1 indicates register to register transfer
MOD = 0 0 indicates memory without displacement
In this case, R/M fields indicates a memory when MOD is not 1 1
R/M = 1 1 1 indicates (BX)
When MOD = 0 1, the offset address is  BX   D8

When MOD = 1 0, the offset address is  BX   D16

e) Immediate operand to register:

In this format, the first byte as well as the 3 bits from the second byte which are used for REG
field in case of register to register format are used for opcode. It also contains one or two bytes
of immediate data.
D7 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D0 D7 D0
Lower byte Higher byte
Op code w 11 op code R/M DATA DATA

When w  0 , the size of immediate data is 8 bits and the size of instruction is 3 bytes.
When w  1 , the size of immediate data is 16 bits and the size of instruction is 4 bytes.
f) Immediate operand to memory with 16-bit displacement:
This type of instruction format requires 5 to 6 bytes for coding. The first two bytes contain the
information regarding OPCODE, MOD and R/M fields. The remaining 4 bytes contain 2 bytes
of displacement and 2 bytes of data.
D7 D0 D7 D6 D5 D4 D3 D2 D1 D0

Op code w MOD op code R/M

D7 D0 D7 D0 D7 D0
Higher byte of Lower byte of data Higher byte of
data data

The different addressing modes of the 8086 instructions along with corresponding MOD, REG
and R/M field are given in the table.
operands Memory operands Register operands
No Displacement Displacement
Displacement 8 bits 16 bits
MOD 00 01 10 11
R/M w0 w 1
000  BX    SI   BX    SI   D8  BX    SI   D16 AL AX

001  BX    DI   BX    DI   D8  BX    DI   D16 CL CX

010  BP    SI   BP    SI   D8  BP    SI   D16 DL DX

011  BP    DI   BP    DI   D8  BP    DI   D16 BL BX

100  SI   SI   D8  SI   D16 AH SP

101  DI   DI   D8  DI   D16 CH BP

110 D16  BP   D8  BP   D16 DH SS

 111  BX   BX   D8  BX   D16 BH DI

D8 and D16 represent 8 and 16 bit displacement respectively.

The default segment for the addressing modes using BP and SP is SS. For all other addressing
modes the default segments are DS or ES.
Addressing Modes
Specifies the location of operand, generally the operands must be present in registers, memory
or directly in the instruction
They are classified as:
Addressing modes for accessing immediate data, data in registers, data in memory
Different addressing modes of 8086:
1. Immediate:
In this addressing mode, immediate data is a part of instruction, and appears in the form
of successive byte or bytes.
ex. MOV AX, 0005H
Here 0005H is the immediate data and it is moved to register AX. The immediate data may be
8-bit or 16-bit in size.
2. Direct:
In the direct addressing mode, a 16 bit address (offset) is directly specified in the
instruction as a part of it.
ex. MOV AX, [1 0 0 0 H]
In direct addressing mode the data resides in a memory location in the data segment, whose
effective address is 10 H  DS  1000 H
3. Register:
In register addressing mode, the data is stored in a register and it is referred using the
particular register. All the registers except IP may be used in this mode.
ex. MOV AX, BX
In register addressing mode the data is transferred from one register to the other, from the
example we can see that the data is transferred from BXAX
4. Register Indirect:
In this addressing mode, the address of the memory location which contains data or
operand is determined in an indirect way using offset registers. The offset address of data is in
either BX or SI or DI register. The default segment register is either DS or ES.
e.g. MOV AX,  BX 
The data is present in a memory location in DS whose offset is in BX. The effective address is
10H  DS   BX 

5. Indexed:
In this addressing mode offset of the operand is stored in one of the index register. DS
and ES are the default segments for index registers SI and DI respectively
e.g. MOV AX,  SI 

The effective address of the data is 10H  DS   SI 

6. Register Relative:
In this addressing mode the data is available at an effective address formed by adding
an 8-bit or 16-bit displacement with the content of any one of the registers BX, BP, SI and DI
in the default either DS or ES segment.
e.g. MOV AX, 50H  BX 

The effective address of the data is 10 H  DS  50 H   BX 

7. Based Indexed:
In this addressing mode the effective address of the data is formed by adding the content
of a base register (any one of BX or BP) to the content of an index register (any one of SI or
DI). The default segment register may be ES or DS.
e.g MOV ,  BX   SI 

The effective address is 10H  DS   BX    SI 

8. Relative Based Indexed:

The effective address is formed by adding an 8-bit or 16-bit displacement with the sum
of contents of any one of the base register (BX or BP) and any one of the index registers in a
default segment.
e.g. MOV AX, 50H  BX  SI 

Here 50H is an immediate displacement. The effective address is

10 H  DS   BX    SI   50 H .

INSTRUCTION SET OF 8086

The 8086 instructions are categorized into eight different groups. Since various instructions are
available to program a microprocessor.
a) Data Transfer Instructions:

This type of instructions are used to transfer data from source operand to destination
operand. All the store, load, move, exchange, input and output operations belong to this category.

b) Arithmetic and Logical Instructions:

All the instructions performing arithmetic, logical, increment, decrement, compare and scan
instructions belong to this category.

c) Branch Instructions:

These instructions transfer control of execution to the specified address. All the call, jump,
interrupt and return instructions belong to this category.

d) Loop Instructions:

The LOOP, LOOPNZ and LOOPZ instructions belong to this category. These are useful to
implement different loop structures.

e) Machine control Instructions:

These instructions control the machine status. NOP, HLT, WAIT and LOCK instructions
belongs to this category.

f) Flag Manipulation Instructions:

All instructions which directly affect the flag register belong to this category. The instructions
CLD, STD, CLI, STI etc. belong to this category.

g) Shift and Rotate Instructions:

These instructions involve the bitwise shifting or rotation in either direction with or without
a count in CX.

h) String Instructions:

These instructions involve string manipulation operations like load, move, scan, compare,
store etc. These instructions are only to be operated upon the string data.

DATA TRANSFER INSTRUCTIONS

MOV – Move data from source to destination
 MOV Destination, Source:
 o The MOV instruction copies a word or byte of data from a specified source to
a specified destination.
o The destination can be a register or a memory location.
o The source can be a register, a memory location or an immediate number.
o The source and destination cannot both be memory locations. They must both
be of the same type (bytes or words).
o MOV instruction does not affect any flag.
MOV CX, 037AH Put immediate number 037AH to CX
MOV AX, BX Copy content of register BX to AX
XCHG – Exchange data from source to destination
XCHG Destination, Source:
 The XCHG instruction exchanges the content of a register with the content of another
register or with the content of memory location(s).
 The source and destination must both be of the same type (bytes or words).
 This instruction does not affect any flag.
XCHG AX, DX Exchange word in AX with word in DX
XCHG BL, CH Exchange byte in BL with byte in CH
LEA – Load Effective address, LEA Register, Source:
 This instruction determines the offset of the variable or memory location named
as the source and puts this offset in the indicated 16-bit register.
 LEA does not affect any flag.
LEA BX, PRICES Load BX with offset of PRICE in DS
LAHF (copy low byte of flag register to AH register)
The LAHF instruction copies the low-byte of the 8086 flag register to AH register. It can then
be pushed onto the stack along with AL by a PUSH AX instruction. LAHF does not affect any
flag.
SAHF (copy AH register to low byte of flag register)
The SAHF instruction replaces the low-byte of the 8086 flag register with a byte from the AH
register. SAHF changes the flags in lower byte of the flag register.
PUSH – PUSH Source
 The PUSH instruction decrements the stack pointer by 2 and copies a word from a
specified source to the location in the stack segment to which the stack pointer points.
 The source of the word can be general-purpose register, segment register, or memory.
  The stack segment register and the stack pointer must be initialized before this
instruction can be used. PUSH can be used to save data on the stack so that it will not
destroyed by a procedure. This instruction does not affect any flag.
PUSH BX Decrement SP by 2, copy BX to stack.
POP – POP Destination
 The POP instruction copies a word from the stack location pointed to by the stack
pointer to a destination specified in the instruction.
 The destination can be a general-purpose register, a segment register or a memory
location. The data in the stack is not changed.
 After the word is copied to the specified destination, the stack pointer is automatically
incremented by 2 to point to the next word on the stack. The POP instruction does not
affect any flag.
PUSHF (push flag register to stack)
The PUSHF instruction decrements the stack pointer by 2 and copies a word in the flag
register to two memory locations in stack pointed to by the stack pointer. The stack segment
register is not affected. This instruction does to affect any flag.
POPF (pop word from top of stack to flag register)
The POPF instruction copies a word from two memory locations at the top of the stack
to the flag register and increments the stack pointer by 2. The stack segment register and word
on the stack are not affected. This instruction does to affect any flag.
IN – IN Accumulator, Portaddress
 The IN instruction copies data from a port to the AL or AX register.
 If an 8-bit port is read, the data will go to AL. If a 16-bit port is read, the data will go
to AX.
 The port address is directly specified in the instruction or indirectly specified using DX
register.
IN AL, 0C8H Input a byte from port 0C8H to AL
OUT – OUT Portaddress, Accumulator
 The OUT instruction copies a byte from AL or a word from AX to the specified port.
 The port address is directly specified in the instruction or indirectly specified using DX
register.
ARITHMETIC INSTRUCTIONS
ADD – ADD Destination, Source &ADC – ADC Destination, Source:
ADD&ADC - Add two numbers with and without carry respectively.
  These instructions add a number from some source to a number in some destination
and put the result in the specified destination. The ADC also adds the status of the carry
flag to the result.
 The source may be an immediate number, a register, or a memory location.
 The destination may be a register or a memory location.
 The source and the destination must be of the same type (bytes or words).
 Flags affected: AF, CF, OF, SF, ZF.
ADD AL, 74H- Add immediate number 74H to content of AL and store the result in AL
ADC CL, BL Add content of BL plus carry to content of CL
SUB – SUB Destination, Source &SBB – SBB Destination, Source:
SUB&SBB - Subtract two numbers with and without borrow respectively.
 These instructions subtract the number in some source from the number in some
destination and put the result in the destination.
 The SBB instruction also subtracts the content of carry flag from the destination.
 The source may be an immediate number, a register or memory location. The
destination can also be a register or a memory location.
 The source and the destination must both be of the same type (bytes or words).
 Flags affected: AF, CF, OF, PF, SF, ZF.
SUB CX, BX CX – BX; Result in CX
SBB CH, AL Subtract content of AL and content of CF from content of CH, Result in CH
MUL – (Unsigned multiplication).
MUL Source:
 This instruction multiplies an unsigned byte in some source with an unsigned
byte in AL register or an unsigned word in some source with an unsigned word
in AX register.
 The source can be a register or a memory location.
 When a byte is multiplied by the content of AL, the result (product) is put in
AX. When a word is multiplied by the content of AX, the result is put in DX
and AX registers.
 CF and OF will both be 0’s. AF, PF, SF and ZF are undefined after a MUL
instruction.
MUL BH - Multiply AL with BH; result in AX
MUL CX- Multiply AX with CX; result high word in DX, low word in AX
IMUL – (Signed Multiplication).
IMUL Source:
 This instruction multiplies a signed byte from source with a signed byte in AL
or a signed word from some source with a signed word in AX.
 The source can be a register or a memory location. When a byte from source is
multiplied with content of AL, the signed result (product) will be put in AX.
 When a word from source is multiplied by AX, the result is put in DX and AX.
AF, PF, SF and ZF are undefined after IMUL.
IMUL AX -Multiply AX times AX; result in DX and AX
DIV – DIV Source:
 This instruction is used to divide an unsigned word by a byte or to divide an
unsigned double word (32 bits) by a word.
 When a word is divided by a byte, the word must be in the AX register.
 The divisor can be in a register or a memory location.
 After the division, AL will contain the 8-bit quotient, and AH will contain the
8-bit remainder.
 When a double word is divided by a word, the most significant word of the
double word must be in DX, and the least significant word of the double word
must be in AX.
 After the division, AX will contain the 16-bit quotient and DX will contain the
16-bit remainder.
 All flags are undefined after a DIV instruction.
DIV BL- Divide word in AX by byte in BL; Quotient in AL, remainder in AH
DIV CX- Divide down word in DX and AX by word in CX; Quotient in AX, and remainder
in DX.
IDIV – IDIV Source
This instruction is used to divide a signed word by a signed byte, or to divide a signed double
word by a signed word.
 When dividing a signed word by a signed byte, the word must be in the AX register.
 The divisor can be in an 8-bit register or a memory location.
 After the division, AL will contain the signed quotient, and AH will contain the signed
remainder.
 The sign of the remainder will be the same as the sign of the dividend.
  When dividing a signed double word by a signed word, the most significant word of
the dividend (numerator) must be in the DX register, and the least significant word of
the dividend must be in the AX register.
 The divisor can be in any other 16-bit register or memory location. After the division,
AX will contain a signed 16-bit quotient, and DX will contain a signed 16-bit
remainder. The sign of the remainder will be the same as the sign of the dividend. All
flags are undefined after an IDIV.
IDIV BL- Signed word in AX/signed byte in BL
IDIV BP- Signed double word in DX and AX/signed word in BP
INC – INC Destination:
 The INC instruction adds 1 to a specified register or to a memory location.
 AF, OF, PF, SF, and ZF are updated, but CF is not affected.
 This means that if an 8-bit destination containing FFH or a 16-bit destination containing
FFFFH is incremented, the result will be all 0’s with no carry.
INC BL Add 1 to contain of BL register
INC CX Add 1 to contain of CX register
DEC – DEC Destination:
 This instruction subtracts 1 from the destination word or byte.
 The destination can be a register or a memory location.
 AF, OF, SF, PF, and ZF are updated, but CF is not affected.
 This means that if an 8-bit destination containing 00H or a 16-bit destination
containing 0000H is decremented, the result will be FFH or FFFFH with no
carry (borrow).
DEC CL- Subtract 1 from content of CL register
DEC BP- Subtract 1 from content of BP register
DAA (decimal adjust after BCD addition):
 This instruction is used to make sure the result of adding two packed BCD
numbers is adjusted to be a legal BCD number.
 The result of the addition must be in AL for DAA to work correctly.
 If the lower nibble in AL after an addition is greater than 9 or AF was set by the
addition, then the DAA instruction will add 6 to the lower nibble in AL.
 If the result in the upper nibble of AL in now greater than 9 or if the carry flag
was set by the addition or correction, then the DAA instruction will add 60H to
AL.
Let AL = 59 BCD, and BL = 35 BCD
ADD AL, BL AL = 8EH; lower nibble > 9, add 06H to AL
DAA AL = 94 BCD, CF = 0
Let AL = 88 BCD, and BL = 49 BCD
DAS (decimal adjust after BCD subtraction):
 This instruction is used after subtracting one packed BCD number from another
packed BCD number, to make sure the result is correct packed BCD.
 The result of the subtraction must be in AL for DAS to work correctly.
 If the lower nibble in AL after a subtraction is greater than 9 or the AF was set
by the subtraction, then the DAS instruction will subtract 6 from the lower
nibble AL.
 If the result in the upper nibble is now greater than 9 or if the carry flag was set,
the DAS instruction will subtract 60 from AL.
Let AL = 86 BCD, and BH = 57 BCD
SUB AL, BH AL = 2FH; lower nibble > 9, subtract 06H from AL
AL = 29 BCD, CF = 0
CMP – CMP Destination, Source
This instruction compares a byte / word in the specified source with a byte / word in the
specified destination.
 The source can be an immediate number, a register, or a memory location. The
destination can be a register or a memory location.
 The comparison is actually done by subtracting the source byte or word from the
destination byte or word.
 The source and the destination are not changed, but the flags are set to indicate the
results of the comparison. AF, OF, SF, ZF, PF, and CF are updated by the CMP
instruction.
NEG – NEG Destination
This instruction replaces the number in a destination with its 2’s complement.
 The destination can be a register or a memory location.
 The NEG instruction updates AF, AF, PF, ZF, and OF.
NEG- AL Replace number in AL with its 2’s complement
LOGICAL INSTRUCTIONS
AND – AND Destination, Source:
  This instruction ANDs each bit in a source byte or word with the same numbered bit in
a destination byte or word. The result is put in the specified destination.
 The source can be an immediate number, the content of a register, or the content of a
memory location.
 The destination can be a register or a memory location.
 CF and OF are both 0 after AND. PF, SF, and ZF are updated by the AND instruction.
AF is undefined. PF has meaning only for an 8-bit operand.
AND CX, [SI]- AND word in DS at offset [SI] with word in CX register; Result in CX register
OR – OR Destination, Source:
 This instruction ORs each bit in a source byte or word with the same numbered bit in a
destination byte or word. The result is put in the specified destination.
 The source can be an immediate number, the content of a register, or the content of a
memory location. The destination can be a register or a memory location.
 CF and OF are both 0 after OR. PF, SF, and ZF are updated by the OR instruction. AF
is undefined. PF has meaning only for an 8-bit operand.
OR AH, CL- CL ORed with AH, result in AH, CL not changed
XOR – XOR Destination, Source
 This instruction Exclusive-ORs each bit in a source byte or word with the same
numbered bit in a destination byte or word. The result is put in the specified destination.
 The source can be an immediate number, the content of a register, or the content of a
memory location.
 CF and OF are both 0 after XOR. PF, SF, and ZF are updated. PF has meaning only for
an 8-bit operand. AF is undefined.
XOR CL, BH- Byte in BH exclusive-ORed with byte in CL.
NOT – NOT Destination
The NOT instruction inverts each bit (forms the 1’s complement) of a byte or word in the
specified destination.
 The destination can be a register or a memory location.
 This instruction does not affect any flag.
NOT BX- Complement content or BX register
TEST – TEST Destination, Source
 This instruction ANDs the byte / word in the specified source with the byte / word in
the specified destination.
  Flags are updated, but neither operand is changed. The test instruction is often used to
set flags before a Conditional jump instruction.
 The source can be an immediate number, the content of a register, or the content of a
memory location. The destination can be a register or a memory location.
 CF and OF are both 0’s after TEST. PF, SF and ZF will be updated to show the results
of the destination. AF is be undefined.
TEST AL, BH- AND BH with AL. No result stored; Update PF, SF, ZF.
ROTATE AND SHIFT INSTRUCTIONS
RCL –(Rotate left through carry) RCL Destination, Count
 This instruction rotates all the bits in a specified word or byte some number of bit
positions to the left.
 The operation circular because the MSB of the operand is rotated into the carry flag and
the bit in the carry flag is rotated around into LSB of the operand.
 CF MSB LSB
 For multi-bit rotates, CF will contain the bit most recently rotated out of the MSB.
 The destination can be a register or a memory location.
 If you want to rotate the operand by one bit position, you can specify this by putting a
1 in the count position of the instruction. To rotate by more than one bit position, load
the desired number into the CL register and put “CL” in the count position of the
instruction.
 RCL affects only CF and OF. OF will be a 1 after a single bit RCL if the MSB was
changed by the rotate. OF is undefined after the multi-bit rotate.
RCR –(Rotate right through carry) RCR Destination, Count
This instruction rotates all the bits in a specified word or byte some number of bit positions to
the right.
 The operation circular because the LSB of the operand is rotated into the carry flag and
the bit in the carry flag is rotate around into MSB of the operand.
 CF MSB LSB
 For multi-bit rotate, CF will contain the bit most recently rotated out of the LSB.
 The destination can be a register or a memory location.
 If you want to rotate the operand by one bit position, you can specify this by putting a
1 in the count position of the instruction.
 To rotate more than one bit position, load the desired number into the CL register and
put “CL” in the count position of the instruction.
 RCR affects only CF and OF. OF will be a 1 after a single bit RCR if the MSB was
changed by the rotate. OF is undefined after the multi-bit rotate.
RCR BX, 1 -Word in BX right 1 bit, CF to MSB, LSB to CF
ROL – (Rotate left without carry) ROL Destination, Count
 This instruction rotates all the bits in a specified word or byte to the left some number
of bit positions.
 The data bit rotated out of MSB is circled back into the LSB. It is also copied into CF.
In the case of multiple-bit rotate, CF will contain a copy of the bit most recently moved
out of the MSB.
 CF MSB LSB
 The destination can be a register or a memory location. If you to want rotate the operand
by one bit position, you can specify this by putting 1 in the count position in the
instruction.
 To rotate more than one bit position, load the desired number into the CL register and
put “CL” in the count position of the instruction.
 ROL affects only CF and OF. OF will be a 1 after a single bit ROL if the MSB was
changed by the rotate.
ROL AX, 1 Rotate the word in AX 1 bit position left, MSB to LSB and CF
ROR –(Rotate right without carry) ROR Destination, Count
 This instruction rotates all the bits in a specified word or byte some number of bit
positions to right.
  The operation is desired as a rotate rather than shift, because the bit moved out of the
LSB is rotated around into the MSB.
 The data bit moved out of the LSB is also copied into CF. In the case of multiple bit
rotates, CF will contain a copy of the bit most recently moved out of the LSB.
 CF MSB LSB
The destination can be a register or a memory location.
ROR BL, 1 Rotate all bits in BL right 1 bit position LSB to MSB and to CF
SAL/SHL – (shift left arithmetic/logical) SAL Destination, Count & SHL Destination,
Count
SAL and SHL are two mnemonics for the same instruction. This instruction shifts each bit in
the specified destination some number of bit positions to the left.
 As a bit is shifted out of the LSB operation, a 0 is put in the LSB position.
 The MSB will be shifted into CF.
 In the case of multi-bit shift, CF will contain the bit most recently shifted out from the
MSB. Bits shifted into CF previously will be lost.
 CF MSB LSB 0
 The destination operand can be a byte or a word. It can be in a register or in a memory
location.
SAL BX, 1- Shift word in BX 1 bit position left, 0 in LSB
SAR – (Arithmetic shift right) SAR Destination, Count
 This instruction shifts each bit in the specified destination some number of bit positions
to the right.
 As a bit is shifted out of the MSB position, a copy of the old MSB is put in the MSB
position. In other words, the sign bit is copied into the MSB. The LSB will be shifted
into CF.
 In the case of multiple-bit shift, CF will contain the bit most recently shifted out from
the LSB. Bits shifted into CF previously will be lost.
 MSB MSB LSB CF
SAR DX, 1- Shift word in DI one bit position right, new MSB = old MSB
SHR –(Shift right logical) SHR Destination, Count
This instruction shifts each bit in the specified destination some number of bit positions to the
right.
  As a bit is shifted out of the MSB position, a 0 is put in its place. The bit shifted out of
the LSB position goes to CF. In the case of multi-bit shifts, CF will contain the bit most
recently shifted out from the LSB. Bits shifted into CF previously will be lost.
 0 MSB LSB CF
 The destination operand can be a byte or a word in a register or in a memory location.
SHR BP, 1 Shift word in BP one bit position right, 0 in MSB
BRANCH INSTRUCTIONS
JMP (unconditional jump to specified destination)
 This instruction will fetch the next instruction from the location specified in the
instruction rather than from the next location after the JMP instruction.
 If the destination is in the same code segment as the JMP instruction, then only the
instruction pointer will be changed to get the destination location. This is referred to as
a near jump.
 If the destination for the jump instruction is in a segment with a name different from
that of the segment containing the JMP instruction, then both the instruction pointer
and the code segment register content will be changed to get the destination location.
This referred to as a far jump. The JMP instruction does not affect any flag.
JMP BX:
This instruction replaces the content of IP with the content of BX. BX must first be loaded with
the offset of the destination instruction in CS. This is a near jump. It is also referred to as an
indirect jump because the new value of IP comes from a register rather than from the instruction
itself, as in a direct jump.
Conditional jump instructions
To change the program sequence these instructions will check the status of conditional flags
and according to it will take the jump.
JA / JNBE (Jump if Above / Jump if Not below or Equal):
After a compare or some other instructions which affect flags, the zero flag and the carry flag
both are 0, this instruction will cause execution to jump to a label given in the instruction. If
CF and ZF are not both 0, the instruction will have no effect on program execution.
CMP AX, 4371H Compare by subtracting 4371H from AX
JA NEXT Jump to label NEXT if AX above 4371H
JAE / JNB / JNC (Jump if above or equal / jump if not below / jump if no carry)
After a compare or some other instructions which affect flags, the carry flag is 0, this instruction
will cause execution to jump to a label given in the instruction. If CF is 1, the instruction will
have no effect on program execution.
JB / JC / JNAE (jump if below / jump if carry / jump if not above or equal)
After a compare or some other instructions which affect flags, the carry flag is a 1, this
instruction will cause execution to jump to a label given in the instruction. If CF is 0, the
instruction will have no effect on program execution.
JBE / JNA (jump if below or equal / jump if not above)
After a compare or some other instructions which affect flags, either the zero flag or the carry
flag is 1, this instruction will cause execution to jump to a label given in the instruction. If CF
and ZF are both 0, the instruction will have no effect on program execution.
JG / JNLE (jump if greater / jump if not less than or equal)
This instruction is usually used after a Compare instruction. The instruction will cause a jump
to the label given in the instruction, if the zero flag is 0 and the carry flag is the same as the
overflow flag.
JGE / JNL (jump if greater than or equal / jump if not less than)
This instruction is usually used after a Compare instruction. The instruction will cause a jump
to the label given in the instruction, if the sign flag is equal to the overflow flag.
JL / JNGE (jump if less than / jump if not greater than or equal)
This instruction is usually used after a Compare instruction. The instruction will cause a jump
to the label given in the instruction if the sign flag is not equal to the overflow flag.
JLE / JNG (jump if less than or equal / jump if not greater)
This instruction is usually used after a Compare instruction. The instruction will cause a jump
to the label given in the instruction if the zero flag is set, or if the sign flag not equal to the
overflow flag.
JE / JZ (jump if equal / jump if zero)
This instruction is usually used after a Compare instruction. If the zero flag is set, then this
instruction will cause a jump to the label given in the instruction.
JNE / JNZ (jump not equal / jump if not zero)
This instruction is usually used after a Compare instruction. If the zero flag is 0, then this
instruction will cause a jump to the label given in the instruction.
JS (jump if signed / jump if negative)
This instruction will cause a jump to the specified destination address if the sign flag is set.
Since a 1 in the sign flag indicates a negative signed number, you can think of this instruction
as saying “jump if negative”.
JNS (jump if not signed / jump if positive)
This instruction will cause a jump to the specified destination address if the sign flag is 0. Since
a 0 in the sign flag indicate a positive signed number, you can think to this instruction as saying
“jump if positive”.
JP / JPE (jump if parity / jump if parity even)
If the number of 1’s left in the lower 8 bits of a data word after an instruction which affects the
parity flag is even, then the parity flag will be set. If the parity flag is set, the JP / JPE instruction
will cause a jump to the specified destination address.
JNP / JPO (jump if no parity / jump if parity odd)
If the number of 1’s left in the lower 8 bits of a data word after an instruction which affects the
parity flag is odd, then the parity flag is 0. The JNP / JPO instruction will cause a jump to the
specified destination address, if the parity flag is 0.
JO (jump if overflow)
The overflow flag will be set if the magnitude of the result produced by some signed arithmetic
operation is too large to fit in the destination register or memory location. The JO instruction
will cause a jump to the destination given in the instruction, if the overflow flag is set.
JNO (jump if no overflow)
The overflow flag will be set if some signed arithmetic operation is too large to fit in the
destination register or memory location. The JNO instruction will cause a jump to the
destination given in the instruction, if the overflow flag is not set.
JCXZ (jump if the CX register is zero)
This instruction will cause a jump to the label to a given in the instruction, if the CX register
contains all 0’s. The instruction does not look at the zero flag when it decides whether to jump
or not.
LOOP (jump to specified label if CX ≠ 0 after auto decrement)
This instruction is used to repeat a series of instructions some number of times.
 The number of times the instruction sequence is to be repeated is loaded into
CX. Each time the LOOP instruction executes, CX is automatically
decremented by 1.
  If CX is not 0, execution will jump to a destination specified by a label in the
instruction. If CX = 0 after the auto decrement, execution will simply go on to
the next instruction after LOOP.
 The destination address for the jump must be in the range of –128 bytes to +127
bytes from the address of the instruction after the LOOP instruction.
 This instruction does not affect any flag.
LOOPE / LOOPZ (loop while CX ≠ 0 and ZF = 1)
 This instruction is used to repeat a group of instructions some number of times, or until
the zero flag becomes 0.
 The number of times the instruction sequence is to be repeated is loaded into CX.
 Each time the LOOP instruction executes, CX is automatically decremented by 1. If
CX ≠ 0 and ZF = 1, execution will jump to a destination specified by a label in the
instruction. If CX = 0, execution simply go on the next instruction after LOOPE /
LOOPZ.
LOOPNE / LOOPNZ (loop while CX ≠ 0 and ZF = 0)
 This instruction is used to repeat a group of instructions some number of times, or until
the zero flag becomes a 1.
 The number of times the instruction sequence is to be repeated is loaded into the count
register CX. Each time the LOOPNE / LOOPNZ instruction executes, CX is
automatically decremented by 1. If CX ≠ 0 and ZF = 0, execution will jump to a
destination specified by a label in the instruction.
 If CX = 0, after the auto decrement or if ZF = 1, execution simply go on the next
instruction after LOOPNE / LOOPNZ
CALL (Call A Procedure)
The CALL instruction is used to transfer execution to a subprogram or a procedure.
There two basic type of calls near and far.
1. A near call
2. a call to a procedure, which is in the same code segment as the CALL instruction. When
the 8086 executes a near CALL instruction, it decrements the stack pointer by 2 and
copies the offset of the next instruction after the CALL into the stack.
3. This offset saved in the stack is referred to as the return address, because this is the
address that execution will return to after the procedure is executed.
4. A near CALL instruction will also load the instruction pointer with the offset of the first
instruction in the procedure.
 5. A RET instruction at the end of the procedure will return execution to the offset saved
on the stack which is copied back to IP.
 A far call is a call to a procedure,
 which is in a different segment from the one that contains the CALL instruction.
 When the 8086 executes a far call, it decrements the stack pointer by 2 and copies the
content of the CS register to the stack.
 It then decrements the stack pointer by 2 again and copies the offset of the instruction
after the CALL instruction to the stack.
 Finally, it loads CS with the segment base of the segment that contains the procedure,
and loads IP with the offset of the first instruction of the procedure in that segment.
 A RET instruction at the end of the procedure will return execution to the next
instruction after the CALL by restoring the saved values of CS and IP from the stack.
RET (Return Execution From Procedure To Calling Program)
 The RET instruction will return execution from a procedure to the next
instruction after the CALL instruction which was used to call the procedure.
 If the procedure is near procedure (in the same code segment as the CALL
instruction), then the return will be done by replacing the IP with a word from
the top of the stack.
 The word from the top of the stack is the offset of the next instruction after the
CALL. This offset was pushed into the stack as part of the operation of the
CALL instruction. The stack pointer will be incremented by 2 after the return
address is popped off the stack.
STRING MANIPULATION INSTRUCTIONS
MOVSB/MOVSW – move string byte/word
 This instruction copies a byte or a word from location in the data segment to a
location in the extra segment.
 The offset of the source in the data segment must be in the SI register.
 The offset of the destination in the extra segment must be in the DI register.
 For multiple-byte or multiple-word moves, the number of elements to be moved
is put in the CX register so that it can function as a counter.
 After the byte or a word is moved, SI and DI are automatically adjusted to point
to the next source element and the next destination element.
 If DF is 0, then SI and DI will incremented by 1 after a byte move and by 2 after
a word move.
  If DF is 1, then SI and DI will be decremented by 1 after a byte move and by 2
after a word move. MOVS does not affect any flag.
LODS / LODSB / LODSW (load string byte into AL or string word into AX)
o This instruction copies a byte from a string location pointed to by SI to AL, or
a word from a string location pointed to by SI to AX.
o If DF is 0, SI will be automatically incremented (by 1 for a byte string, and 2
for a word string) to point to the next element of the string.
o If DF is 1, SI will be automatically decremented (by 1 for a byte string, and 2
for a word string) to point to the previous element of the string.
o LODS does not affect any flag. CLD Clear direction flag so that SI is auto-
incremented
STOS / STOSB / STOSW (store string byte or string word)
 This instruction copies a byte from AL or a word from AX to a memory location
in the extra segment pointed to by DI.
 In effect, it replaces a string element with a byte from AL or a word from AX.
After the copy, DI is automatically incremented or decremented to point to next
or previous element of the string.
 If DF is cleared, then DI will automatically incremented by 1 for a byte string
and by 2 for a word string.
 If DI is set, DI will be automatically decremented by 1 for a byte string and by
2 for a word string. STOS does not affect any flag.
CMPS / CMPSB / CMPSW (compare string bytes or string words)
o This instruction can be used to compare a byte / word in one string with a byte
/ word in another string.
o SI is used to hold the offset of the byte or word in the source string, and DI is
used to hold the offset of the byte or word in the destination string.
 The AF, CF, OF, PF, SF, and ZF flags are affected by the comparison, but the two
operands are not affected.
 After the comparison, SI and DI will automatically be incremented or decremented to
point to the next or previous element in the two strings.
 If DF is set, then SI and DI will automatically be decremented by 1 for a byte string and
by 2 for a word string.
 If DF is reset, then SI and DI will automatically be incremented by 1 for byte strings
and by 2 for word strings.
  The string pointed to by SI must be in the data segment. The string pointed to by DI
must be in the extra segment.
 The CMPS instruction can be used with a REPE or REPNE prefix to compare all the
elements of a string.
SCAS / SCASB / SCASW (scan a string byte or a string word)
 SCAS compares a byte in AL or a word in AX with a byte or a word in ES pointed to
by DI. Therefore, the string to be scanned must be in the extra segment, and DI must
contain the offset of the byte or the word to be compared.
 If DF is cleared, then DI will be incremented by 1 for byte strings and by 2 for word
strings. If DF is set, then DI will be decremented by 1 for byte strings and by 2 for word
strings. SCAS affects AF, CF, OF, PF, SF, and ZF, but it does not change either the
operand in AL (AX) or the operand in the string.
REP / REPE / REPZ / REPNE / REPNZ (PREFIX) (Repeat string instruction until
specified conditions exist)
 REP is a prefix, which is written before one of the string instructions. It will
cause the CX register to be decremented and the string instruction to be repeated
until CX = 0.
 The instruction REP MOVSB, for example, will continue to copy string bytes
until the number of bytes loaded into CX has been copied.
FLAG MANIPULATION INSTRUCTIONS
STC (set carry flag)
This instruction sets the carry flag to 1. It does not affect any other flag.
CLC (clear carry flag)
This instruction resets the carry flag to 0. It does not affect any other flag.
CMC (complement carry flag)
This instruction complements the carry flag. It does not affect any other flag.
STD (set direction flag)
This instruction sets the direction flag to 1. It does not affect any other flag.
CLD (clear direction flag)
This instruction resets the direction flag to 0. It does not affect any other flag.
STI (set interrupt flag)
CLI (clear interrupt flag)
MACHINE CONTROL INSTRUCTIONS
HLT (HALT Processing)
 The HLT instruction causes the 8086 to stop fetching and executing instructions. The
8086 will enter a halt state. The different ways to get the processor out of the halt state are with
an interrupt signal on the INTR pin, an interrupt signal on the NMI pin, or a reset signal on the
RESET input.
NOP (perform no operation)
This instruction simply uses up three clock cycles and increments the instruction pointer
to point to the next instruction. The NOP instruction can be used to increase the delay of a
delay loop. When hand coding, a NOP can also be used to hold a place in a program for an
instruction that will be added later. NOP does not affect any flag.
ESC (escape)
o This instruction is used to pass instructions to a coprocessor, such as the 8087
Math coprocessor, which shares the address and data bus with 8086.
o Instructions for the coprocessor are represented by a 6-bit code embedded in the
ESC instruction.
o As the 8086 fetches instruction bytes, the coprocessor also fetches these bytes
from the data bus and puts them in its queue.
INT – INT Type
The term type in the instruction format refers to a number between 0 and 255, which identify
the interrupt. When an 8086 executes an INT instruction, it will
1. Decrement the stack pointer by 2 and push the flags on to the stack.
2. Decrement the stack pointer by 2 and push the content of CS onto the stack.
3. Decrement the stack pointer by 2 and push the offset of the next instruction after the INT
number instruction on the stack.
4. Get a new value for IP from an absolute memory address of 4 times the type specified in the
instruction. For an INT 8 instruction, for example, the new IP will be read from address
00020H.
5. Get a new for value for CS from an absolute memory address of 4 times the type specified
in the instruction plus 2, for an INT 8 instruction, for example, the new value of CS will be
read from address 00022H.
6. Reset both IF and TF. Other flags are not affected.
INTO (interrupt on overflow)
If the overflow flag (OF) is set, this instruction causes the 8086 to do an indirect far call
to a procedure you write to handle the overflow condition. Before doing the call, the 8086 will
1. Decrement the stack pointer by 2 and push the flags on to the stack.
2. Decrement the stack pointer by 2 and push CS on to the stack.
3. Decrement the stack pointer by 2 and push the offset of the next instruction after INTO
instruction onto the stack.
4. Reset TF and IF. Other flags are not affected. To do the call, the 8086 will read a new value
for IP from address 00010H and a new value of CS from address 00012H.
IRET (interrupt return)
When the 8086 responds to an interrupt signal or to an interrupt instruction, it pushes the flags,
the current value of CS, and the current value of IP onto the stack.
 It then loads CS and IP with the starting address of the procedure, which you
write for the response to that interrupt.
 The IRET instruction is used at the end of the interrupt service procedure to
return execution to the interrupted program.
 To do this return, the 8086 copies the saved value of IP from the stack to IP, the
stored value of CS from the stack to CS, and the stored value of the flags back
to the flag register.
 Flags will have the values they had before the interrupt, so any flag settings
from the procedure will be lost unless they are specifically saved in some way.
LOCK – assert bus lock signal
Many microcomputer systems contain several microprocessors. Each microprocessor has its
own local buses and memory.
 The individual microprocessors are connected together by a system bus so that
each can access system resources such as disk drive or memory.
 Each microprocessor takes control of the system bus only when it needs to
access some system resources.
 The LOCK prefix allows a microprocessor to make sure that another processor
does not take control of the system bus while it is in the middle of a critical
instruction, which uses the system bus.
 The LOCK prefix is put in front of the critical instruction. When an instruction
with a LOCK prefix executes, the 8086 will assert its external bus controller
device, which then prevents any other processor from taking over the system
bus. LOCK instruction does not affect any flag.
WAIT – wait for signal or interrupt signal
 When this instruction is executed, the 8086 enters an idle condition in which it is doing
no processing. The 8086 will stay in this idle state until the 8086 test input pin is made low or
until an interrupt signal is received on the INTR or the NMI interrupt input pins.
ASSEMBLER DIRECTIVES
The logical errors or other programming errors are not found by the assembler. For completing
all these tasks, an assembler needs some hints from the programmer. These types of hints are
given to the assembler using some predefined alphabetical strings called assembler directives,
which helps the assembler to correctly understand the assembly language program to prepare
the codes.
Another type of hint which helps the assembler to assign a particular constant with a label or
initialize particular memory locations or labels with constants is an operator.

 DB: Define Byte: The DB directive is used to reserve byte or bytes of memory
locations in the available memory.
 DW: Define Word: The DW directive serves the same purposes as the DB directive,
but it makes the assembler reserves the number of memory words (16bit) instead of
bytes.
 DQ: Define Quad word: This directive is used to direct the assembler to reserve 4
words (8 bytes) of memory for the specified variable and may initialize it with the
specified values.
 DT: Define Ten Bytes: The DT directive directs the assembler to define the specified
variable requiring 10-bytes for its storage and initialize the 10-bytes with the specified
values.
 ASSUME: Assume Logical Segment Name: The ASSUME directive is used to
inform the assembler, the names of the logical segments to be assumed for different
segments used in the program.
 END: END of Program: The END directive marks the end of an assembly language
program.
 ENDP: END of Procedure: The ENDP directive is used to indicate the end of a
procedure.

PROCEDURE STAR
:
.
STAR ENDP //indicates the end of procedure STAR

 ENDS: END of Segment: This directive marks the end of a logical segment.

DATA SEGMENT

DATA ENDS //indicates the end of segment DATA

 EVEN: Align On Even Memory Address: The EVEN directive updates the location
counter to the next even address, if the current location counter contents are not even,
and assigns the following routine or variable or constant to that address. If the content
of the location counter is already even, then the procedure will be assigned with the
same address.

 EQU: Equate: The directive EQU is used to assign a label with a value or symbol. The
use of this directive is just to reduce the recurrence of the numerical values or constants
in the program code.

LABEL EQU 0500H

 EXTERN: External and PUBLIC: Public: The directive EXTERN informs the
assembler that the names, procedures and labels declared after this directive have
already been defined in some other assembly language module.

 GROUP: Group the Related Segments: This directive is used to form logical groups
of segments with similar purpose or type.

PROGRAM GROUP CODE, DATA, STACK //this statement directs the

loader/linker to prepare an EXE file such that CODE, DATA, STACK segment must
lie within a 64byte memory segment that is named as PROGRAM

 LABEL: The LABEL directive is used to assign a name to the current content of the
location counter. A LABEL directive can be used to make a FAR jump. The label
directive can be used to refer to the data segment along with the data type, byte or word.

DATA SEGMENT
DATAS DB 50H DUP (?)
DATA-LAST LABEL BYTE FAR
DATA ENDS
After reserving 50H locations for DATAS, the next location will be assigned a label
DATA-LAST and its type will be byte and far.

 LENGTH: Byte Length of A Label: This directive is used to refer to the length of a
data array or a string. Not available in MASM.
 LOCAL: The label, variables, constants or procedures declared LOCAL in a module
are to be used only by that particular module.
 NAME: Logical Name of A Module: The NAME directive is used to assign a name
to an assembly language program module.
 OFFSET: Offset of A Label: When the assembler comes across the OFFSET operator
along with a label, it first computes the 16-bit displacement of the particular label, and
replaces the string ‘OFFSET LABEL’ by the computed displacement.
 ORG: Origin: The ORG directive directs the assembler to start the memory allotment
for the particular segment, block or code from the declared address in the ORG
statement.
  PROC: Procedure: The PROC directive marks the start of a named procedure in the
statement. Also the types FAR and NEAR specifies the type of the procedure.
 PTR: Pointer: The POINTER operator is used to declare the type of a label, variable
or memory operand. The operator PTR is prefixed by either BYTE (8-bit quantity)
or WORD (16-bit quantity).
 SEGMENT: Logical Segment: The SEGMENT directive marks the starting of a
logical segment. The started segment is also assigned a name, i.e. label, by this
statement.
 SHORT: The SHORT operator indicates the assembler that only one byte is required
to code the displacement for a jump. This method of specifying jump address saves
memory.
 TYPE: The TYPE operator directs the assembler to decide the data type of the
specified label and replaces the TYPE label by the decided data type.

 GLOBAL: The labels, variables, constants or procedures declared GLOBAL may be

used by other modules of the program.
 ‘+ & -‘Operators: These operators represent arithmetic addition and subtraction
respectively. And are typically used to add or subtract displacements (8 or 16 bit) to
base or index registers or stack or base pointers.

 FAR PTR: This directive indicates the assembler that the label following FARPTR is
not available within the same segment and the address of the bit is of 32 bits i.e. 2 bytes
offset followed by 2 bytes.

 NEAR PTR: This directive indicates that the label following NEAR PTR is in the
same segment and need only 16 bit i.e. 2 byte offset to address it. A NEAR PTR label
is considered as default if a label is not preceded by NEAR PTR or FAR PTR.
 MACRO and ENDM directives: They are used to define macros in assembly language
programs. MACROS are a set of instructions which are intended to do a particular task.
Where ever assembler finds the name of the macro in the main program, it replaces the
set of instructions present in the macro at that place.

Syntax: Macro_name MACRO

..
body of the macro . .
ENDM
Macros:
Macro is also a set of instructions that is intended to perform one particular task. The difference
here is unlike procedures which are stored only once in the memory. Macro definition appears
at all the places of its invocation. That is, in entire set of instructions are will appear in the place
its invocation. So, macros take more space in memory. As there is no need for the control to
jump to a different memory location and since there is no need to remember the return address,
macros are bit faster compare to procedure/subroutines.
Assembly Language Programs
1. The 8 bit data bytes are stored from memory location E000H to E007H. Write 8086 ALP to
transfer the block of data to new location B001H to B008H.
MOV BL, 08H
MOV SI, E000H
MOV DI, B001H
Loop: MOV DL, [SI]
MOV [DI], DL
DEC BL
JNZ loop
HLT
2. A Program to find out the number of even and odd numbers from a given series of 16 bit
hexa decimal numbers.
ASSUME CS: CODE, DS: DATA
DATA SEGMENT
LIST DW 2375H, 0A579H, 0C322H, 0C991H, 0C000H, 0957H
COUNT EQU 06H
DATA ENDS
CODE SEGMENT
START: XOR BX, BX
AGAIN: MOV AX, [SI]
XOR DX, DX
ROR AX, 01
JC ODD
INC BX
JMP NEXT
ODD: INC DX
NEXT: ADD SI, 02
DEC CL
JNZ AGAIN
INT 03H
CODE ENDS
END START
Introduction to Microcontrollers
 Industrial and domestic products like remote controllers, telephone bill printing
machines, automatic power regulators, automatic or semi-automatic washing machines,
microwave ovens, automobiles, engines, indicating and measuring instruments and
similar products requires automation.
 Automation is needed to facilitate the process or mechanism for its operation and
control. Data storage and processing is an integral part of any automatic control system.
 The need is to have a device, so called ‘microcontroller’, which allows controlling the
timing and sequencing of these machines and processes.
 Further, with the help of microcontroller, it is possible to carry out simple arithmetic
and logical operations. Any system that has a remote controller, almost certainly
contains a microcontroller.
 Microcontrollers are single-chip microcomputers, more suitable for control and
automation of machines and processes.
 Microcontrollers have central processing unit (CPU), memory, input/output ports (I/O),
timers and counters, analog-to-digital converter (ADC), digital-to-analog converter
(DAC), serial ports, interrupt logic, oscillator circuitry and many more functional
blocks on chip.
 Figure 1.1 shows a general functional block diagram of microcontroller. Note that there
may be variations in the functional blocks from device to device and from one
manufacturer to another.
 All these functional blocks on a single Integrated Circuit (IC), results into a reduced
size of control board, low power consumption, more reliability and ease of integration
within an application design.
 The usage of microcontrollers not only reduces the cost of automation, but also provides
more flexibility. The designer is little bit relieved from the complex interfacing of
external peripherals like ADC/DACs, etc. and can concentrate on applications and
development aspects.
 The device can be programmed to make the system intelligent. This is possible because
of the data processing and memory capability of microcontrollers.

Fig. 1.1 Generalized Functional Block Diagram of a Microcontroller

Overview of 8051 microcontroller

  Features
The Intel MCS-51 family of microcontrollers consists of various devices and versions.
The salient features of 8051 microcontrollers are given below.
(i) MCS-51 is a family of 8-bit microcontrollers by Intel, designed around HMOS
technology.
(ii) 8-bit CPU.
(iii) On-chip clock oscillator.
(iv) Operating frequency is 12 MHZ.
(v) Available in ROM/EPROM/EEPROM versions.
(vi) 4K bytes of on-chip program memory.
(vii) 128 bytes of on-chip data random access memory.
(viii) 64 KB address space for external data memory.
(ix) 64 KB address space for program memory.
(x) 32 bidirectional I/O lines can be either used as four 8-bit ports or 32 individually
addressable I/O lines.
(xi) Two 16-bit timers or counters
(xii) 21 special function registers.
(xiii) 16 bit address bus multiplexed with port 0 and port 2 and 8-bit data bus
multiplexed with port 0.
(xiv) Full duplex asynchronous receiver transmitter.
(xv) Five vector interrupt structure with two priority levels
(xvi) Bit addressability
(xvii) Powerful bit processing capability.
(xviii) Multiply and divide instructions available.
(xix) Available in CHMOS versions also.

Architecture of the 8051

The block diagram of 8051 microcontroller is shown in Fig. 1.2. The term 8051 refers
here to all the MCS-51 family members, unless specifically mentioned. Similarly 8052 is used
to refer 8032 and 8052 microcontrollers.
 Fig. 1.2 Block diagram of 8051 microcontroller

 Arithmetic and Logic Unit (ALU)

 It performs arithmetic and logic operation on 8-bit operands. ALU performs
arithmetic operations such as addition, subtraction, multiplication, division, etc.
similarly logical operations such AND, OR, NOT, EX-OR, etc.
 Most of the arithmetic and logical operations are done by using accumulator i.e. A
register.
 In those operations one of the operand is in ‘A’ register. After the arithmetic/logical
operations are performed, the result is stored in ‘A’ register.
 ALU affects various flags namely carry, auxiliary carry, overflow, and parity flags
of status register.

 Instruction decoder and control:

 The instruction decoder and control are parts of timing and control unit. When an
instruction is fetched from program memory it is loaded in the instruction register.
 The decoder decodes the instruction and establishes the sequence of events to
follow.
 The instruction register is not programmable and cannot be accessed through any
instruction. The timing generation and control unit synchronizes all the
 microcontroller operations with the clock and generates control signals necessary
for communication between the processor and peripherals.

 Oscillator
 All the 8051 family members use an external crystal for oscillator function. The
frequency of operation can be depending upon the individual device.
 Data sheets of the device can be referred to see the operating frequencies supported
by a typical device. For example, 80C51 operates at 12 MHz frequency.
 Actually, most of the time, the common frequency is 11.0592 MHz because many
devices actually run at frequencies below or up to 12 MHZ.
 The slight lower frequency allows one of the timers to generate clock frequency for
the baud rate of 9600 baud for the operation of serial port. It must be noted that only
it is necessary to connect the quartz crystal externally and all the other oscillator
circuit is on-chip.

 Functional description of the 8051

 The internal architecture of 8051 is shown in Fig. 1.2. The instruction decoding and
control signal generation, are performed using the timing and control circuit block.
 The bidirectional ports P0 to P3 have the basic structure containing drivers and
latches.
 The port drives are connected to I/O ports, where as latches are connected to the
internal bus of the microcontroller.
 The 8051 contains 128 bytes RAM as data memory and 4 KB ROM as program
memory, on the chip. Internal data RAM with address register is connected to the
internal bus.
 The address register will get the address from the internal bus and data will be
transferred to the specified register through the bus.
 In order to access the internal program memory as well as the external program
memory, the program address register is interfaced to program counter which in
turn is connected to the increment circuit for incrementing the pc.
 A bidirectional buffer has been provided to temporarily store the branch address as
well as the operand address information. this will also facilitate the transfer of the
program counter to the other circuits to calculate PC relative jump address.
 Ports P0 and P2 also facilitate the connection to the external memory. The lower
order address bits (A0 to A7) are sent through Port 0 (port 0.0 to port 0.7), A8 to
A15 are sent through port 2 (port 2.0 to port 2.7).
 Data pointer register (DPTR) is interfaced to the address register. It plays a major
role in external program and data memory addressing using MOVC and MOVX
instructions.
 Two temporary registers TMP1 and TMP2 are connected to ALU. These registers
hold the operands for calculation. The PSW register is directly interfaced to ALU
to update based on the last operation.
 Port 3 pins are used for input/output for serial I/O (P 3.0 & P 3.3), external interrupt
inputs (P 3.2 & P 3.3), timer inputs ( P 3.4 & P 3.5) and external data memory write
and read strobes (P 3.6 & P 3.7).
 There is an alternate connection of port 3 drivers to timer, interrupt and serial port
circuit blocks. The specific special function registers to program and control these
functions are contained in these circuit blocks.
Registers in MCS-51
There are three types of registers in 8051
 General purpose or working registers
 Stack pointer and program counter
 Special function registers.

 General purpose or working registers:

Accumulator, B-register and four register banks may be used as general purpose
registers. Table 1.1 shows the general purpose registers.
Table 1.1 General purpose or working registers.
Register symbol Description

Accumulator or A-register 8-bit

B-register 8-bit

R0 through R7 Bank 0: 00-07 H

(There are four register banks in the on-chip Bank 1: 08-0F H

RAM, each having 8-bit wide registers R0
through R7) Bank 2: 10-17 H

Bank 3: 18 -1FH

 Accumulator: Similar to 8085 microprocessor 8051 microcontroller has an 8-

bit accumulator. Accumulator is used by all the arithmetic and logical instructions.
Accumulator has a special importance in the sense that, one of the operand is stored
in it before the execution of an instruction and it also stores the result after the
execution of an instruction. Accumulator of 8051 is also referred to as ‘A’ register.
Access to accumulator is faster than access to main memory. Accumulator has
direct path to ALU and can immediately store the intermediate result of operation,
also, accumulator is a bit addressable register, it is also used in indexed addressing
mode to access information from program memory.
 B register (F0 H): It is an 8-bit register, which is used during multiply and division
operations. In multiplication operation, one of the 8-bit operand is stored in ‘B’
register. After the operation, it stores the higher byte of the result in B register. In
division operation, it holds 8-bit divisor and after the operation remainder is stored
in B register. For other instructions, it can be used as an 8-bit general purpose
register also B is a bit addressable register.
 Registers R0 through R7: These 8-bit registers are used as scratch pad registers.
There are four register banks each containing R0 through R7 registers. Each of these
registers is 8-bit wide. At a time only one bank can be selected by appropriate setting
of bits in the program status word (PSW). These register banks are located in the
on-chip RAM. That way, effectively selecting register banks can allow 32 registers
to be used while writing programs. Certain instructions can access these registers in
RAM directly. Power-up reset causes bank 0 to be selected by default. Now if one
were writing byte in R4, it would be stored at RAM location 04H. If in another case,
the programmer is selecting bank 1 and writing a byte in R4, it would store the byte
at RAM location 0CH. The advantage of this type of access to general purpose
 registers is that for programmer it becomes simpler to refer those by register names
R0, R1 etc. Table 1.1 shows the address ranges of the four register banks. Figure
1.2 shows the four register banks located in the on-chip RAM.

Fig 1.3 Four register banks and their locations in the On-Chip RAM

 Stack pointer and Program counter

 Stack pointer: Stack pointer of 8051 is 8-bit wide, it is incremented during
push or call operations and is decremented during POP or return operation. It
may be initialized anywhere in the available on-chip data RAM i.e locations
from 0-127. After the RESET operation, the stack pointer is initialized to 07 H,
causing stack to begin at 08 H.
 Program counter (PC): The program counter in 8051 is 16 bit register, and it
can address 64 K code bytes. The 16 bit program counter specifies the address
of the next instruction to be executed. PC always points to the instruction to be
fetched and is automatically incremented after fetching the instruction. PC is
affected by CALL and Jump instructions. After reset, PC will be set to 0000H
and the CPU will start executing the first execution stored at program memory
location 0000H. Note that only PC register has no (internal) on-chip RAM
address. Table 1.2 shows the stack pointer and program counter and their
addresses.

Table 1.2 Stack pointer and Program counter

Register symbol Register name Address

SP (8) Stack pointer 81 H

PC (16) Program Counter NO ADDR

 Special Function Registers (SFR)

As the name itself suggests, these registers have some special functions like controlling
the timer/counter, enabling interrupts, controlling the serial port operations, etc. The
128 bytes of on-chip additional RAM locations from 80H to 0FFH are reserved for the
special function registers (SFRs). There are 21 special function registers in the 8051.
Some special function registers are bit addressable. The various special function
registers are shown in Table 1.3.

Table 1.3 Special Function Registers.

SFR symbol Register name Address

ACC* Accumulator 0E0H

B* B-register 0F0H

P0* Port 0 80H

P1* Port 1 90H

P2* Port 2 0A0H

P3* Port 3 0B0H

IP* Interrupt priority control 0B8H

IE* Interrupt Enable Control 0A8H

TMOD Timer/Counter Mode Control 89H

T2CON (Only in 8052) Timer/Counter 2 control 0C8H

TCON* Timer/Counter control 88H

TH0 Timer/Counter 0 (high byte) 8CH

TL0 Timer/Counter 0 (low byte) 8AH

TH1 Timer/Counter 1 (high byte) 8DH

TL1 Timer/Counter 1 (low byte) 8BH

TH2 (only in 8052) Timer/Counter 2 (high byte) 0CDH

TL2 ( only in 8052) Timer/Counter 2 (low byte) 0CCH

RCAP2H (only in 8052) Timer/Counter 2 Capture register (high byte) 0CBH

RCAP2L (only in 8052) Timer/Counter 2 Capture register (low byte) 0CAH

SCON* Serial control 98H

SBUF Serial data buffer 99H

PCON Power control 97H

PSW* Program status word 0D0H

DPTR Data pointer

DPH Data pointer (high byte) 83H

DPL Data pointer (low byte) 82H

Registers marked with ‘*’ are bit addressable as well as byte addressable.

 Program Status Word: Program status word or simply PSW, is an 8-bit register,
it consists of carry, auxiliary carry, overflow, and parity flags, also RS1 and RS0
for register bank selection. The PSW is a bit addressable register, each bit of the
PSW is referred as PSW.X. Thus PSW.0 is the LSB, which is a parity flab, and the
MSB PSW.7 is the carry flag. Figure 1.4 shows the program status word.
MSB LSB
C AC F0 RS1 RS0 OV ---- P

Fig. 1.4 Program status word

 Bit 7 (Carry/ Borrow flag) PSW.7: When two 8-bit operands are added, the
result may exceed 8-bit ( may exceed 255 or FFH), and the 9th bit is copied in
the carry bit. During subtraction, if the borrow occurs, the carry bits is set and
otherwise it is cleared. Similarly, SETB C and CLR C instructions can also
change carry bit.
 Bit 6 (Auxiliary carry/ Borrow) PSW.6: This bit indicates a carry from the
lower nibble during 8-bit addition. If auxiliary carry flag is set, it means there
is a carry from 3rd to 4th position. In subtraction, if there is a borrow from 4th bit
to 3rd bit position, then AC is set, else it is cleared.
 Bit 5 (F0): F0 is available to user as a general purpose flag. This flag can be
set/cleared by software or its status can be observed by software.
 Bit 4 & 3: Register Bank select bits RS1 and RS0: These are bits for selecting
one of the four register banks each of these register banks consists of registers
R0 through R7. When power up reset, bank 0 is selected as a default register
bank and both RS1 and RS0 bits are cleared. Table 1.4 shows the address ranges
of four register banks along with RS1 and RS0 bits. Each bank contains 8-bit
registers.

Table 1.4 Register Bank Select Bits

RS1 RS0 Register bank selected Address range in the on-chip RAM

0 0 Bank 0 00-07 H

0 1 Bank 1 08-0F H

1 0 Bank 2 10-17 H

1 1 Bank 3 18-1F H

 Bit 2 (Over flow flag): OV flag is used to detect errors in signed arithmetic
operations. when two signed numbers are added, if the result exceeds the
destination, overflow flag is set, else it is reset. OV is set, if there is a carry from
D6 to D7 but no carry D7 or if there is a carry from D7 but no carry from D6 to
D7.
 Bit 0 (Parity flag): Parity flag indicates the number of 1’s in accumulator.
Parity flag is set, if the result contains an even number of 1 bit, else it is reset,
if the result contains an odd number of 1 bit.
  Timer Register: Registers pairs (TH0, TL0), (TH1, TL1), (TH2, TL2) form 16-bit
timer/counter registers 0, 1,2 respectively. There are instructions for reading and
writing these registers byte-wise. Timer/counter 2 is only available in 8052. The
operation may be timing or counting. Further there are various modes in which
timers can be configured. For this purpose there are Timer control (TCON) and
timer mode registers (TMOD).
 Control and status registers: All the special function registers (like IP, IE, TMOD,
TCON, PCON, SCON etc) that are used for controlling the internal resources or to
see the status of these registers. These registers contain the control and status bits
of the interrupt systems, timers, and serial port operations.
 Serial data Buffer (SBUF): This register holds the data that has to be
transmitted through the serial port and holds the data that is received. This register
is interconnected to two 8-bit shift registers. When data is written into the SBUF, it
is loaded in the transmit shift register and hence the process of moving a data byte
into the SBUF starts the transmission process. During the reception, the data coming
to the 8051 is clocked into the receive shift register and once all the 8-bits of data
of a frame is received, it is transferred to the SBUF.
 Capture Registers: Register pair (RCAP2H-RCAP2L) are the capture registers for
the timer 2. These are available only in 8052, for timer 2 capture mode operation.
In capture mode, a transition at the 8052 T2EX pin causes TH2 and TL2 to be
copied into RCAP2H and RCAP2L. Timer 2 is also has a 16-bit auto reload mode
and RCAP2H and RCAP2L hold the reload value for this mode.

8051 PIN DESCRIPTION

The pin diagram of 8051 microcontroller is shown in Fig.1.5, which is a 40 pin DIP.
The crystal frequency is the basic clock frequency of the microcontroller. The 8051 requires a
+5V single power supply and is designed for minimum 1MHz clock frequency to maximum
16 MHz clock frequency. A brief discussion of these pins is given below.

Fig. 1.5 Pin configuration of 8051 Microcontroller

  Vcc (Pin 40): Vcc pin is connected to +5V power supply with rated current 125 mA.
In 8051, maximum power dissipation rating is 1W.
 Vss (Pin 20):Vss is connected to ground reference.
 XTAL 2 (Pin 18) & XTAL 1 (Pin 19): The 8051 has an internal clock circuit,
hence a crystal of proper frequency can be connected directly to these pins. The
frequency range is 3.5 MHz -12MHz. An external oscillator can also be connected
instead of a crystal. In this case, the XTAL1 pin is grounded and the oscillator signal
is given to the XTAL 2 pin.
 𝐏𝐒𝐄𝐍 (Pin 29): This pin gives out active low output pulses. This signal is used
for fetching the data from the external program memory. A pulse is generated after
every six clock pulses, which is used as a read signal for reading from the external
program memory. If the data to be fetched is inside the chip itself, then PSEN is not
generated.
 Port 0 (Pins 32-39): Port 0 is an 8-bit bi-directional open drain I/O. Low order
address and data bus is also multiplexed with Port 0. Port 0 is open drain and must
be pulled high externally through a pull-up resistor.
 Port 1 (Pins 1-8): Port 1 is an 8-bit quasi-bi-directional port is due to the fact that
Port 1 pins are internally pulled high with fixed pull-up resistors. One has to
configure it either as a input or output. Writing a ‘1’ to the port latch causes it to act
as input. When configured as input, the port pin is pulled high and will source
current if it is made low externally.
 Port 2 (Pins 21-28): Port 2 is also an 8-bit quasi bi-directional I/O port. Port pins
are pulled high internally. It is multiplexed with the higher order address bus.
 Port 3 (Pins 10-17): Port 3 is again an 8-bit quasi bi-directional I/O port. Port pins
are pulled high internally. There are other functions multiplexed with port 3 pins.
The alternate functions are listed in Table 1.5. These alternate functions of Port 3
are related to external interrupts, serial port, timer/counter and read/write control
signals.

Table 1.5 Alternate Functions of Port 3 Pins

P3.0 RXD serial input

P3.1 TXD serial output

P3.2 INT0 external interrupt

P3.3 INT1 external interrupt

P3.4 T0 timer/counter 0 external interrupt

P3.5 T1 timer/counter 1 external interrupt

P3.6 WR external data memory write strobe

P3.7 RD external data memory read strobe

 RST/ VPD (Pin 9): The microcontroller provides a reset mechanism to establish initial
conditions. The special function registers and few CPU registers must be initialized
before the microcontroller can operate properly. If the reset pin is high for more than
 24 oscillator cycles (2 Machine cycles), will reset the chip. VPD may be used to supply
power to the internal RAM during power failure or power down modes.
 𝐄𝐀 /VPP (Pin 31): External access (EA) pin, when held high, executes instruction from
the internal program memory till address 0FFFH, beyond this address, the instructions
are fetched from external program memory. If this pin is low, all the instructions are
fetched from the external memory, during normal operation, this pin should not be
floated.
 ALE (Pin 30): Address latch enable (ALE) output is used for latching the low address
byte during external memory access, ALE is activated periodically with a constant rate
of 1/6 the oscillator frequency. However, during the external data memory access, one
ALE pulse is skipped.

8051 CONNECTIONS

Before discussing the programming of microcontrollers, let us see the 8051 connection
diagram and the minimum hardware environment. This is shown in Fig. 1.6. The
oscillator connections, reset circuitry, power supply connections are basically needed
to design any 8051 based board, for any application in general.

 Oscillator Circuit
 8051 has on-chip oscillator. Only the frequency determining components (crystal)
are to be connected externally.
 30 pF disc capacitors are recommended when a quartz crystal is used.8051 can work
up to 12 MHz.

Fig. 1.6 8051 Connections, Oscillator and Reset Circuit

 For low-cost designs, one may go for 3-pin ceramic resonators. For ceramic
resonators, the capacitor values are typically 47 pF.
 Recommendations by the manufacturer of ceramic resonators must be considered
for the values of these capacitors. Normally, a quartz crystal is preferred, because
resonators are not available for higher frequencies of the order of 12 MHz.
  The reduction in cost due to the use of resonators may be negligible as compared
with the total cost of a microcontroller board. Further, resonators are not as stable
as the quartz crystals. MCS-51 also supports an external clock. This is shown in
Fig. 1.6.

Fig. 1.7 External Clock source for: (a) CHMOS MCS-51 Parts, (b) HMOS Parts

 When external clock is used, pin XTAL2 is left floating in case of CHMOS MCS-
51 parts. There is one important difference between HMOS and CHMOS parts of
MCS-51, as far as the external clock source is concerned. For CHMOS parts
(80C51), the internal clocking circuitry is driven by the signal at XTAL 1. In case
of HMOS versions, the external clock source needs to be connected to XTAL 2 and
XTAL 1 is to be grounded.

8051 I/O PORTS

As seen earlier, 8051 has four 8-bit I/O ports that are used either as four 8-bit ports or
each of the port pins could be addressed individually. Figures 1.8 and 1.9 shows the
8051 I/O port structures. Each port consists of a latch, an output driver and an input
buffer. The bit latch is shown as D flip-flop, which clocks in a value from the internal
data bus in response to

Fig. 1.8 A Quasi-bi-directional Port

 Fig. 1.9 A True bi-directional Port (Port 0 of 8051)

 The write to latch signal from the CPU. The Q output from the flip-flop can be read on
to the internal data bus in response to a Read Latch signal from the CPU. Read pin is a
different operation from reading a latch. The port pin status can be read onto the internal
data bus when CPU gives a ‘read pin’ command.
 Ports 1, 2 and 3 : Ports 1, 2 and 3 are quasi-bi-directional ports and have fixed internal
pull-up resistors. Figure 1.8 shows a quasi-bi-directional port. Ports 1, 2 and 3 when
configured as input, they are pulled high and source current if externally pulled low.
For configuring a port pin as input, a ‘1’ must be written to a port latch. This turns 0FF
the FET and the pin is simply pulled high by the pull-up resistor, the external device
may pull it low.
 The pin status can now be read onto the internal data bus. On reset, 8051 port latches
have 1’s written to them and configured as inputs. One can drive the pin as output at
any time; however, for input the FET must be 0FF. If the pin is to be used as output
writing a ‘0’ on to a pin requires that the FET should be ON. Similarly, to write a ‘1’
onto the pin, the FET should be 0FF, outputting a’1’ because of the pull-up resistor.
One important thing that must be observed here is that the 8051 ports can sink more
current than it can source. Port pins can sink around 0.5 mA but can source only tens
of µA.
 Port 0: Port 0 does not have internal pull-up resistors. When configured as an input, it
floats and is therefore a true bi-directional port. Port 0 structure can be seen from Fig.
1.9. It has two output FETs. For normal operation, the upper pull-up FET is OFF,
providing ‘open drain’ output pin and external pull-up resistor is required. If a ‘1’ is
written to a port 0 latch, either FETs go OFF and the pin floats and can be used as high-
impedance input.
 The pull-up FET only operates when there is an access to external memory. Port 0
output buffers can drive 8 LS TTL inputs. The output drivers of Port 0 (and also Port
2) can be switched to an internal ADDR (and ADDR/DATA) bus by using an internal
control signal while accessing the external memory. When used as ADDR and
ADDR/DATA bus, Port 0 and port 2 pins, respectively, cannot be used as general-
purpose I/Os.

Memory Organization
  The MCS-51 has 64K external data memory, 64K program memory and 256 bytes
of internal data memory. The program memory map of 8051 is shown in Fig. 1.10.
 The 64K program memory space of 8051 is divided into internal and external
memory.
 If the EA pin is high, then 8051 executes from the internal program memory until
the address exceeds 0FFFH.

Fig. 1.10 Program memory of 8051

Fig. 1.11 Internal and External Data Memory of 8051

Table 1.6 Program memory of 8051 and program execution

status of 𝐄𝐀 Program execution from 0000H Program execution from
pin through 0FFFH 1000H through 0FFFFH
 High(1) Internal program memory External program memory

Low (0) External Program memory External Program memory

 After that, locations 1000H through 0FFFFH are executed from the external
memory portion. If EA pin is held low, then 8051 executes instructions from
external memory only.
 Table 1.6 shows this. The external 64 K data memory can be accessed using MOVX
instruction. Figure 1.11 shows the internal and external data memory of 8051.
 The internal data memory of 8051 is 256 bytes, which is divided into two parts
again. The lower 128 bytes (00H through 7FH) called as internal data RAM and the
upper 128 bytes (80 through FFH) consists of special function registers (SFRs).
 In case of 8032/52, the upper 128 bytes of internal data memory are also
addressable. Even though the SFRs and upper 128 bytes of RAM have the same
address space, they are different and accessed through different addressing modes.

8051 addressing modes

The CPU can access data in various ways. The data could be in a register, or in a
memory, or be provided as an immediate value. These various ways of accessing data are called
addressing modes. The 8051 provides total of five distinct addressing modes.
(i) Immediate addressing mode
(ii) Register addressing mode
(iii) Direct addressing mode
(iv) Register Indirect addressing mode
(v) Indexed addressing mode

 Immediate addressing mode

In immediate addressing, as the name implies, when the instruction is assembled, the
operand comes immediately after the opcode. Note that immediate data must be preceded by
the pound sign “#”. This addressing mode can be used to load information into any of the
registers, including the DPTR register.
Ex: MOV A, #25H : Load 25H into A
MOV R4, #62 : Load the decimal value 62 into R4
MOV DPTR, #4521H : DPTR = 4521H
Although, the DPTR is 16 bit, it can also be accessed as two 8-bit registers, DPH and DPL.
Ex: MOV DPTR, #2550H
MOV DPL, #50H
MOV DPH, #25H
Also note that we can also us immediate addressing mode to send data to ports
Ex: MOV P1, #55H

 Register addressing mode

Register addressing mode involves the use of registers to hold data to be manipulated.
Ex: MOV A, R0 : Copy the contents of R0 into A
MOV R2, A : Copy the contents of A into R2
ADD A, R5 : add the contents of R5 to contents of A
It should be noted that the source and destination registers must match in size, otherwise an
error will be occurred.
  Direct addressing mode
The 8051 contains 128 bytes of RAM. The RAM has been assigned addresses 00 to
7FH as shown below
(i) RAM locations 00-1FH are assigned to the register banks and stack.
(ii) RAM locations 20-2FH are set aside as bit-addressable space to save single bit data
(iii) RAM locations 30-7FH are available as a place to save byte-sized data.
Although the entire 128 bytes of RAM can be accessed using direct addressing mode but it
is most often used to access RAM locations 30-7F RAM locations 00-1FH are assigned to the
register banks and stack.
In direct addressing mode, the data is in a RAM memory location whose address is
known, and this address space is given as a part of the instruction. This addressing mode is
similar to immediate addressing mode but ‘#’ sign distinguishes the two modes.
Ex: MOV R0, 40H ; Save content of RAM location 40H in R0
MOV 56H, A ; Save content of A in RAM location 56H

 Indirect addressing or Register Indirect addressing mode

Indirect addressing provides a powerful addressing capability. In the register indirect
addressing mode, a register is used as a pointer to the dat. Registers R0, R1 and DPTR are the
only registers that can be used as a data pointers.

8051 INSTRUCTION SET

The instruction set of MCS-51 consists of data transfer instructions, arithmetic
instructions, logical instructions, Boolean variable manipulation instructions and control
transfer instructions. There are 111 instructions supported by MCS-51. The instructions can
further be classified as single-byte, two-byte and three-byte instructions. There are 45 single
byte instructions, 45 two byte instructions, and 17 three byte instructions.

 Data transfer instructions

Data transfer instructions of 8051 are MOV, MOVX, MOVC, PUSH, POP and
exchange XCHG, XCH instructions. Data transfer instructions do not affect any of the PSW
flags. However, if there is a MOV or POP directly to PSW, it can affect the PSW. Signed and
unsigned addition and subtraction by using OV flag. BCD arithmetic is also possible on packed
BCD. There are unsigned multiplication and division operations directly supported by the
instructions. Table 6.8 lists the arithmetic instructions.

 Logical Instructions

Bitwise logical AND, OR, EXCLUSIVE-OR operations are possible in MCS-51. These
instructions accept two 8-bit operands and the result is stored at the destination, no flags are
affected by ANL, OR and XOR instructions. There are single-operand instructions lick CLR,
SETB and CPL. Rotate instructions RR, RRC, RL, RLC, and swap instruction SWAP. It is
important to note that the CPL instruction complements the accumulator without affecting any
of the flags. Rotate instructions RL and RR do not affect any flag. However, RLC and RRC
instructions modify CY flag. RLC instruction moves bit-7 of the accumulator into CY position.
Similarly RRC instruction moves bit-0 of the accumulator into CY-flag. SWAP A instruction
simply interchange the lower and higher nibbles of the accumulator and no flags are affected.
Logical instructions are listed in Table 1.9
  Boolean Variable Manipulation Instructions

Operands for Boolean variable manipulations are defined in these instructions. In case
of two operand instructions, there is a destination bit and source bit. For example, MOV
instruction has two single-bit operands. OR, AND operations with two single-bit operands are
possible. Single-operand instructions CLR, SETB, CPL modifies the bit location specified in
the instruction. Table 6.10 shows the Boolean Manipulation instructions.
There are instructions that test a specified bit and transfer control to the desired location.
For example, JC instruction transfers control to the location specified by the relative address,
if the Cary bit is set, 8-bit relative address is in 2’s complement form and it is possible to
transfer the control within a range from -128 to 127 bytes, relative to the first byte of the
following instructions. Similarly, it is possible to test any direct bit and transfer the control.
In case of JC, JNC, JB, JNB instructions, the bit under test is not modified and no flags
are affected. However, it is important to note that JBC instruction transfers the control to the
relative address specified, if the bit is set, and clears the bit specified in the instruction.

 Program Branching instructions

Both conditional branch and unconditional branch operations are possible in MCS-51.
There are jump, call and return instructions. Jump instructions are of three types: short jumps
(SJMP), long jumps (LJMP) and absolute jumps (AJMP). A short jump transfers control within
a 256 byte range, which is from -128 to +127 bytes relative to the first byte of the following
instruction. Absolute jump allows 11-bit address to be specified in the instruction. The
destination must be within 2K block of the program memory from the next instruction followed
by AJMP instruction. In case of LJMP instruction, a 16-bit address is specified in the
instruction and a jump to anywhere within the 64K block of program memory is possible.
Similar to absolute and long jumps, there are absolute calls (LCALL) instruction, is possible.
LCALL uses a 16-bit address in the instruction and subroutine anywhere within 64K-program
memory block can be called. There are conditional jumps JZ, CJNE, DJNZ, JZ rel instruction
tests the accumulator for zero and then transfers control to the address in the program memory
given by the relative address. CJNE instruction compares the first operand with the second
operand and then performs branch operation if the operands are not equal. DJNZ instruction
decrements the source operand and the result is stored in the source operand. A jump is made
to the relative address if the result is not zero.. DJNZ can be used to implement the software
delay routines. Apart from these, there are RET and RETI instructions. RETI and RET both
transfer control to the return address stored on the stack; the only difference is that in addition
to the return function, RETI instruction enables interrupts of the current priority level, All the
program branching instructions are listed in Table 1.11.

Arithmetic Operations

Mnemonic Description Size

Cycles
ADD A,Rn Add register to Accumulator (ACC). 1 1
ADD A,direct Add direct byte to ACC. 2 1
ADD A,@Ri Add indirect RAM to ACC . 1 1
ADD A,#data Add immediate data to ACC . 2 1
ADDC A,Rn Add register to ACC with carry . 1 1
ADDC A,direct Add direct byte to ACC with carry. 2 1
ADDC A,@Ri Add indirect RAM to ACC with carry. 1 1
ADDC A,#data Add immediate data to ACC with carry. 2 1
SUBB A,Rn Subtract register from ACC with borrow. 1 1
SUBB A,direct Subtract direct byte from ACC with borrow 2 1
SUBB A,@Ri Subtract indirect RAM from ACC with borrow. 1 1
SUBB A,#data Subtract immediate data from ACC with borrow. 2 1
INC A Increment ACC. 1 1
INC Rn Increment register. 1 1
INC direct Increment direct byte. 2 1
INC @Ri Increment indirect RAM. 1 1
DEC A Decrement ACC. 1 1
DEC Rn Decrement register. 1 1
DEC direct Decrement direct byte. 2 1
DEC @Ri Decrement indirect RAM. 1 1
INC DPTR Increment data pointer. 1 2

MUL AB Multiply A and B Result: A <‐ low byte, B <‐ high byte. 1 4
DIV AB Divide A by B Result: A <‐ whole part, B <‐ remainder. 1 4
DA A Decimal adjust ACC. 1 1

Logical Operations

Mnemonic Description Size

Cycles

ANL A,Rn AND Register to ACC. 1 1

ANL A,direct AND direct byte to ACC. 2 1
ANL A,@Ri AND indirect RAM to ACC. 1 1
ANL A,#data AND immediate data to ACC. 2 1
ANL direct,A AND ACC to direct byte. 2 1
ANL direct,#data AND immediate data to direct byte. 3 2
ORL A,Rn OR Register to ACC. 1 1
ORL A,direct OR direct byte to ACC. 2 1
ORL A,@Ri OR indirect RAM to ACC. 1 1
ORL A,#data OR immediate data to ACC. 2 1
ORL direct,A OR ACC to direct byte. 2 1
ORL direct,#data OR immediate data to direct byte. 3 2
XRL A,Rn Exclusive OR Register to ACC. 1 1
XRL A,direct Exclusive OR direct byte to ACC. 2 1
XRL A,@Ri Exclusive OR indirect RAM to ACC. 1 1
XRL A,#data Exclusive OR immediate data to ACC. 2 1
XRL direct,A Exclusive OR ACC to direct byte. 2 1

XRL direct,#data XOR immediate data to direct byte. 3 2

CLR A Clear ACC (set all bits to zero). 1 1
CPL A Compliment ACC. 1 1
RL A Rotate ACC left. 1 1
RLC A Rotate ACC left through carry. 1 1
RR A Rotate ACC right. 1 1
RRC A Rotate ACC right through carry. 1 1
SWAP A Swap nibbles within ACC. 1 1

Data Transfer

Mnemonic Description Size

Cycles
MOV A,Rn Move register to ACC. 1 1
MOV A,direct Move direct byte to ACC. 2 1
MOV A,@Ri Move indirect RAM to ACC. 1 1
MOV A,#data Move immediate data to ACC. 2 1
MOV Rn,A Move ACC to register. 1 1
MOV Rn,direct Move direct byte to register. 2 2
MOV Rn,#data Move immediate data to register. 2 1
MOV direct,A Move ACC to direct byte. 2 1
MOV direct,Rn Move register to direct byte. 2 2
MOV direct,direct Move direct byte to direct byte. 3 2
MOV direct,@Ri Move indirect RAM to direct byte. 2 2
MOV direct,#data Move immediate data to direct byte. 3 2
MOV @Ri,A Move ACC to indirect RAM. 1 1
MOV @Ri,direct Move direct byte to indirect RAM. 2 2
MOV @Ri,#data Move immediate data to indirect RAM. 2 1
MOV DPTR,#data16 Move immediate 16 bit data to data pointer register. 3 2
MOVC A,@A+DPTR Move code byte relative to DPTR to ACC (16 bit address). 1 2
MOVC A,@A+PC Move code byte relative to PC to ACC (16 bit address). 1 2
MOVX A,@Ri Move external RAM to ACC (8 bit address). 1 2
MOVX A,@DPTR Move external RAM to ACC (16 bit address). 1 2
MOVX @Ri,A Move ACC to external RAM (8 bit address). 1 2
MOVX @DPTR,A Move ACC to external RAM (16 bit address). 1 2
PUSH direct Push direct byte onto stack. 2 2
POP direct Pop direct byte from stack. 2 2
XCH A,Rn Exchange register with ACC. 1 1
XCH A,direct Exchange direct byte with ACC. 2 1

XCH A,@Ri Exchange indirect RAM with ACC. 1 1

XCHD A,@Ri Exchange low order nibble of indirect

RAM with low order nibble of ACC 1 1

Boolean Variable Manipulation

Mnemonic Description Size
Cycles

CLR C Clear carry flag. 1 1

CLR bit Clear direct bit. 2 1
SETB C Set carry flag. 1 1
SETB bitSet direct bit 2 1
CPL C Compliment carry flag. 1 1
CPL bit Compliment direct bit. 2 1
ANL C,bit AND direct bit to carry flag. 2 2
ANL C,/bit AND compliment of direct bit to carry. 2 2
ORL C,bit OR direct bit to carry flag. 2 2
ORL C,/bit OR compliment of direct bit to carry. 2 2
MOV C,bit Move direct bit to carry flag. 2 1
MOV bit,C Move carry to direct bit. 2 2
JC rel Jump if carry is set. 2 2
JNC rel Jump if carry is not set. 2 2
JB bit,rel Jump if direct bit is set. 3 2
JNB bit,rel Jump if direct bit is not set. 3 2
JBC bit,rel Jump if direct bit is set & clear bit. 3 2
Program Branching
Mnemonic Description Size
Cycles

ACALL addr11 Absolute subroutine call. 2 2

LCALL addr16 Long subroutine call. 3 2
RET Return from subroutine. 1 2
RETI Return from interrupt. 1 2
AJMP addr11 Absolute jump. 2 2
LJMP addr16 Long jump. 3 2
SJMP rel Short jump (relative address). 2 2
JMP @A+DPTR Jump indirect relative to the DPTR. 1 2
JZ rel Jump relative if ACC is zero. 2 2
JNZ rel Jump relative if ACC is not zero. 2 2
CJNE A,direct,rel Compare direct byte to ACC and jump if not equal. 3 2
CJNE A,#data,rel Compare immediate byte to ACC and jump if not equal. 3 2
CJNE Rn,#data,rel Compare immediate byte to register and jump if not equal. 3 2
CJNE @Ri,#data,rel Compare immediate byte to indirect and jump if not equal. 3 2
DJNZ Rn,rel Decrement register and jump if not zero. 2 2
DJNZ direct,rel Decrement direct byte and jump if not zero. 3 2

Other Instructions

Mnemonic Description Size Cycles

NOP No operation. 1 1
8051 Interrupts
The 8051 architecture can handle interrupts from 5 sources. These are: the two external interrupt
lines, two timers and the serial interface. Each one of these is assigned an interrupt vector address.
This is quite similar to the RST interrupt vectors in the case of 8085.

 External Interrupts
Port P3 of 8051 is a multi‐function port. Different lines of this port carry out functions which are
additional to data input‐output on the port.
Lines P3.2 and P3.3 can be used as interrupt inputs. Interrupts will be caused by a ‘LOW’ level,
or a negative edge on these lines. Half of the special function register TCON is used for setting
the conditions for causing interrupts from external sources. This register is bit addressable.

IT1 and IT0 are the “Interrupt Type” flags for external sources 1 and 0 respectively. These
decide whether a negative going edge or a ‘LOW’ level will cause an interrupt. If the bit is set,
the corresponding interrupt is edge sensitive. If it is cleared, the interrupt is level sensitive. IE1
and IE0 are the status flags for the two external interrupt lines. If the flag is 1, the selected type
of event (edge or level) has occurred on the corresponding interrupt line.

 Internal Interrupts
Internally generated interrupts can be from either timer, or from the serial interface. The serial
interface causes interrupts due to a receive event (RI) or due to a transmit event (TI). The
receive event occurs when the input buffer of the serial line (SBUF in) is full and a byte needs
to be read from it. The transmit event indicates that a byte has been sent a new byte can be
written to output buffer of the serial line (SBUF out).
8051 timers always count up. When their count rolls over from the maximum count to 0000,
they set the corresponding timer flag TF1 or TF0 in TCON. Counters run only while their run
flag (TR1 or TR0) is set by the user program. When the run flag is cleared, the count stops
incrementing. The 8051 can be setup so that an interrupt occurs whenever TF1 or TF0 is set.

 Enabling Interrupts
At power-up, all interrupts are disabled. Suppose Timer 0 is started. When it times out, TF0 in
the special function register TCON will be set. However, this will not cause an interrupt. To
enable interrupts, a number of steps need to be taken.

Interrupts are enabled in a manner which is quite similar to the 8085. There is an interrupt
enable special function register IE at byte address A8H. This register is bit addressable.
The most significant bit of the register is a global interrupt enable flag. This bit must be set in
order to enable any interrupt. Bits 6 and 5 are undefined for 8051. (Bit 5 is used by 8052 for
the third timer available in 8052). Bit 4, when set, enables interrupts from the serial port. Bit 3
should be set to enable interrupts from Timer 1 overflow. Bit 2 is set to enable interrupts from
external interrupt 1 (pin P3.3 on Port 3). Bit 1 enables interrupts from Timer 0 when it
overflows.
Bit 0, when set, will enable interrupts from external interrupt 0 (pin P3.2 on Port 3).

 Interrupt Vectors
When an interrupt occurs, the updated PC is pushed on the stack and is loaded with the vector
address corresponding to the interrupt. The following table gives the vector addresses. The
order of entries in the table is also the order in which the 8051 will poll these in case of multiple
interrupts.

8051 starts executing from address 0000H at power-up or reset. The first 3 bytes are typically
used for placing a long jump instruction to start of the code area. The interrupt vectors start
from 0003 and are separated by 8 bytes from each other. Many simple interrupt handlers can
be accommodated in this space. Otherwise, jump instructions (to handler locations) need to be
placed at the vector addresses. This is quite similar to the RST handlers for 8085.

Thus, to enable interrupts from T0, we have to do

SetB EA ;(or SetB IE.7) to enable interrupts
SetB ET0 ;(or SetB IE.1) to enable interrupts from T0

After this, whenever T0 overflows, TF0 will be set (in SFR TCON), the currently running
program will be interrupted, its PC value will be put on the stack (PC-L first, PC-H after –
because the stack grows upwards in 8051), and PC will be loaded with 000B H. The interrupt
handler for T0 should be placed here, and it should end with the instruction: RETI

 Interrupt Priorities
8051 has two levels of interrupt priorities: high or low. By assigning priorities, we can control
the order in which multiple interrupts will be serviced. Priorities are set by bits in a special
function register called IP, which is at the byte address B8H. This register is also bit
addressable. The assembler defines special names for bits of this register.
Notice that the bits are in the polling order of interrupts. A 1 in a bit position assigns a high
priority to the corresponding source of interrupts – a 0 gives it a low priority. In case of multiple
interrupts, the following rules apply:
 While a low priority interrupt handler is running, if a high priority interrupt arrives,
the handler will be interrupted and the high priority handler will run. When the high
priority handler does ‘RETI’, the low priority handler will resume. When this
handler does ‘RETI’, control is passed back to the main program.
 If a high priority interrupt is running, it cannot be interrupted by any other source –
even if it is a high priority interrupt which is higher in polling order.
 A low-priority interrupt handler will be invoked only if no other interrupt is already
executing. Again, the low priority interrupt cannot preempt another low priority
interrupt, even if the later one is higher in polling order.
 If two interrupts occur at the same time, the interrupt with higher priority will
execute first. If both interrupts are of the same priority, the interrupt which is higher
in polling sequence will be executed first. This is the only context in which the
polling sequence matters.
 Serial Interrupts

 There are independent interrupt flags for reception and transmission of serial data,
called RI and TI.
 RI indicates that a byte has been received and is available for reading in the input
buffer.
 TI indicates that the previous byte has been sent serially and a new byte can be
written to the serial port.
 A serial interrupt occurs if either of these flags is set. (Of course the serial interrupt
must be enabled for this to occur).
 The interrupt service routine should check which of these events caused the
interrupt. This can be done by examining the flags. Either or both of the flag might
be set, requiring a read from or write to the serial buffer SBUF (or both).
 Recall that the input and output buffers are distinct but are located at the same
address. A read from this address reads the input buffer while a write to the same
address writes to the output buffer.
 The RI and TI flags are not automatically cleared when an interrupt is serviced.
Therefore, the interrupt service routine must clear them before returning.

 Sequence of Events after an interrupt

When an enabled interrupt occurs,
1. The PC is saved on the stack, low byte first. Notice that this order is different from
8085. This is because the stack grows upwards in 8051.
2. Other interrupts of lower priority and same priority are disabled.
3. Except for the serial interrupt, the corresponding interrupt flag is cleared.
4. PC is loaded with the vector address corresponding to the interrupt.

When the handler executes ‘RETI”

1. PC is restored by popping the stack.

2. Interrupt status is restored to its original value. (Same and lower priority interrupts
restored to original status).
8051 Timer/Counters

 The 8051 has two timer/counters T0 and T1, which may be configured and used
individually. The 8052 has an additional Timer T2.
 All these counters count up on negative going edges at their inputs.
 These can be used as event counters (where they count the number of negative
transitions on a pin connected to some external source), or as Timers, where they count
up once every twelfth clock cycle.
 A special use of timers is for generating baud rates for the serial port.
 8051 timers always count up. Each counter has a 16 bit count register in the SFR area.
 The low and high bytes can be accessed as separate bytes. When their count rolls over
from the maximum count to 0000, they set the corresponding timer flag (TF1 or TF0)
in TCON.
 The 8051 can be set up so that an interrupt occurs whenever TF1 or TF0 is set. When
8051 branches to the interrupt vector, it automatically clears the TF flag.

 Timer Functions

When used as timers, the 8051 timers count up every 12th clock cycle. This is selected by
clearing the corresponding C/T flags in the TMOD special function register, placed at the
address 89H.
 External Event Counting

Port P3 of 8051 is a multi-function port. Different lines of this port carry out functions which
are additional to data input-output on the port.

Lines P3.5 and P3.4 can be used as inputs to Timers T1 and T0 respectively. If the C/T flag of
a timer is set, the corresponding line is sampled once every machine cycle. The count is
advanced when a negative step is noticed on the line: this involves sampling a high level in one
cycle and a low one on the next. Since each machine cycle takes 12 clock cycles, the fastest
event counting rate is clock frequency/24.
 Special Function Registers
The functioning of these timers is controlled through several special function registers.

The TR0 and TR1 flags in the TCON register (at address 88H) enable a timer to run, when set.
 The C/T flags in the TMOD register (at address 89H) decide whether event counter
operation (flag set) or timer operation (flag cleared) will be used. (TMOD is not bit
addressable).
 The Gate flags in TMOD decide whether counting will be gated by the corresponding
external interrupt pin in P3. If the Gate Flag is cleared, the counter is enabled by the TR
flag alone. If the Gate flag is set, counting also requires the corresponding external interrupt
pin in P3 to be HIGH. This is useful for measuring pulse widths.

Various control registers for timers are placed in the SFR area as shown below:

 Timer modes
The timers may operate in one of four modes:

 Mode 0 :In this mode, the timers act as 13 bit counters. This mode is largely meant for
providing compatibility with an older microcontroller from intel (8048). This mode is
practically never used in fresh designs. Except for the counter size, this mode is
identical to mode 1.
 Mode 1: In this mode, the timers are 16 bits in size. This is a commonly used mode. It
is common to configure the timer to cause an interrupt when it overflows. The interrupt
routine then reloads the timer.
 Mode 2 : This mode provides an 8 bit counter with auto-reload. It uses the high byte of
the count register to store the count value and the low byte as the actual counter. The
counter is automatically re-loaded from TH when it overflows. Thus, there is no
software overhead for re-loading the registers. This is convenient for generating baud
rates etc. The timing resolution is much lower in this mode (only 8 bits). Therefore
crystal frequencies have to be carefully chosen to generate accurate baud rates. Crystals
of 11.059 MHz are often used rather than 12 MHz for this reason.
 Mode 3 : In this mode Timers T0 and T1 behave quite differently. T0 acts as two
independent 8 bit counters. Count register TL0 uses the resources (such as the RUN
 flag, overflow flag) in TCON, TMOD etc. meant for T0. Similarly, TH0 uses the
resources meant for T1. Thus, TR1 will enable running the 8 bit counter made up of
TH0. TF1 will be set whenever TH0 overflows.

8051-SERIAL COMMUNICATION :

Basics of Serial communication

Data transfer between two electronic devices (Ex Between a computer and microcontroller or
a peripheral device) is generally done in two ways

(i).Serial data Transfer and

(ii).Parallel data Transfer

Serial communication uses only one or two data lines to transfer data and is generally used for
long distance communication. In serial communication the data is sent as one bit at a time in
a timed sequence on a single wire. Serial Communication takes place in two methods,
Asynchronous data Transfer and Synchronous data Transfer.

Serial Data Transfer

Asynchronous data transfer allows data to be transmitted without the sender having to send
a clock signal to the receiver. Instead, special bits will be added to each word in order to
synchronize the sending and receiving of the data. When a word is given to the UART for
Asynchronous transmissions, a bit called the "Start Bit" is added to the beginning of each word
that is to be transmitted. The Start Bit is used to alert the receiver that a word of data is about
to be sent, and to force the clock in the receiver into synchronization with the clock in the
transmitter.
 Serial data transmission

After the Start Bit, the individual bits of the word of data are sent .Here each bit in the word is
transmitted for exactly the same amount of time as all of the other bits. When the entire data
word has been sent, the transmitter may add a Parity Bit that the transmitter generates. The
Parity bit may be used by the receiver to perform simple error checking. Then at least one Stop
Bit is sent by the transmitter. If the Stop Bit does not appear when it is supposed to, the UART
considers the entire word to be corrupted and will report a Framing Error.

Baud rate is a measurement of transmission speed in asynchronous communication , it

represents the number of bits/sec that are actually being sent over the serial link. The Baud
count includes the overhead bits Start, Stop and Parity that are generated by the sending UART
and removed by the receiving UART.

In the Synchronous data transfer method the receiver knows when to “read” the next bit
coming from the sender. This is achieved by sharing a clock between sender and receiver. In
most forms of serial Synchronous communication, if there is no data available at a given time
to transmit, a fill character will be sent instead so that data is always being transmitted.
Synchronous communication is usually more efficient because only data bits are transmitted
between sender and receiver, however it will be more costly because extra wiring and control
circuits are required to share a clock signal between the sender and receiver.

Devices that use serial cables for their communication are split into two categories.

1. DTE (Data Terminal Equipment). Examples of DTE are computers, printers & terminals.
2. DCE (Data Communication Equipment). Example of DCE is modems.

Parallel Data Transfer :

Parallel communication uses multiple wires (bus) running parallel to each other, and can
transmit data on all the wires simultaneously. i.e all the bits of the byte are transmitted at a
time. So, speed of the parallel data transfer is extremely high compared to serial data transfer.
An 8-bit parallel data transfer is 8-times faster than serial data transfer. Hence with in the
computer all data transfer is mainly based on Parallel data transfer. But only limitation is due
to the high cost ,this method is limited to only short distance communications.

Differences between Serial data transfer and Parallel data transfer

S.No Serial Communication Parallel Communication

1 Data is transmitted bit after the bit in a Data is transmitted simultaneously

single line through group of lines(Bus)

2 Data congestion takes place No, Data congestion

3 Low speed transmission High speed transmission

4 Implementation of serial links is not an Parallel data links are easily

easy task. implemented in hardware

5. In terms of transmission channel costs It is more expensive

such as data bus cable length, data bus
buffers, interface connectors, it is less
expensive

6 No , crosstalk problem Crosstalk creates interference between

the parallel lines.

7 No effect of inter symbol interference Parallel ports suffer extremely from

and noise inter-symbol interference (ISI) and
noise, and therefore the data can be
corrupted over long distances.

8 The bandwidth of serial wires is much The bandwidth of parallel wires is

higher. much lower.

9 Serial interface is more flexible to Parallel data transfer mechanism rely

upgrade , without changing the on hardware resources and hence not
hardware flexible to upgrade.

10 Serial communication work effectively Parallel buses are hard to run at high
even at high frequencies. frequencies.

SERIAL COMMUNICATION IN 8051 MICROCONTROLLER

The 8051 has two pins for transferring and receiving data by serial communication. These two
pins are part of the Port3(P3.0 &P3.1) .These pins are TTL compatible and hence they require
a line driver to make them RS232 compatible .Max232 chip is one such line driver in use.
Serial communication is controlled by an 8-bit register called SCON register,it is a bit
addressable register.

SCON (Serial control) register :

SM0 SCON.7 Serial port mode selector

SM1 SCON.6 Serial port mode selector

SM2 SCON.5 Used for multiprocessor mode communication

(not applicable for 8051)

REN SCON.4 Receive enable. Set or cleared by making this

bit either 1 or 0 foe enable /disable reception.

TB8 SCON.3 9th data bit transmitted in modes 2 and 3

RB8 SCON.2 9th data bit received in modes 2 and 3.it is not
used in mode 0 & mode 1.If SM2 = 0 RB8 is
the stop bit .

TI SCON.1 Transmit interrupt flag

RI SCON.0 Receive interrupt flag.

 M0 , SM1 : These two bits of SCON register determine the framing of data by
specifying the number of bits per character and start bit and stop bits. There are 4 serial
modes.

SM0 SM1

0 0 : Serial Mode 0

0 1 : Serial Mode 1, 8 bit data, 1 stop bit, 1 start bit

1 0 : Serial Mode 2

1 1 : Serial Mode 3
 REN (Receive Enable) also referred as SCON.4. When it is high,it allows the 8051 to
receive data on the RxD pin. So to receive and transfer data REN must be set to 1.When
REN=0,the receiver is disabled. This is achieved as below

SETB SCON.4

& CLR SCON.4

 TI (Transmit interrupt) is the D1 bit of SCON register. When 8051 finishes the transfer
of 8-bit character, it raises the TI flag to indicate that it is ready to transfer another byte.
The TI bit is raised at the beginning of the stop bit.

 RI (Receive interrupt) is the D0 bit of the SCON register. When the 8051 receives data
serially ,via RxD, it gets rid of the start and stop bits and places the byte in the SBUF
register. Then it raises the RI flag bit to indicate that a byte has been received and should
be picked up before it is lost. RI is raised halfway through the stop bit.