8086 Microprocessor LEC - 1: Topic: Why 8086 Was Required? Various Features of 8086 Microprocessor

8086
MICROPROCESSOR
LEC -1
TOPIC:
Why 8086 was required?
Various features of 8086 Microprocessor

Why 8086 was required?
 The 8085 is an 8-bit microprocessor which was mainly used in small
industrial applications to control few operations.
 It was having no. of limitations which made it unsuitable for large or
general purpose systems.
 The 8085 does not support multiplication and division instructions as
well as there is no support for string processing directly.
 As an 8-bit processor, it can not process also large quantities with
adequate speed.
 The 16-bit operations become more time consuming and require special
processing steps.
 So Intel’s first 16-bit processor 8086 was developed to overcome all
these limitations.
 It was introduced in 1978.
Various features of 8086 Microprocessor
 In this processor Intel introduced some new concepts with 8086 which
are mainly pipelining & memory segmentation.
 The introduction of pipeline made 8086 to perform operations at higher
speed which reduces overall processing time considerably.
 The memory segmentation makes programs more manageable.
 The 8086 also introduced multiplication and division instructions as well
as special instructions for string processing.
 The 8086 consists of 20 address bit address bus having memory
maximum memory size of 1 Mb.
 The Address range for 1 Mb memory will be 00000 h to FFFFF h.
 It has 16 bit data bus so it can process 16 bit data at a time.
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8086
MICROPROCESSOR
LEC -2
TOPIC:
8086 Architecture
Logical Block Diagram of 8086
BIU(BUS INTERFACE UNIT)
EU(EXECUTION UNIT)
8086 Block Diagram
 The 8086 hardware is internally divided into two functional parts:
 They are
 1. Bus Interface unit (BIU) 2. Execution Unit (EU)
BIU (Bus Interface Unit)
 The BIU Contains following functional units
 Prefetch Queue
 Segment registers
 Instruction pointer
 The BIU is responsible for interfacing 8086 with the external

devices.
 It sends addresses on address bus, fetches instructions from
memory, performs read and write operations with memory
and I/O devices.
 BIU also computes address before it sends address on
Execution Unit
 The major components of EU are:
 Control circuit
 Instruction decoder
 ALU
 General purpose registers
 Stack pointers
 Index registers
 Flag register
Execution Unit
 The execution unit executes an instruction while BIU
is fetching another instruction or data from memory
which makes two units works parallelly to improve
performance.
 Once execution unit completes execution of current
instruction, it reads next instruction from prefetch
queue.
 The EU also tells BIU whenever it needs some data
to be read from memory or written into memory as
part of execution of current instruction.
 The main functions of EU are telling BIU from
where to fetch information. Decoding instructions
Execution Unit
 The control circuit controls all the operations
performed by the processor.
 The instruction decoder decodes the instructions and
divide an instruction into small steps required to
execute it.
 The 16-bit ALU performs all the arithmetic and
logical operations.
 The registers provide memory space for Operands.

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8086
MICROPROCESSOR
LEC -3
TOPIC:
Prefetch queue
What is Prefetch Queue?
 Prefetch queue: It is 6-byte First-In-First-Out
(FIFO) queue which can store upto 6 instruction
bytes.
 The BIU fetches instruction bytes from memory
ahead of time and stores it in prefetch queue.
 Whenever execution unit completes execution of
previous instruction, it receives next instruction
from queue and starts executing it.
Working of Prefetch Queue
Memory
0000 h 34 h
45 h
.
.
. Prefetch queue
Execution Unit
On going program
. 10 h
(44 h)
44 h B1 h
F3FF h 23 h
10 h
B1 h 40 h
23 h 22 h
33 h
40 h
22 h
FFFF h
Advantage of Prefetch Queue
 Asnext instruction is readily available in queue, EU

need not wait for fetching the instruction. This saves
considerable time and speeds up execution.
 Theconcept of fetching instructions ahead of time
and storing it in queue which is used by EU
whenever it is free, is known as pipelining.
Prefetch Queue & Branching Instructions
 The BIU fetches instructions in sequence which

causes problem when JMP or CALL instruction
comes.
 In case of JMP or CALL, the execution will not
continue in sequence, but the control will be
transferred to target of JMP or CALL and execution
should continue from new location.
 To avoid this problem, whenever execution unit
executes JMP or CALL Instruction. Prefetch queue
is made empty and it is filled up again from new
location.
Working of Prefetch Queue during JMp
& CALL
Memory
0000 h 34 h
45 h
22 h
15 h
. Prefetch
queue1 Execution Unit
On going program
. 10 h
34 44 h
34
44 h B1
F3FF h 45 hh
10 h 23 hh
22
B1 h 40 hh
15
23 h 22 h
.. h
JMP 0000 h 40 h 33 h
.. h
22 h
FFFF h
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8086
MICROPROCESSOR
LEC -4
TOPIC:
Pipelining
8085 Instruction Execution
 In 8085 to run any instruction a fetch-decode-execute
cycle needs to be completed
 But this cycle used to be performed only one at a
time for instructions due to which overall
performance of processor was slow.
T1 T2 T3 T4 T5 T6 T7 T8 T9
Fetch Decode Execute Fetch Decode Execute Fetch Decode Execute
 Itwas overcome in 8086 processor by using

pipelining.
8086 Pipelining
 In 8086 three unit, fetch , decode and execute can work
simultaneously and hence increases the overall performance
of processor.
T1 T2 T3 T4 T5 T6
Fetch Decode Execute
 The concept of fetching instructions ahead of time and

executing them whenever EU is free is called as pipelining
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8086
MICROPROCESSOR
LEC -5
TOPIC:
8086 REGISTER ORGANIZATION
GENERAL PURPOSE REGISTERS OF 8086
STACK POINTERS
INDEX REGISTERS
8086 REGISTER ORGANIZATION
divided in two groups
 All the registers of 8086 can be broadly
depending on which unit they belong
 The 8086 consists of following registers:
EU registers:
 Four General purpose registers
 Two Stack pointer registers
 Two Index registers
 Flag register
BIU registers
 Four segment registers
 IP register
General Purpose Registers of 8086
 The 8086 has four 16-bit general purpose registers namely
AX, BX, CX and DX.
 Each of them can be also used as two 8-bit registers.
 Eg: AX can be used as AH and AL, BX can be used as BH
and BL,CX be used as CH and CL and DX can be used as
DH and DL.
AH AX AL
BH BX BL
CH CX CL
DH DX DL
General Purpose Registers
 AH is higher byte of AX register while AL is lower byte of AX
register. Same is for BX. CX and DX.
 The AX Register is known as accumulator of 8086 and used
as default register in some instructions like multiplication and
division.
 The BX register is called base register as it is frequently used
as Pointer to memory location.
 The CX register is used as counter in looping and repeat
instructions and hence sometimes also known as counter
register.
 The DX register is referred as data register as it is used as I/O
address pointer in IN and OUT Instructions.
Stack Pointers
 A 16-bit register SP (stack pointer) is used to
store Offset address of top of stack where last
value is stored.
 The 8086 has another stack pointer known as
BP (Base pointer).
 It is also used with stack segment and very
useful in parameter passing and accessing
during subroutine execution.
Index Registers
 The 8086 has two more 16-bit registers known as
index registers.
 They are SI (Source Index) and DI (Destination
Index).
 They can used only as 16-bit registers.
 They can be used as general purpose registers or as
Index registers to keep track of index values in
arrays.
 The Sl and DI registers are used inherently in string
instructions to point to source & destination strings
respectively.
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8086
MICROPROCESSOR
LEC -6
TOPIC:
FLAG REGISTER OF 8086
Flag Registers
 It is a 16-bit register and contains 9 flags.
 They are divided into two categories as flags
 Control flags:
 Trap Flag (TF)
 Interrupt Flag (IF)
 Direction Flag (DF)
 Conditional flags:
 Carry Flag (CF)
 Parity Flag (PF)
 Auxiliary Carry Flag (AF)
 Zero Flag (ZF),
 Sign Flag ( SF),
 Over flow Flag (OF)
Conditional flags
ZERO FLAG PARITY FLAG
1=Result Zero 1=Even Parity
0=Result Non-zero 0=Odd Parity
- - - - OF DI IF TF S Z - AC - PF - CF
OVER FLOW FLAG SIGN FLAG CARRY FLAG

AUXILIARY CARRY FLAG
1=OVER FLOW 1=NEGATIVE 1=CARRY
1=BCD Overflow
0=NO OVER FLOW 0=POSITVE 0=No BCD Overflow 0=No CARRY
 The conditional flags are set or reset according to execution of

arithmetic and logical instructions.
 They are used as condition in branch instructions and are very useful
for flow control.
 The conditional flags here has same meaning as 8085 microprocessor.
 The only difference is they can be used for both 8-bit and 16-bit
Control flags
- - - - OF DI IF TF S Z - AC - PF - CF
 The control flags are used to control behaviour of processor itself.

 They can be set or reset by special instructions.
 The TF (Trap flag) is useful for single stepping of program during Debugging and
used by debugging tools.
 The IF (Interrupt Flag)is used to enable or disable maskable interrupts.
 If IF is 0, 8086 ignores maskable interrupts
 The CLI (Clear Interrupt) and STI (Set Interrupt) instructions are used to clear
or set IF flag respectively.
 The DF (Direction flag) is useful in string operations.
 lf DF=0, then index registers are incremented, and if DF=1, they are decremented.
 The CLD and STD insructions are used to clear and set direction flag respectively.
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8086
MICROPROCESSOR
LEC -7
TOPIC:
8086 MEMORY SEGMENTATION

 The 8086 divides program into three different components code,

data and stack.
 Each component is stored in separate segment which makes
changes in one segment independent of others.
 Because of segmented organization of a program, it can be
managed easily and changes can be accommodated easily.
 The code segment is used to store instructions of a program.
 The data segment stores data part of program.
 The stack segment provides necessary stack space to store values
temporarily during execution of program.
 The extra segment is another data segment and used when data is
large.
Segmentation in 8086
Memory
00000 h
 It is not necessary that segment is
64 kb Code segment
always of 64 KB. If segment is
smaller than 64 KB, it can be
304FF h overlapped with another segment.
40F00 h  The first segment can start from

64 kb physical address 00000h, second can
data segment
Start from 00010h, third can start
from 00020h and so on.
50020 h
64 kb  The minimum distance between two
stack segment starts is 16-byte which is called
paragraph boundary.
a2320 h
 Hence, minimum size of segment is
64 kb 16 Byte and maximum size is 64 KB.
extra segment
fffff h
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you
8086
MICROPROCESSOR
LEC -8
TOPIC:
ADDRESS GENERATION IN 8086
Address Generation in 8086
 The physical address in 8086 is of 20-bit, but 8086
does not contain any 20-bit register.
 To store 20-bit address into 16-bit registers, 8086
divides 20- bIt physical address into two parts called
segment base and offset and is referred as Seg :
offset.
 For example, 20-bit address 20502 h can be
represented as 2050:0002 h where 2050h is segment
base and 0002 h is offset or displacement.
 The 16-bit segment base is stored in one of the
segment register while offset is either stored in
register or directly in instruction.
How Address is generated in 8086?
The 8086 always put 20 bit address on its physical address us , but
before that BIU computes the address using segment and offset.
Eg: lets say physical address of memory location is 20502 and it is
stored as 2050:0002 in 8086.
To get back the original physical address the following steps are done
:
1) Segment is shifted 4 times left or multiplied with 16
2) Then offset is added to the new segment address.
20500 -(segment x 16)
+0002 (OFFSET)
20502 (20-BIT Physical Address)
Instruction Pointer
 The IP is a 16-bit register and stores offset address of next
instruction to be executed.
 The program (instructions) is always stored in code segment.
 Thus. IP is always used as offset with CS and complete
address of instruction is refferred as CS:IP.
 The IP is incremented every time by length of instruction to
point next instruction in code segment.
 Instruction is computed as Address of instruction = CS x 16 +
IP
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you
8086
MICROPROCESSOR
LEC -9
TOPIC:
PIN DIAGRAM OF 8086
MINIMUM MODE
Pin Diagram of 8086
 The 8086 microprocessor contains the 40 pins
 The 8086 supports two hardware operating modes:
 Minimum mode
 Maximum mode

 The operating mode of the 8086 is decided by the pin number
33 called MN/MX.
 The functions of pins 24 to 31 are different in minimum and
maximum modes, The rests of the pins work in same way in
both the modes.
Pin Diagram of 8086(Minimum Mode)
GND 1 40 VCC
AD14 2 39 AD15
Vcc and GND pins are used to
AD13 3 38
connect the power source to
AD12 4 37
the microprocessor.
AD11 5 36
AD10 6 35
AD9 7 34
AD8 8 33 MN/MX’ MN/MX : This pin decides the
CLK: It is called clock input. It is
AD7 9 32 operating mode of the 8086
connected to the external INTEL
AD6 10 31 processor. If it is at Logic 1,
circuit providing clock input to 8086
AD5 11 MICROPROCESSOR 30 then the 8086 operates in
the 8086 microprocessor.
AD4 12 29 minimum mode and if it is at
AD15-AD0 : This is called AD3 13 28 Logic 0, then 8086 operates in
multiplexed address/data bus. AD2 14 27 maximum mode.
AD1 15 26
When ALE = 1, it is used as
AD0 16 25
address bus (lower 16 bits) and
17 24
when ALE = 0, it is used as 16-bit
18 23
data bus. CLK 19 22
GND 20 21
S6, S5, S4, S3: These are
GND 1 40 VCC status lines and multiplexed
AD14 2 39 AD15 with upper 4 address bits
AD13 3 38 AD16/ S3 A19-A16. They are effective
AD12 4 37 AD17/ S4 when ALE = 0.
AD11 5 36 AD18/ S5 These pins are used to
AD10 6 35 AD19/S6 A19-A16 : These
indicate the four pins
processor
AD9 7 34 represents
status as: S6 theis upper
always40,bits
S5 of
AD8 8 33 MN/MX’ 20-bit address
gives status of when ALE=1.
interrupt flag
AD7 9 32 They are multiplexed
and S4,S3 together giveswith
INTEL
AD6 10 31 status linesofS6-
the status S3 and called
which
8086
AD5 11 MICROPROCESSOR 30 A19/S6-A16/S3
segment register is
AD4 12 29 currently used to generate
AD3 13 28 the address.
AD2 14
ALE : It is called Address Latch
27
AD1 15
Enable (ALE). When this pin is
26
AD0 16
high, the multiplexed
25 ALE
17
address/data bus work as
24
18
address bus and when it is low
23
CLK 19 22
address/bus work as data bus
GND 20 21 and status bus respectively.
GND 1 40 VCC BHE/S7: The BHE (Bus High
AD14 2 39 AD15 Enable) pin acts as enable
AD13 3 38 AD16/ S3 signal for the odd memory
AD12 4 37 AD17/ S4 bank in 8086 system. It is also
AD11 5 36 AD18/ S5 multiplexed with the status
AD10 6 35 AD19/S6 signal S7.
AD9 7 34 BHE/S7
AD8 8 33 MN/MX’ RD/WR: These are known as
AD7 9 32 RD’ Read and Write control signals.
INTEL When RD= 0, the processor is
AD6 10 31
8086
AD5 11 MICROPROCESSOR 30 reading from memory or IO
AD4 12 29 WR’ device. When WR=0, the
AD3 13 28 M/IO’ processor is writing to memory
AD2 14 27 or IO device.
AD1 15 26
AD0 16
M/IO: It is called memory/IO
25 ALE
17
pin. When it is 1, processor
24
18
deals with memory and when
23
CLK 19
it is 0, processor deals with
22
GND 20 21
Input/Output devices.
GND 1 40 VCC
AD14 2 39 AD15
AD13 3 38 AD16/ S3
NMI, INTR : These are AD12 4 37 AD17/ S4 HOLD, HLDA: These pins are
interrupt pins. The NMI and AD11 5 36 AD18/ S5 used to interface 8086 with
INTR are used by external AD10 6 35 AD19/S6 DMA (Direct Memory Access)
devices to send the interrupt AD9 7 34 BHE/S7 controller.
request. AD8 8 33 MN/MX’ The HOLD is an request from
The INTA indicates interrupt AD7 9 32 RD’ DMA controller for getting
acknowledgement. INTEL
AD6 10
8086
31 control
HOLD DT/R: It of buses Data
is called & HLDA (Hold
The NMI is non-maskable AD5 11 Acknowledgement) is used
MICROPROCESSOR 30 HLDA Transmit/Receive. When it isto1,
interrupt and can not be AD4 12 29 WR’ indicate the requestdata
is granted
processor transmits and
disabled, while INTR is AD3 13 28 by processor.
M/IO’ when it is 0, processor receives
maskable and can be disabled. AD2 14 27 DT/R’ data.
AD1 15 26 DEN’
AD0 16
DEN: It is called data enable
25 ALE
NMI 17
pin and goes low during read
24 INTA’
INTR 18
operation to enable the
23
CLK 19
memory.
22
GND 20 21
GND 1 40 VCC
AD14 2 39 AD15
AD13 3 38 AD16/ S3
AD12 4 37 AD17/ S4
AD11 5 36 AD18/ S5
AD10 6 35 AD19/S6
AD9 7 34 BHE/S7
AD8 8 33 MN/MX’
AD7 9 32 RD’
INTEL TEST: It is used during the
AD6 10 31 HOLD
8086
AD5 11 MICROPROCESSOR 30 HLDA execution of WAIT instruction
AD4 12 29 WR’ to synchronize with external
AD3 13 28 M/IO’ hardware.
RESET: When processor
AD2 14 27 DT/R’ receives 0 on this pin, it resets
AD1 15 26 DEN’ itself.
READY: This is input signal and
AD0 16 25 ALE used to synchronize the
NMI 17 24 INTA’
processor with slow devices
INTR 18 23 TEST’
during external operations
CLK 19 22 READY
GND 20 21 RESE
Thank
you
8086
MICROPROCESSOR
LEC -10
TOPIC:
PIN DIAGRAM OF 8086
MAXIMUM MODE
Pin Diagram of 8086(Maximum Mode)
 The 8086 microprocessor contains the 40 pins.
 The operating mode of the 8086 is decided by the pin
number 33 called MN/MX.
 When this pin MN/MX is 0 the 8086 works in
maximum mode.
 The functions of pins 24 to 31 are different in
minimum and maximum modes, The rests of the pins
work in same way in both the modes.
GND 1 40 VCC
AD14 2 39 AD15
AD13 3 38 AD16/ S3
AD12 4 37 AD17/ S4
AD11 5 36 AD18/ S5
AD10 6 35 AD19/S6
AD9 7 34 BHE/S7
AD8 8 33 MN/MX’
AD7 9 32 RD’
INTEL
AD6 10 31 HOLD
8086
AD5 11 MICROPROCESSOR 30 HLDA
AD4 12 29 WR’
AD3 13 28 M/IO’
AD2 14 27 DT/R’
AD1 15 26 DEN’
AD0 16 25 ALE
NMI 17 24 INTA’
INTR 18 23 TEST’
CLK 19 22 READY
GND 20 21 RESE
GND 1 40 VCC
AD14 2 39 AD15
AD13 3 38 AD16/ S3
AD12 4 37 AD17/ S4
AD11 5 36 AD18/ S5
AD10 6 35 AD19/S6
RQ/GT1. RQ/GT0: The
AD9 7 34 BHE/S7
functions of HOLD and HLDA
AD8 8 33 MN/MX’ pins are replaced by RQ/GT
AD7 9 32 RD’ (Request//Grant) pins.
INTEL They are used by another
AD6 10 31 RQ’/GT0’
8086
AD5 11 MICROPROCESSOR 30 RQ’/GT1’
processor in system to gain the
AD4 12 29 LOCK’
control of system.
AD3 13 28 LOCK: This signal is used to
AD2 14 27 prevent another processor in
AD1 15 26 system to gain the control of
AD0 16 25 system.
NMI 17 24
INTR 18 23 TEST’
CLK 19 22 READY
GND 20 21 RESE
GND 1 40 VCC
AD14 2 39 AD15
AD13 3 38 AD16/ S3
AD12 4 37 AD17/ S4
AD11 5 36 AD18/ S5
AD10 6 35 AD19/S6
AD9 7 34 BHE/S7
AD8 8 33 MN/MX’
AD7 9 32 RD’ S2, S1, S0: These are status
INTEL signals connected as input to
AD6 10 31 RQ’/GT0’
8086
AD5 11 MICROPROCESSOR 30 RQ’/GT1’ external bus controller 8288 as
AD4 12 29 LOCK’ 8086 does not generate status
AD3 13 28 S2’ signals directly in maximum
AD2 14
QS1,
mode.QS0: These queue status
27 S1’
AD1 15
signals are used
The control to provide
signals are the
26 S0’
AD0 16
status of internal
provided queue in
by the 8288
25 QS0
NMI 17
maximum mode.
controller in maximum mode.
24 QS1
INTR 18

23 TEST’
CLK 19 22 READY
GND 20 21 RESE
Thank
you

8086 Microprocessor LEC - 1: Topic: Why 8086 Was Required? Various Features of 8086 Microprocessor

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8086

Various features of 8086 Microprocessor

Logical Block Diagram of 8086

BIU(BUS INTERFACE UNIT)

 The BIU is responsible for interfacing 8086 with the external

 Asnext instruction is readily available in queue, EU

 The BIU fetches instructions in sequence which

 Itwas overcome in 8086 processor by using

Fetch Decode Execute

Fetch Decode Execute

Fetch Decode Execute

 The concept of fetching instructions ahead of time and

OVER FLOW FLAG SIGN FLAG CARRY FLAG

 The conditional flags are set or reset according to execution of

 The control flags are used to control behaviour of processor itself.

 The 8086 divides program into three different components code,

40F00 h  The first segment can start from

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