Department of Electronics & Communication Engineering

LECTURE NOTES

ON

MICROPROCESSOR AND MICROCONTROLLER

Unit 1
8086 Architecture Instruction Set and Assembly Language Programming of 8086

III B. Tech II semester (JNTUH-R16)

R RAJA KISHORE, Asst. Professor

Faculty Name HOD Director Principal

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 UNIT: 1

INTEL MICROPROCESSORS 8086

1.0 Introduction to Microprocessor

A microprocessor is an electronic device which computes on the given input similar to

CPU of a computer. It is made by fabricating millions(or billions) of transistors on a single chip.

History of Microprocessor

Microprocessor journey started with a 4-bit processor called 4004, it was made by Intel corporation in
1971. It was 1st single chip processor. Then the idea was extended to 8-bit processors like 8008, 8080 and
then 8085 (all are Intel products). 8085 was a very successful one among the 8-bit processors, however its
application is very limited because of its slower computing speed and other quality factors.

Some years later Intel came up with its 1st 16-bit processors 8086.

Intel 8086:
The 8086 is a 16-bit microprocessor chip designed by Intel corporation in between early 1976 and mid-1978.
The release of Intel's 8086 microprocessor in 1978 was a watershed moment for personal computing.

Elements of the 8086 Microprocessor Architecture

The 80x86 has:

• 16-bit internal data bus
• 20-bit address bus: 220 = 1,048,576 = 1 megabyte
• Control bus
• Execution Unit
• Bus Interface Unit

Among the on-chip peripherals are:

• 2 direct memory access controllers (DMA)
• Three 16-bit programmable timers
• Clock generator
• Chip select unit
• Programmable Control Registers

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 Differences between 8086 and 8088 Microprocessors :

Though the architecture and instruction set of both 8086 and 8088 processors are same, still we find certain
differences between them They are
(i) 8086 has 16-bit data bus lines whereas 8088 has 8-data lines.
(ii) 8086 is available in three clock speds namely 5 M.Hz,8M.Hz(8086-2) and 10 M.Hz
(8086-1) whereas 8088 is available is only available only in two speeds namely
5M.Hz and 8M.Hz
(iii) The memory address space of 8086 is organized as two 512kB banks whereas 8088
memory space is implemented as a single 1MX 8 memory bank.
(iv) 8086 has a 6-byte instruction queue whereas 8088 has a 4 byte instruction queue .
The reason for this is that 8088 can fetch only one byte at a time.
(v) In 8086 the memory control pin ( M/ IO) signal is complement of the 8088
equivalent signal(IO/M)
(vi) The 8086 has BHE(Bank high enable whereas 8088 has SSO status signal .
(vii).The byte and word data operations of 8086 are different from 8088.
(viii) 8086 can read or write either 8-bit or 16-bit word at a time ,whereas 8088 can read
only 8-bit data at a time.
(ix) The I/O voltage levels for 8086 are , Vol is measured at 2.5mA and for 8088 it is
measured at 2.0mA.
(x) 8086 draws a maximum supply current of 360 mA and the 8088 draws a maximum
of 340 mA.

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1.1 The 8086 Architecture Processor Model

The simplified block diagram of the 80x 86 processor models is organized

as two separate processors :

1) Bus Interface Unit (BIU)

2) Execution Unit (EU).

Bus Interface Unit (BIU)

The BIU provides hardware functions. Including generation of the memory and I/0 addresses for the transfer
of data between itself and the outside world.
Following functions are supported by BIU.
 It provides a full 16 bit bidirectional data bus and 20 bit address bus.
 It sends address of memory or I/O.
 It fetches instruction from memory.
 It reads data from port/memory.
 It writes data into port/memory.
 It supports instruction queuing .
 It makes 8086’s interface to the outside world.
 The BIU uses a mechanism known as an instruction stream queue to implement a pipeline
architecture.
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  If the BIU is already in the process of fetching an instruction when the EU request it to read or write
operands from memory or I/O, the BIU first completes the instruction fetch bus cycle before initiating
the operand read / write cycle.

 The BIU also contains a dedicated adder which is used to generate the 20bit physical address.

Execution Unit (EU)

The EU receives program instruction codes and data from the BIU, executes these instructions, and stores the
results in the general registers.
Following functions are supported by BIU.
 The Execution unit is responsible for decoding and executing all instructions.
 The EU extracts instructions from the top of the queue in the BIU.
 During the execution of the instruction, the EU tests the status and control flags and updates them
based on the results of executing the instruction.
 If the queue is empty, the EU waits for the next instruction byte to be fetched and shifted to top of the
queue.
 The EU accesses the queue from the output end. It reads one instruction byte after the other from the
output of the queue.
 It tells BIU from where to fetch instructions or data, decodes instructions & execute instructions.

The main linkage between the two functional blocks is the instruction
queue, with the BIU looking ahead of the current instruction being executed in order to keep the queue filled
with instructions for the EU to decode and operate on.

Instruction Queue
• It is of 6 Bytes.

• To increase the execution speed, BIU fetches as many as six instruction bytes ahead to time
from memory.

• It operates on the principle first in first out (FIFO).

• Then all bytes are given to EU one by one.

• This pre-fetching operation of BIU may be in parallel with execution operation of EU.

It improves the execution speed of the instruction.

The Fetch and Execute Cycle
The organization of the processor into a separate BIU and EU allows the fetch and execute cycles to
overlap. To see this, consider what happens when the 8086 is first started. Figure 3.2.
1. The BIU outputs the contents of the instruction pointer register (IP) onto the address bus,
causing the selected byte or word in memory to be read into the BIU.
2. Register IP is incremented by one to prepare for the next instruction fetch.

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3. Once inside the BIU, the instruction is passed to the queue: a first-in/first-out storage register
sometimes likened to a pipeline.
4. Assuming that the queue is initially empty, the EU immediately draws this instruction from the
queue and begins execution.
5. While the EU is executing this instruction, the BIU proceeds to fetch a new instruction.
Depending on the execution time of the first instruction, the BIU may fill the queue with several
new instructions before the EU is ready to draw its next instruction.
6. The cycle continues, with the BIU filling the queue with instructions and the EU fetching and
executing these instructions. The BIU is programmed to fetch a new instruction whenever the
queue has room for two additional bytes. The advantage to this pipelined architecture is that the
EU can execute instructions (almost) continually instead of having to wait for the BIU to fetch a
new instruction. This is shown schematically in the following Figure

The “Wait” mode

There are three conditions that will cause the EU to enter a "wait" mode.
I. When an instruction requires access to a memory location. The BIU must suspend fetching
instructions and output the address of this memory location. After waiting for the memory
access, the EU can resume executing instruction codes from the queue, and the BIU can
resume filling the queue.
II. When the instruction to be executed is a jump instruction. In this case, control is to be
transferred to a new address. The EU must wait while the instruction at the jump address is
fetched. Any bytes presently in the queue must be discarded (they are overwritten).
III. During the execution of slow-executing instructions.

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1.2 REGISTER ORGANISATION, Programming model
The programming model for a microprocessor shows the various internal registers that are accessible
to the programmer. The Following Figure is a model for the 8086. In general, each register has a special
function.

Registers of 8086
• General Purpose Registers
• Pointer and Index Registers
• Segment Registers
• Instruction Pointer
• Status Flags

General Purpose Registers

There are four 16-bit general purpose registers:
 AX
 BX
 CX
 DX

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Each of these 16-bit registers are further subdivided into two 8-bit registers.

AX AH AL
BX BH BL
CX CH CL

DX BH DL

1. AX Register: AX register is also known as accumulator register that stores operands for arithmetic
operation like divided, rotate.

2.BX Register: This register is mainly used as a base register. It holds the starting base location of a memory
region within a data segment.

3.CX Register: It is defined as a counter. It is primarily used in loop instruction to store loop counter.

4.DX Register: DX register is used to contain I/O port address for I/O instruction.

Pointers and Index Registers

Following four registers are under this category:
1. Stack Pointer (SP),
2. Base Pointer (BP),
3. Source Index (SI),
4. Destination Index (DI).

Following Registers can also be used as a general Purpose Registers.

1. Stack Pointer (SP) is a 16-bit register pointing to program Stack, also contains 16-Bit offset address.
2. Base Pointer (BP) is a 16-bit register pointing to data in stack segment. BP register is usually used for
based indexed or register indirect addressing.
3. Source Index (SI) is a 16-bit register. SI is used for indexed, based indexed and register indirect
addressing, as well as a source data address in string manipulation Instructions
4. Destination Index (DI) is a 16-bit register. DI is used for indexed, based indexed and register indirect
addressing, as well as a destination data address in string manipulation instructions.

Segment Register
There are four segment registers in Intel 8086:
1. Code Segment Register (CS),
2. Data Segment Register (DS),
3. Stack Segment Register (SS),
4. Extra Segment Register (ES).
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A segment register points to the starting address of a memory segment.
For Example: The code segment register points to the starting address of the code segment.
The data segment register points to the starting address of the data segment, and so on.
The maximum capacity of a segment may be up to 64 KB.

Code segment (CS):-

It is a 16-bit register containing address of 64 KB segment with processor instructions. The processor uses
CS segment for all accesses to instructions referenced by instruction pointer (IP) register. CS register cannot
be changed directly. The CS register is automatically updated during far jump, far call and far return
instructions .
Stack segment (SS):-
It is a 16-bit register containing address of 64KB segment with program stack. By default, the processor
assumes that all data referenced by the stack pointer (SP) and base pointer (BP) registers is located in the
stack segment. SS register can be changed directly using POP instruction.
Data segment (DS):-
It is a 16-bit register containing address of 64KB segment with program data. By default, the processor
assumes that all data referenced by general registers (AX, BX, CX, DX) and index register (SI, DI) is located
in the data segment.

Extra segment (ES):-

It is a 16-bit register containing address of 64KB segment, usually with program data. By default, the
processor assumes that the DI register references the ES segment in string manipulation instructions. It is
possible to change default segments used by general and index registers by prefixing instructions with a CS,
SS,DS or ES prefix.

Concept of Segmented Memory

• It allows the memory addressing capacity to be 1 Mbytes.

• It allows instruction code, data stack and portion of program to be more than 64KB long.
• It facilitates use of separate memory areas for program, data and stack.
• It permits a program or its data to be put in different areas of memory
• In this program can be relocated which is very useful in multiprogramming i.e.multitasking becomes
easy.

Instruction Pointer
• The Instruction Pointer (IP) in 8086 acts as a Program Counter. It points to the address of the next
instruction to be executed. Its content is automatically incremented when the execution of a program
proceeds further. The contents of the IP and Code Segment Register are used to compute the memory
address of the instruction code to be fetched. This is done during the Fetch Cycle.

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 Concept of Segmented Memory
FFFFFH Highest Address

7FFFFH Top Of Extra Segment

64KB
Extra Segment Base ES=7000H

5FFFFH Top Of Stack Segment

64KB
50000H Stack Segment Base SS=5000H
4489FH Top Of Code Segment
64KB
348A0H Code Segment Base CS=348AH

2FFFFH Top Of Data Segment

64KB
20000H Bottom Of Data Segment
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Status Flags
Status Flags determines the current state of the accumulator. They are modified automatically by CPU after
mathematical operations. This allows to determine the type of the result. 8086 has 16-bit status register. It is
also called Flag Register or Program Status Word (PSW). There are nine status flags and seven bit positions
remain unused.

15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

OF DF IF TF SF ZF AF PF CF

Carry Flag
Undefined Parity
Flag
Auxiliary Carry Flag
Zero Flag
Sign Flag
Trap Flag
Interrupt Flag
Direction Flag
Overf low Flag 25

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The following Figure shows the bit definitions for the 16-bit flag register.
• Six of the flags are status indicators reflecting properties of the result of the last arithmetic or logical
instruction
• 8086 flag word. DF, IF, and TF can be set or reset to control the operation of the processor.
• The remaining flags are status indicators. Bits marked X are undefined.

Flag Register: This register is also called status register. It is a 16 bit register which contains six status flags
and three control flags. So, only nine bits of the 16 bit register are defined and the remaining seven bits are
undefined. Normally this status flag bits indicate the status of the ALU after the arithmetic or logical
operations. Each bit of the status register is a flip/flop. The Flag register contains Carry flag, Parity flag,
Auxiliary flag Zero flag, Sign flag ,Trap flag, Interrupt flag, Direction flag and overflow flag as shown in the
diagram. The CF,PF,AF,ZF,SF,OF are the status flags and the TF,IF and CF are the control flags.

CF- Carry Flag: This flag is set, when there is a carry out of MSB in case of addition or a borrow in case of
subtraction.

PF - Parity Flag : This flag is set to 1, if the lower byte of the result contains even number of 1’s else (for
odd number of 1s ) set to zero.

AF- Auxilary Carry Flag: This is set, if there is a carry from the lowest nibble, i.e, bit three during addition,
or borrow for the lowest nibble, i.e, bit three, during subtraction.

ZF- Zero Flag: This flag is set, if the result of the computation or comparison performed by the previous
instruction is zero

SF- Sign Flag : This flag is set, when the result of any computation is negative

TF - Tarp Flag: If this flag is set, the processor enters the single step execution mode.

IF- Interrupt Flag: If this flag is set, the maskable interrupt INTR of 8086 is enabled and if it is zero ,the
interrupt is disabled.It can be set by using the STI instruction and can be cleared by executing CLI
instruction.
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DF- Direction Flag: This is used by string manipulation instructions. If this flag bit is ‘0’, the string is
processed beginning from the lowest address to the highest address, i.e., auto incrementing mode.
Otherwise, the string is processed from the highest address towards the lowest address, i.e., auto
incrementing mode.

OF- Over flow Flag: This flag is set, if an overflow occurs, i.e, if the result of a signed operation is large
enough to accommodate in a destination register. The result is of more than 7-bits in size in case of 8-bit
signed operation and more than 15-bits in size in case of 16-bit sign operations, then the overflow will be
set.

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1.3 8086 PIN DIAGRAM – PIN DESCRIPTION
Intel 8086 is a 16-bit HMOS microprocessor. It is available in 40 pin DIP chip. It uses a 5V d.c. supply for
its operation. The 8086 uses 20-line address bus. It uses a 16-line data bus. The 20 lines of the address bus
operate in multiplexed mode. The 16-low order address bus lines are multiplexed with data and 4 high-order
address bus lines are multiplexed with status signals. The pin diagram of Intel 8086 is shown in Fig.4.

AD0-AD15 (Bidirectional) : Address/Data bus. These are low order address bus. They are multiplexed with
data. When AD lines are used to transmit memory address the symbol A is used instead of AD, for example
A0-A15. When data are transmitted over AD lines the symbol D is used in place of AD, for example D0-D7,
D8-D15 or D0-D15.

A16-A19 (Output) : High order address bus. These are multiplexed with status signals.
A16/S3, A17/S4, A18/S5, A19/S6 : The specified address lines are multiplexed with corresponding status signals.

BHE (Active Low)/S7 (Output) : Bus High Enable/Status. During T1 it is low. It is used to enable data onto
the most significant half of data bus, D8-D15. 8-bit device connected to upper half of the data bus use BHE
(Active Low) signal. It is multiplexed with status signal S7. S7 signal is available during T2, T3 and T4.

RD (Read) (Active Low) : The signal is used for read operation. It is an output signal. It is active when low.

READY : This is the acknowledgement from the slow device or memory that they have completed the data
transfer. The signal made available by the devices is synchronized by the 8284A clock generator to provide
ready input to the 8086. the signal is active high.

INTR-Interrupt Request : This is a triggered input. This is sampled during the last clock cycles of each
instruction to determine the availability of the request. If any interrupt request is pending, the processor
enters the interrupt acknowledge cycle. This can be internally masked by resulting the interrupt enable flag.
This signal is active high and internally synchronized.

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 Fig.4. Pin Diagram of 8086 Processor
NMI (Input) –NON-MASKABLE INTERRUPT : It is an edge triggered input which causes a type 2
interrupt. A subroutine is vectored to via an interrupt vector lookup table located in system memory. NMI is
not maskable internally by software. A transition from LOW to HIGH initiates the interrupt at the end of the
current instruction. This input is internally synchronized.
INTA: INTA: Interrupt acknowledge. It is active LOW during T 2 ,T 3 and T w of each interrupt
acknowledge cycle.
MN/ MX MINIMUM / MAXIMUM :This pin signal indicates what mode the processor is to operate in.
RQ/GT RQ/GT0 : REQUEST/GRANT: These pins are used by other local bus masters to force the
processor to release the local bus at the end of the processor's current bus cycle. Each pin is bidirectional
with RQ/GT having higher priority than RQ /GT 1.
LOCK: Its an active low pin. It indicates that other system bus masters are not to allowed to gain control
of the system bus while LOCK is active LOW. The LOCK signal remains active until the completion of
the next instruction.

TEST : This input is examined by a ‘WAIT’ instruction. If the TEST pin goes low, execution will continue,
else the processor remains in an idle state. The input is synchronized internally during each clock cycle on
leading edge of clock.

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CLK- Clock Input : The clock input provides the basic timing for processor operation and bus control
activity. Its an asymmetric square wave with 33% duty cycle.

RESET (Input) : RESET: causes the processor to immediately terminate its present activity. The signal
must be active HIGH for at least four clock cycles.
Vcc – Power Supply ( +5V D.C.)
GND – Ground
QS1,QS0 (Queue Status) These signals indicate the status of the internal 8086 instruction queue according to
the table shown below

QSI QS0 Status

0 (LOW) 0 No Operation

1 First Byte of Op Code from Queue

0
0 Empty the Queue

1 (HIGH) 1
Subsequent Byte from Queue

DT/R : DATA TRANSMIT/RECEIVE: This pin is needed in minimum system that desires to use an
8286/8287 data bus transceiver. It is used to control the direction of data flow through the transceiver.

DEN: DATA ENABLE .This pin is provided as an output enable for the 8286/8287 in a minimum system
which uses the transceiver. DEN is active LOW during each memory and I/O access and for INTA cycles.

HOLD/HOLDA : HOLD indicates that another master is requesting a local bus .This is an active HIGH.
The processor receiving the ``hold'' request will issue HLDA (HIGH) as an acknowledgement in the middle
of a T 4 or T 1 clock cycle.

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1.4 MEMORY ORGANIZATION AND SEGMENTATION

The 8086 processor provides a 20-bit address toaccess any location of the 1 MB memory space. The
memory is organized as a linear array of 1 million bytes, addressed as 00000(H) to FFFFF(H). The memory
is logically divided into code, data, extra data, and stack segments of up to 64K bytes each . Physically, the
memory is organized as a high bank (D15 - D8) and a low bank (D7 –D0) of 512 K 8-bitbytes addressed in
parallel by the processor's address lines A19 -A1. Byte data with even addresses is transferred on the D7 –
D0 bus lines while odd addressed byte data (A0 HIGH) is transferred on the D15-D8 bus lines. The
processor provides two enable signals, BHE and A0 , to selectively allow reading from or writing into either
an odd byte location, even byte location, or both. The instruction stream is fetched from memory as words
and is addressed internally by the processor to the byte level as necessary.

1.5 INTERRUPTS :

An interrupt to the microprocessor is defined as that which disturbs the normal execution of a program .
Broadly the interrupts are divided into two types. They are external hardware Interrupts and internal
(Software) Interrupts . The hardware interrupts are classified as non-maskable and maskable interrupts. The
hardware interrupt is caused by any peripheral device by sending a signal through a specified pin to the
microprocessor. Whereas internal interrupts are initiated by the state of the CPU (e.g. divide by zero error)
or by an instruction. So, the software interrupt is one which interrupts the normal execution of a program of
the microprocessor. The 8086 has two hardware interrupt pins namely NMI and INTR.In the two ,the NMI
is a non-maskable interrupt and the INTR interrupt request is a maskable interrupt which has lower proirity
.The third pin associated with the hardware interrupts are the INTA called interrupt acknowledge.

NMI : The processor provides a single non-maskable interrupt pin (NMI) which has higher priority than the
maskable interrupt request pin (INTR). A typical use would be to activate a power failure routine. The NMI
is edge-triggered on a LOW-to-HIGH transition. The activation of this pin causes a type 2 interrupt.
INTR: The 8086 provides a single interrupt request input (INTR) which can be masked internally by
software with the resetting of the interrupt enable FLAG status bit. The interrupt request signal is level
triggered. It is internally synchronized during each clock
cycle on the high-going edge of CLK. To be responded to, INTR must be present (HIGH) during the clock
period preceding the end of the current instruction or the end of a whole move for a block type instruction.
Software Interrupts: Coming to the software interrupts , 8086 can generate 256 interrupt types through the

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instruction INT n .Any of the 256 interrupt types can be generated by specifying the interrupt type after INT
instruction . For example INT 33 will cause type 33 interrupt.
I k Bytes of memory from 00000H to 003FF H is set aside to store the starting address
of the Interrupt service sub-routine(ISS) programs in an 8086 based systems. To store the starting address of
the each ISS , four bytes of memory space is required.Two bytes are for storing CS value and two bytes for
IP value. The starting address of an ISS stored in 1kB of memory space is called Interrupt pointer or Interrupt
vector.The 1kB memory space acts as a table and it is called Interrupt Vector Table(IVT).

The 256 interrupt pointers have been numbered from 0 to 255.The number given to an
interrupt pointer denotes the type of the interrupt. For example Type0,Type1,Type2 etc…The starting
address of the ISS for type0 interrupt is 000000H.For type1 interrupt is 00004H similarly for type2 is
00008H ……In the IVT the first five pointers are dedicated interrupt pointers. They are :
TYPE 0 Interrupt corresponds to divide by zero situation
TYPE 1 Interrupt corresponds to Single step execution during the debugging of a program.
TYPE 2 Interrupts to non-maskable NMI interrupt.
TYPE 3 :Interrupt corresponds to break point interrupt.
TYPE 4 Interrupt corresponds to Overflow interrupt.
The Interrupts from Type 5 to Type 31 are reserved for other advanced microprocessors,and from
32 to Type 255 are available for hardware and software interrupts.

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Differences between CALL and INT : In fact both the instructions CALL and INT n
will interrupt the execution of the main program. But there are certain differences
between their functioning. They are given below in the table.

S.No CALL Instruction INTn instruction

1 Upon the execution ,the Upon execution the
control will jump to any control will jump to a fixed
one of the 1 MB of location in the vector
memory locations . table.
2 The user can insert in the Can occur at any time
sequence of instructions of activated by hardware
a program
3 Once initiated it cannot be Can be masked
masked
4 When initiated ,it stores When initiated ,it stores
the CS:IP of the next the CS:IP of the next
instruction on the stack instruction and also the
flag register on the stack.
5 The last instruction of the The last instruction of the
subroutine will be RET ISS will be IRET

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 1.6 ADDRESSING MODES:

The different ways in which a source operand is denoted in an instruction are known as the addressing
modes. There are 8 different addressing modes in 8086 programming. They are
1. Immediate addressing mode
2. Register addressing mode
3. Direct addressing mode
4. Register indirect addressing mode
5. Based addressing mode
6. Indexed addressing mode.
7. Based indexed addressing mode
8. Based, Indexed with displacement.

Immediate addressing mode: The addressing mode in which the data operand is a part of the instruction
itself is called Immediate addressing mode.

For Ex: MOV CX, 4847 H

ADD AX, 2456 H
MOV AL, FFH

Register addressing mode : Register addressing mode means, a register is the source of an operand for an
instruction.

For Ex : MOV AX, BX copies the contents of the 16-bit BX register into the 16-bit AX register.
EX : ADD CX,DX

Direct addressing mode: The addressing mode in which the effective address of the memory location at
which the data operand is stored is given in the instruction.i.e the effective address is just a 16-bit number is
written directly in the instruction.

For Ex: MOV BX, [1354H]

MOV BL,[0400H]

. The square brackets around the 1354 H denotes the contents of the memory location. When executed, this
instruction will copy the contents of the memory location into BX register. This addressing mode is called
direct because the displacement of the operand from the segment base is specified directly in the instruction.

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Register indirect addressing mode: Register indirect addressing allows data to be addressed at any memory
location through an offset address held in any of the following registers: BP, BX, DI and SI.

Ex: MOV AX, [BX]. Suppose the register BX contains 4675H ,the contents of the 4675 H are
moved to AX.
ADD CX,{BX}

Based addressing mode: The offset address of the operand is given by the sum of contents of the BX or BP
registers and an 8-bit or 16-bit displacement.
Ex: MOV DX, [BX+04]
ADD CL,[BX+08]

Indexed Addressing mode: The operands offset address is found by adding the contents of SI or DI
register and 8-bit or 16-bit displacements.
Ex: MOV BX,[SI+06]
ADD AL,[DI+08]

Based -index addressing mode: The offset address of the operand is computed by summing the base
register to the contents of an Index register.

Ex: ADD CX,[BX+SI]

MOV AX,[BX+DI]

Based Iindexd with displacement mode: The operands offset is computed by adding the base register
contents, an Index registers contents and 8 or 16-bit displacement.
Ex : MOV AX,[BX+DI+08]
ADD CX,[BX+SI+16]

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 1.7 ASSEMBLER DIRECTIVES & Macros

Assembler directives are the directions to the assembler which indicate how an operand or section of
the program is to be processed. These are also called pseudo operations which are not executable by the
microprocessor. The various directives are explained below.
1. ASSUME : The ASSUME directive is used to inform the assembler the name of the logical segment it
should use for a specified segment.
Ex: ASSUME DS: DATA tells the assembler that for any program instruction which refers to the data
segment ,it should use the logical segment called DATA.
2.DB -Define byte. It is used to declare a byte variable or set aside one or more storage locations of type
byte in memory.
For example, CURRENT_VALUE DB 36H tells the assembler to reserve 1 byte of memory for a variable
named CURRENT_ VALUE and to put the value 36 H in that memory location when the program is loaded
into RAM .
3. DW -Define word. It tells the assembler to define a variable of type word or to reserve storage locations
of type word in memory.
4. DD(define double word) :This directive is used to declare a variable of type double word or restore
memory locations which can be accessed as type double word.
5.DQ (define quadword) :This directive is used to tell the assembler to declare a variable 4 words in length
or to reserve 4 words of storage in memory .
6.DT (define ten bytes):It is used to inform the assembler to define a variable which is 10 bytes in length or
to reserve 10 bytes of storage in memory.
7. EQU –Equate It is used to give a name to some value or symbol. Every time the assembler finds the
given name in the program, it will replace the name with the value or symbol we have equated with that
name
8.ORG -Originate : The ORG statement changes the starting offset address of the data.
It allows to set the location counter to a desired value at any point in the program.For example the statement
ORG 3000H tells the assembler to set the location counter to 3000H.
9 .PROC- Procedure: It is used to identify the start of a procedure. Or subroutine.
10. END- End program .This directive indicates the assembler that this is the end of the program module.The
assembler ignores any statements after an END directive.
11. ENDP- End procedure: It indicates the end of the procedure (subroutine) to the assembler.
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12.ENDS-End Segment: This directive is used with the name of the segment to indicate the end of that
logical segment.
Ex: CODE SEGMENT : Start of logical segment containing code
CODE ENDS : End of the segment named CODE.

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1.7.1 ASSEMBLY LANGUAGE DEVELOPMENT TOOLS:
To develop an assembly language program we need certain program development tools .The various
development tools required for 8086 programming are explained below.
1. Editor : An Editor is a program which allows us to create a file containing the assembly language
statements for the program. Examples of some editors are PC write Wordstar. As we type the program the
editor stores the ACSII codes for the letters and numbers in successive RAM locations. If any typing mistake
is done editor will alert us to correct it. If we leave out a program statement an editor will let you move
everything down and insert a line. After typing all the program we have to save the program for a hard disk.
This we call it as source file. The next step is to process the source file with an assembler. While using
TASM or MASM we should give a file name and extension .ASM.

Ex: Sample. asm

2.Assembler : An Assembler is used to translate the assembly language mnemonics into machine language(
i.e binary codes). When you run the assembler it reads the source file of your program from where you have
saved it. The assembler generates two files . The first file is the Object file with the extension .OBJ. The
object file consists of the binary codes for the instructions and information about the addresses of the
instructions. After further processing, the contents of the file will be loaded in to memory and run. The
second file is the assembler list file with the extension .LST.

3. Linker : A linker is a program used to connect several object files into one large object file. While
writing large programs it is better to divide the large program into smaller modules. Each module can be
individually written, tested and debugged. Then all the object modules are linked together to form one,
functioning program. These object modules can also be kept in library file and linked into other programs as
needed. A linker produces a link file which contains the binary codes for all the combined modules. The
linker also produces a link map file which contains the address information about the linked files. The linkers
which come with TASM or MASM assemblers produce link files with the .EXE extension.

4.Locator : A locator is a program used to assign the specific addresses of where the segments of object
code are to be loaded into memory. A locator program called EXE2BIN comes with the IBM PC Disk
Operating System (DOS). EXE2BIN converts a .EXE file to a .BIN file which has physical addresses.

5. Debugger: A debugger is a program which allows to load your object code program into system
memory, execute the program, and troubleshoot or debug it. The debugger allows to look into the contents

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of registers and memory locations after the program runs. We can also change the contents of registers and
memory locations and rerun the program. Some debuggers allows to stop the program after each instruction
so that you can check or alter memory and register contents. This is called single step debug. A debugger
also allows to set a breakpoint at any point in the program. If we insert a break point , the debugger will run
the program up to the instruction where the breakpoint is put and then stop the execution.

6. Emulator: An emulator is a mixture of hard ware and software. It is usually used to test and debug the
hardware and software of an external system such as the prototype of a microprocessor based instrument.

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1.8 Instruction set of 8086 Microprocessor

1. Data Transfer Instructions

2. Arithmetic Instructions

3. Bit Manipulation Instructions

4. Program Execution Transfer Instructions

5. String Instructions

6. Processor Control Instructions

DATA TRANSFER INSTRUCTIONS

1. These instructions are used to transfer data from source to destination.

2. The operand can be a constant, memory location, register or I/O port address.

Mnemonic Meaning Format Operation

MOV Move Mov D,S (S) à (D)

XCHG Exchange XCHG D,S (S) (D)

LEA Load Effective LEA Reg16,EA EA à (Reg16)

Address

LDS Load Register And LDS Reg16,MEM32 (MEM32) à (Reg16)

DS (Mem32+2) à (DS)

LES Load Register LES Reg16,MEM32 (MEM32) à

&ES (Reg16)(Mem32+2) à (DS)

i. MOV Des, Src

1. Src operand can be register, memory location or immediate operand.

2. Des can be register or memory operand.

3. Both Src and Des cannot be memory location at the same time.

E.g.: MOV CX, 037A H , MOV AL, BL

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 ii. PUSH Operand

 It pushes the operand into top of stack.

E.g.: PUSH BX
iii. POP Des
 It pops the operand from top of stack to Des.

 Des can be a general purpose register, segment register (except CS) or memory location.
E.g.: POP AX
iv. XCHG Des, Src
 This instruction exchanges Src with Des.

 It cannot exchange two memory locations directly.

E.g.: XCHG DX, AX

v. IN Accumulator, Port Address
 It transfers the operand from specified port to accumulator register.

E.g.: IN AX, 0028 H

vi. OUT Port Address, Accumulator
 It transfers the operand from accumulator to specified port.

E.g.: OUT 0028 H, AX

vii. LDS Des, Src
 It loads 32-bit pointer from memory source to destination register and DS.

 E.g: LDS BX, [0301 H]

viii. LES Des, Src

 It loads 32-bit pointer from memory source to destination register and ES.

ix LAHF
 It copies the lower byte of flag register to AH.

x SAHF
 It copies the contents of AH to lower byte of flag register.

xi PUSHF
 Pushes flag register to top of stack.

xii POPF
 Pops the stack top to flag register.

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ARITHMETIC INSTRUCTIONS

Mnemonic Meaning Format Operation

SUB Subtract SUB D,S (D) - (S) à (D)

Borrow à (CF)

SBB Subtract with SBB D,S (D) - (S) - (CF) à (D)

borrow

DEC Decrement by one DEC D (D) - 1 à (D)

NEG Negate NEG D

DAS Decimal adjust DAS Convert the result in AL to

for subtraction packed decimal format

AAS ASCII adjust for AAS (AL) difference (AH) dec by

subtraction 1 if borrow

ADD Addition ADD D,S (S)+(D) à (D)

carry à (CF)

ADC Add with carry ADC D,S (S)+(D)+(CF) à (D)

carry à (CF)

INC Increment by one INC D (D)+1 à (D)

AAA ASCII adjust for AAA If the sum is >9, AH

addition is incremented by 1

DAA Decimal adjust DAA Adjust AL for decimal

for addition Packed BCD

i. ADC Des, Src:

 It adds the two operands with CF.

 It effects AF, CF, OF, PF, SF, ZF flags.

 E.g ADC AL, 74H ADC DX, AX

ii. ADD Des, Src

 It adds a byte to byte or a word to word.

 It effects AF, CF, OF, PF, SF, ZF flags.

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  E.g ADD AL, 74H ADD DX, AX

iii. SUB Des, Src

 It subtracts a byte from byte or a word from word.

 It effects AF, CF, OF, PF, SF, ZF flags.

 For subtraction, CF acts as borrow flag.

iv. SBB Des, Src

 It subtracts the two operands and also the borrow from the result

 Eg: SBB AL, 74H SBB DX, AX

v. INC Src

 It increments the byte or word by one.

 It effects AF, OF, PF, SF, ZF flags. CF is not effected

vi. DEC Src

 It decrements the byte or word by one.

 It effects AF, OF, PF, SF, ZF flags. CF is not effected

vii. AAA (ASCII Adjust after Addition)

 The data entered from the terminal is in ASCII format

o AAS (ASCII Adjust after Subtraction)

o AAM (ASCII Adjust after Multiplication)

o AAD (ASCII Adjust Before Division)

viii. DAA (Decimal Adjust after Addition)

 It is used to make sure that the result of adding two BCD numbers is adjusted to be a correct
BCD number.

 It only works on AL register

ix. DAS (Decimal Adjust after Subtraction)

 It is used to make sure that the result of subtracting two BCD numbers is adjusted to be a
correct BCD number.
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  It only works on AL register.

x. NEG Src

 It creates 2’s complement of a given number.

 That means, it changes the sign of a number.

xi. CMP Des, Src

 It compares two specified bytes or words.

 The Src and Des can be a constant, register or memory location.

 Both operands cannot be a memory location at the same time.

 The comparison is done simply by internally subtracting the source from destination.

 The value of source and destination does not change, but the flags are modified to indicate the
result.

xii. MUL Src

 It is an unsigned multiplication instruction.

 It multiplies two bytes to produce a word or two words to produce a double word.

 AX = AL * Src

 DX : AX = AX * Src

 This instruction assumes one of the operand in AL or AX.

 Src can be a register or memory location.

xiii. IMUL Src:

 It is a signed multiplication instruction

xiv. DIV Src :

 It is an unsigned division instruction.

 It divides word by byte or double word by word.

 The operand is stored in AX, divisor is Src and the result is stored as:

 AH = remainder AL = quotient

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 xv. IDIV Src:

 It is a signed division instruction

xvi. CBW (Convert Byte to Word)

 This instruction converts byte in AL to word in AX.

 The conversion is done by extending the sign bit of AL throughout AH.

xvii. CWD (Convert Word to Double Word)

 This instruction converts word in AX to double word in DX : AX

 The conversion is done by extending the sign bit of AX throughout DX

Programming Examples & Tools

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Multiplication and Division Examples

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MULTIPLICATION AND DIVISION:

Multiplication Multiplicand Operand Result

(MUL or IMUL) (Multiplier)

Byte*Byte AL Register or memory AX

Word*Word AX Register or memory DX :AX

Dword*Dword EAX Register or memory EAX :EDX

Division Dividend Operand Quotient: Remainder

(DIV or IDIV) (Divisor)

Word/Byte AX Register or Memory AL : AH

Dword/Word DX:AX Register or Memory AX : DX

Qword/Dword EDX: EAX Register or Memory EAX : EDX

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Bit Manipulation Instructions

 These instructions are used at the bit level.

 These instructions can be used for:

 Testing a zero bit

 Set or reset a bit

 Shift bits across registers

Mnemonic Meaning Format Operation

AND Logical AND AND D,S (S) · (D) → (D)

OR Logical Inclusive OR OR D,S (S) + (D) → (D)
XOR Logical Exclusive OR XOR D,S (S)(D) → (D)
NOT LOGICAL NOT NOT D (D) → (D)

i. AND

 Especially used in clearing certain bits (masking)

 xxxx xxxx AND 0000 1111 = 0000 xxxx

(clear the first four bits B7-B4)

–Examples: AND BL, 0FH
ii. OR
 Used in setting certain bits

 xxxx xxxx OR 0000 1111 = xxxx 1111

(Set the upper four bits B4-B0)

iii. XOR

 Used in Inverting bits

 xxxx xxxx XOR 0000 1111 = xxxx x’x’x’x’ (Invert the upper four bits B 4-B0)

Example: Clear bits 0 and 1, set bits 6 and 7, invert bit 5 of register CL:
 AND CL, FCH ; 1111 1100B

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  OR CL, C0H ; 1100 0000B

 XOR CL, 20H ; 0010 0000B

iv. SHL

 The SHL (shift left) instruction performs a logical left shift on the destination operand, filling
the lowest bit with 0.

 Example:

mov DL,4
shl DL,1 RESULT DL =10 ( 4 * 21 = 8 )
v. SHR

 The SHR (shift right) instruction performs a logical right shift on the destination operand. The
highest bit position is filled with a zero

 Example:

mov DL,8
shr DL,1 RESULT DL =4 ( 8 / 21 = 4 )
vi. SAR

 performs a right arithmetic shift on the destination operand

 Example:

mov DL,-8
sar DL,2 RESULT DL = - 2 ( - 8 / 22 = - 2 )
vii. ROL

 ROL (rotate) shifts each bit to the left

 The highest bit is copied into both the Carry flag and into the lowest bit

 No bits are lost

 Example:

 Example:

viii. ROR

 ROR (rotate right) shifts each bit to the right

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  The lowest bit is copied into both the Carry flag and into the highest bit

 No bits are lost

ix. RCL

 RCL (rotate carry left) shifts each bit to the left

 Copies the Carry flag to the least significant bit

 Copies the most significant bit to the Carry flag

x. ROR Instruction

 ROR (rotate right) shifts each bit to the right

 The lowest bit is copied into both the Carry flag and into the highest bit

 No bits are lost

xi. RCR

 RCR (rotate carry right) shifts each bit to the right

 Copies the Carry flag to the most significant bit

 Copies the least significant bit to the Carry flag

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 PROGRAM EXECUTION TRANSFER INSTRUCTIONS

 These instructions cause change in the sequence of the execution of instruction.

 This change can be through a condition or sometimes unconditional.

 The conditions are represented by flags.

i. CALL Des

 This instruction is used to call a subroutine or function or procedure.

 The address of next instruction after CALL is saved onto stack.

ii. RET

 It returns the control from procedure to calling program.

 Every CALL instruction should have a RET.
iii. JMP Des

 This instruction is used for unconditional jump from one place to another

iv. Jxx Des

 All the conditional jumps follow some conditional statements or any instruction that affects
the flag

Mnemonic meaning condition

JA Above CF=0 and ZF=0

JB Above or Equal CF=0

JB Below CF=1
JBE Below or Equal CF=1 or ZF=1
JC Carry CF=1
JCXZ CX register is Zero (CF or ZF)=0
JE Equal ZF=1
JG Greater ZF=0 and SF=OF
JGE Greater or Equal SF=OF
JL Less (SF XOR OF) = 1

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 Mnemonic meaning condition

JLE Less or Equal ((SF XOR OF) or ZF) = 1

JNA Not Above CF =1 or Zf=1

JNAE Not Above nor Equal CF = 1

JNB Not Below CF = 0

JNBE Not Below nor Equal CF = 0 and ZF = 0

JNC Not Carry CF = 0

JNE Not Equal ZF = 0

JNG Not Greater ((SF XOR OF) or ZF)=1

JNGE Not Greater nor Equal (SF XOR OF) = 1

JNL Not Less SF = OF

Mnemonic meaning format Operation

LOOP Loop Loop short-label (CX) ß (CX) – 1

Jump to location given by
short-label if CX ≠ 0

LOOPE/ Loop while LOOPE/LOOPZ (CX) ß (CX) – 1

LOOPZ equal/ loop while short-label Jump to location given by
zero short-label if CX ≠ 0 and
ZF=1

LOOPNE/ Loop while not LOOPNE/LOOPN (CX) ß (CX) – 1

LOOPNZ equal/ loop while Z short-label Jump to location given by
not zero short-label if CX ≠ 0 and
ZF=0

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 v. Loop Des:

 This is a looping instruction.

 The number of times looping is required is placed in the CX register.

 With each iteration, the contents of CX are decremented.

 ZF is checked whether to loop again or not.

STRING INSTRUCTIONS

 String in assembly language is just a sequentially stored bytes or words.

 There are very strong set of string instructions in 8086.

 By using these string instructions, the size of the program is considerably reduced.

CMPS Des, Src:

o It compares the string bytes or words.

SCAS String:
 It scans a string.

 It compares the String with byte in AL or with word in AX.

MOVS / MOVSB / MOVSW

 It causes moving of byte or word from one string to another.

 In this instruction, the source string is in Data Segment and destination string is in Extra
Segment.

 SI and DI store the offset values for source and destination index.

REP (Repeat):
 This is an instruction prefix.

 It causes the repetition of the instruction until CX becomes zero.

 E.g.: REP MOVSB STR1, STR2

.a. It copies byte by byte contents.

.b. REP repeats the operation MOVSB until CX becomes zero.

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PROCESSOR CONTROL INSTRUCTIONS

 These instructions control the processor itself.

 8086 allows to control certain control flags that:

 causes the processing in a certain direction

 processor synchronization if more than one microprocessor attached.

STC:
o It sets the carry flag to 1.
CLC:
o It clears the carry flag to 0.
CMC:
o It complements the carry flag.
STD:
o It sets the direction flag to 1.
o If it is set, string bytes are accessed from higher memory address to lower memory
address.
CLD:
o It clears the direction flag to 0.
o If it is reset, the string bytes are accessed from lower memory address to higher
memory address.
HLT instruction – HALT processing
The HLT instruction will cause the 8086 to stop fetching and executing
instructions.
NOP instruction
this instruction simply takes up three clock cycles and does no processing.
LOCK instruction
This is a prefix to an instruction. This prefix makes sure that during execution of the
instruction, control of system bus is not taken by other microprocessor.
WAIT instruction
This instruction takes 8086 to an idle condition. The CPU will not do any processing
during this.

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ESC instruction
whenever this instruction executes, the microprocessor does NOP or access a data from
memory for coprocessor. This instruction passes the information to 8087 math processor. Six bits of ESC
instruction provide the opcode to coprocessor.
when 8086 fetches instruction bytes, co-processor also picks up these bytes and puts in its
queue. The co-processor will treat normal 8086 instructions as NOP. Floating point instructions are executed
by 8087 and during this 8086 will be in WAIT.

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