.

UNIT

8086 PROCESSOR

Syllabus

Intel 8086 microprocessor

Architecture
Instruction set and assembler directives
Addressing modes
Interrupts and interrupt service routines
Assembly language programming Procedures Macros (check in file name
UNIT_2_PRO)


The 8086 is a 16-bit microprocessor chip designed by Intel and introduced on the market in
1978, which gave rise to the x86 architecture.

Intel 8088, released in 1979, was essentially the same chip, but with an external 8-bit data
bus (allowing the use of cheaper and fewer supporting logic chips), and is notable as the
processor used in the original IBM PC.

The first multi-chip 16-bit microprocessor was the National Semiconductor IMP-16,
introduced in early 1973.

An 8-bit version of the chipset was introduced in 1974 as the IMP-8. During the same year,
National introduced the first 16-bit single-chip microprocessor, the National
Semiconductor PACE, which was later followed by an NMOS version, the INS8900.

Intel followed a different path, having no minicomputers to emulate, and instead "upsized"
their 8080 design into the 16-bit Intel 8086, the first member of the x86 family which
powers most modern PC type computers.

Intel introduced the 8086 as a cost effective way of porting software from the 8080 lines,
and succeeded in winning much business on that premise.

The 8088, a version of the 8086 that used an external 8-bit data bus, was the
microprocessor in the first IBM PC, the model 5150.

Following up their 8086 and 8088, Intel released the 80186, 80286 and, in 1985, the 32-bit
80386, cementing their PC market dominance with the processor family's backwards
compatibility.

The integrated microprocessor memory management unit (MMU) was developed by
Childs et al. of Intel, and awarded US patent number 4,442,484.

8086 CPU ARCHITECTURE

The microprocessors functions as the CPU in the stored program model of the digital computer. Its
job is to generate all system timing signals and synchronize the transfer of data between memory,
I/O, and itself. It accomplishes this task via the three-bus system architecture previously discussed.
The microprocessor also has a S/W function. It must recognize, decode, and execute program
instructions fetched from the memory unit. This requires an Arithmetic-Logic Unit (ALU) within
the CPU to perform arithmetic and logical (AND, OR, NOT, compare, etc) functions. The 8086
CPU is organized as two separate processors, called the Bus Interface Unit (BIU) and the Execution
Unit (EU).

The BIU provides H/W functions, including generation of the memory and I/O addresses
for the transfer of data between the outside world -outside the CPU, that is- and the EU.


The EU receives program instruction codes and data from the BIU, executes these
instructions, and store the results in the general registers.

By passing the data back to the BIU, data can also be stored in a memory location or written
to an output device.

The important point to note, however, is that because the EU is the same for each
processor, the programming instructions are exactly the same for each. Programs written
for the 8086 can be run on the 8088 without any changes.

FETCH AND EXECUTE

Although the 8086/88 still functions as a stored program computer, organization of the CPU into a
separate BIU and EU allows the fetch and execute cycles to overlap. To see this, consider what
happens when the 8086 or 8088 is first started.
1. The BIU outputs the contents of the instruction pointer register (IP) onto the address bus, causing
the selected byte or word to be read into the BIU.
2. Register IP is incremented by 1 to prepare for the next instruction fetch.3. Once inside the BIU,
the instruction is passed to the queue. This is a first-in, first-out storage register sometimes likened
to a "pipeline".
4. Assuming that the queue is initially empty, the EU immediately draws this instruction from the
queue and begins execution.
5. While the EU is executing this instruction, the BIU proceeds to fetch a new instruction.
Depending on the execution time of the first instruction, the BIU may fill the queue with several
new instructions before the EU is ready to draw its next instruction.

The BIU is programmed to fetch a new instruction whenever the queue has room for one (with the
8088) or two (with the 8086) additional bytes.
The advantage of this pipelined architecture is that the EU can execute instructions almost
continually instead of having to wait for the BIU to fetch a new instruction.

PROGRAMING MODEL

As a programmer of the 8086 or 8088 you must become familiar with the various registers
in the EU and BIU. The data group consists of the accumulator and the BX, CX, and DX
registers

The data registers are normally used for storing temporary results that will be acted on by
subsequent instructions.

The pointer and index group are all 16-bit registers (you cannot access the low or high
bytes alone). These registers are used as memory pointers.


Register IP could be considered in the previous group, but this register has only one
function -to point to the next instruction to be fetched to the BIU. Register IP is physically
part of the BIU and not under direct control of the programmer as are the other pointer
registers.

Six of the flags are status indicators, reflecting properties of the result of the last arithmetic
or logical instructions.

Three of the flags can be set or reset directly by the programmer and are used to control the
operation of the processor. These are TF, IF, and DF.

The final group of registers is called the segment group. These registers are used by the BIU
to determine the memory address output by the CPU when it is reading or writing from the
memory unit. To fully understand these registers, we must first study the way the 8086/88
divides its memory into segments.

All general registers of the 8086 microprocessor can be used for arithmetic and
logic operations. The general registers are:

Accumulator register consists of 2 8-bit registers AL and AH, which can be

combined together and used as a 16-bit register AX. AL in this case contains the
low-order byte of the word, and AH contains the high-order byte. Accumulator
can be used for I/O operations and string manipulation.
Base register consists of 2 8-bit registers BL and BH, which can be combined
together and used as a 16-bit register BX. BL in this case contains the low-order
byte of the word, and BH contains the high-order byte. BX register usually

contains a data pointer used for based, based indexed or register indirect
addressing.

Count register consists of 2 8-bit registers CL and CH, which can be combined
together and used as a 16-bit register CX. When combined, CL register contains
the low-order byte of the word, and CH contains the high-order byte. Count
register can be used as a counter in string manipulation and shift/rotate
instructions.

Data register consists of 2 8-bit registers DL and DH, which can be combined
together and used as a 16-bit register DX. When combined, DL register contains
the low-order byte of the word, and DH contains the high-order byte. Data
register can be used as a port number in I/O operations. In integer 32-bit multiply
and divide instruction the DX register contains high-order word of the initial or
resulting number.

The following registers are both general and index registers:

Stack Pointer (SP) is a 16-bit register pointing to program stack.
Base Pointer (BP) is a 16-bit register pointing to data in stack segment. BP
register is usually used for based, based indexed or register indirect addressing.
Source Index (SI) is a 16-bit register. SI is used for indexed, based indexed and
register indirect addressing, as well as a source data address in string manipulation
instructions.
Destination Index (DI) is a 16-bit register. DI is used for indexed, based indexed
and register indirect addressing, as well as a destination data address in string
manipulation instructions.
Other registers:
Instruction Pointer (IP) is a 16-bit register.
Flags is a 16-bit register containing 9 1-bit flags:

Overflow Flag (OF) - set if the result is too large positive number, or is too
small negative number to fit into destination operand.

Direction Flag (DF) - if set then string manipulation instructions will autodecrement index registers. If cleared then the index registers will be autoincremented.

Interrupt-enable Flag (IF) - setting this bit enables maskable interrupts.

Single-step Flag (TF) - if set then single-step interrupt will occur after the
next instruction.

Sign Flag (SF) - set if the most significant bit of the result is set.

Zero Flag (ZF) - set if the result is zero.

Auxiliary carry Flag (AF) - set if there was a carry from or borrow to bits 0-3
in the AL register.

Parity Flag (PF) - set if parity (the number of "1" bits) in the low-order byte
of the result is even.

Carry Flag (CF) - set if there was a carry from or borrow to the most
significant bit during last result calculation.

Memories of 8086
 Program, data and stack memories occupy the same memory space.

 The total addressable memory size is 1MB KB. As the most of the processor
instructions use 16-bit pointers the processor can effectively address only
64 KB of memory.

 To access memory outside of 64 KB the CPU uses special segment registers

to specify where the code, stack and data 64 KB segments are positioned
within 1 MB of memory (see the "Registers" section below).

16-bit pointers and data are stored as:

address: low-order byte
address+1: high-order byte
32-bit addresses are stored in "segment:offset" format as:
address: low-order byte of segment
address+1: high-order byte of segment
address+2: low-order byte of offset
address+3: high-order byte of offset
Physical memory address pointed by segment:offset pair is calculated as:
address = (<segment> * 16) + <offset>

Program memory
program can be located anywhere in memory.
Jump and call instructions can be used for short jumps within currently
selected 64 KB code segment, as well as for far jumps anywhere within 1
MB of memory.
All conditional jump instructions can be used to jump within approximately
+127 - -127 bytes from current instruction.
Data memory
The processor can access data in any one out of 4 available segments, which
limits the size of accessible memory to 256 KB (if all four segments point to
different 64 KB blocks).
Accessing data from the Data, Code, Stack or Extra segments can be usually
done by prefixing instructions with the DS:, CS:, SS: or ES: (some
registers and instructions by default may use the ES or SS segments instead
of DS segment).

 Word data can be located at odd or even byte boundaries.

The processor uses two memory accesses to read 16-bit word located at
odd byte boundaries. Reading word data from even byte boundaries
requires only one memory access.

Stack memory can be placed anywhere in memory. The stack can be located at
odd memory addresses, but it is not recommended for performance reasons (see
"Data Memory" above).

Reserved locations:

0000h - 03FFh are reserved for interrupt vectors. Each interrupt vector is a
32-bit pointer in format segment:offset.

FFFF0h - FFFFFh - after RESET the processor always starts program

execution at the FFFF0h address.

MEMORY MAP
Still another view of the 8086/88 memory space could be as 16 64K-byte blocks beginning at hex
address 000000h and ending at address 0FFFFFh. This division into 64K-byte blocks is an arbitrary
but convenient choice. This is because the most significant hex digit increments by 1 with each
additional block. That is, address 20000h is 65.536 bytes higher in memory than address 10000h. Be
sure to note that five hex digits are required to represent a memory address.

The diagram is called a memory map. This is because, like a road map, it is a guide showing how the
system memory is allocated.

low-oder hex digit must be 0.

Also note that the four segments need not be defined separately. Indeed, it is allowable for all four
segments to completely overlap (CS = DS = ES = SS).
LOGICAL AND PHYSICAL ADDRESS
Addresses within a segment can range from address 00000h to address 0FFFFh. This corresponds
to the 64K-byte length of the segment. An address within a segment is called an offset or logical
address. A logical address gives the displacement from the address base of the segment to the
desired location within it, as opposed to its "real" address, which maps directly anywhere into the 1
MB memory space. This "real" address is called the physical address. What is the difference
between the physical and the logical address?

The physical address is 20 bits long and corresponds to the actual binary code output by the BIU on
the address bus lines. The logical address is an offset from location 0 of a given segment. When two
segments overlap it is certainly possible for two different logical addresses to map to the same
physical address. This can have disastrous results when the data begins to overwrite the subroutine
stack area, or vice versa. For this reason you must be very careful when segments are allowed to
overlap. You should also be careful when writing addresses on paper to do so clearly. To specify the
logical address XXXX in the stack segment, use the convention SS:XXXX, which is equal to [SS] *
16 + XXXX.

INTERRUPTS
NTERRUPT (HW AND SW)
What is an interrupt ?
An interrupt is the method of accessing the MPU by a peripheral device. An
interrupt is used to cause a temporary halt in the execution of a program. The MPU
responds to the interrupt with an interrupt service routine, which is a short program
or subroutine that instructs the MPU on how to handle the interrupt. When the

8086 is executing a program, it can get interrupted because of one of the

following.
Due to an interrupt getting activated. This is called as hardware interrupt.
2. Due to an exceptional happening during an instruction execution, such as
division of a number by zero. This is generally termed as exceptions or Traps.
3. Due to the execution of an Interrupt instruction like INT 21H. This is called a
Software interrupt.
The action taken by the 8086 is similar for all the three cases, except for minor
differences.There are two basic types of interrupts, maskable and non-maskable. A
nonmaskable interrupt requires an immediate response by the MPU. It is usually
used for serious circumstances like power failure. A maskable interrupt is an
interrupt that the MPU can ignore depending upon some predetermined condition
defined by the status register. Interrupts are also prioritized to allow for the case
when more than one interrupt needs to be serviced at the same time.
1.

Hardware interrupts of 8086

. They are NMI and INTR. NMI stands for non maskable interrupt.
If both NMI and INTR are activated at the same time, NMI will be serviced first. In
an 8086 system the first 1 K bytes memory from 00000H to 003FFH is set aside as a
table for storing the starting addresses of interrupt service procedures. Since 4
bytes are required to store the CS and IP values for each interrupt service
procedure, the table can store starting addresses for upto 256 interrupt procedures.
The starting address of an Interrupt Service procedure stored in this table is often
called as Interrupt Vector Table or the Interrupt Pointer Table.Fig. shows how the
256 interrupt pointers are arranged in the memory table. The lowest five types are
dedicated to specific interrupts such as the divide by zero interrupt and the non
maskable interrupt. The next 27 interrupt types, from 5 to 31 are reserved by Intel
for use in future microprocessors. The upper 224 interrupt types, from 32 to 255,
are available to use for hardware and software interrupts.

Action taken by 8086 when NMI is activated

When NMI pin interrupts the 8086, a branch takes place to the ISS, whose
interrupt type number is 2. The action taken is as follows:
1.
2.
3.
4.
5.
6.

Completes the current instruction that is in progress.

Push the Flag register values on to the stack.
Push the CS value and IP value of the return address on to the stack.
IP is loaded from contents of the word location 00008H.
CS is loaded from contents of next word location 0000AH.
Interrupt flag and trap Flag are reset to O.

Return from Interrupt Handler (IRET)

The execution of the IRET instruction results in POP from the stack top, the IP, CS
and Flag registers. Thus return back to the interrupted program takes place. When
the control is transferred back to the interrupted program, the register values are
not the same it was before the occurrence of interrupt. To solve this problem, an
ISS starts with saving register values on the stack. Finally, the register values are
restored from the stack and a return to the interrupted program takes place using
the IRET instruction.

Action taken by 8086 when INTR line is activated

Whenever an external signal activates the INTR pin, the microprocessor will be
interrupted only if interrupts are enabled using set interrupt Flag instruction. If the
interrupts are disabled using clear interrupt Flag instruction, the microprocessor
will not get interrupted even if INTR is activated. That is, INTR can be masked.
INTR is a non vectored interrupt, which means, the 8086 does not know where to
branch to service the interrupt. The 8086 has to be told by an external device like a
Programmable Interrupt controller regarding the branch. Whenever the INTR pin
is activated by an I/O port, if Interrupts are enabled and NMI is not active at that
time, the microprocessor finishes the current instruction that is being executed and
gives out a 0 on INTA pin twice. When INTA pin goes low for the first time, it
asks the external device to get ready. In response to the second INTA the
microprocessor receives the 8 bit, say N, from a programmable Interrupt
controller. The action taken is as follows.
1. Complete the current instruction.
2. Activates INTA output, and receives type Number, say N.
32
3. Flag register value, CS value of the return address & IP value of the return
address are pushed on to the stack.
4. IP value is loaded from contents of word location N x 4.
5. CS is loaded from contents of the next word location.
6. Interrupt Flag and trap Flag are reset to 0.
At the end of the ISS, there will be an IRET instruction. This performs popping
off from the stack top to IP, CS and Flag registers. Finally, the register values
which are also saved on the stack at the start of ISS, are restored from the stack
and a return to the interrupted program takes place using the IRET instruction.

Divide-by-zero interrupt - Type 0

The 8086 will automatically do a Type 0 interrupt if the result of a division
operation is too large to fit in the destination register. For example, if we execute
DIV BL, then AX will be divided by BL. The quotient will be stored in AL and the

remainder in AH.If AX content is 4060H and BL is 02H, then the quotient is 2030H.
But the 8-bit AL register cannot hold this data. This results in automatic branching
to an ISS. It is an internal interrupt, and the 8086 branches to an ISS whose
interrupt Type number is 0.
Action taken by the 8086 when divide by zero error occurs is as follows.
1. Flag register value is pushed on to the stack.
2. CS value of the Return address and IP value of the Return address are pushed
on to the stack.
3. IP is loaded from contents of word location 0x4 = 00000H.
4. CS loaded from contents of next word location, 00002H.
5. Interrupt Flag and trap Flag are reset to 0.
The action taken by the ISS could be to display a suitable error message on the CRT
and then halt the proceedings. Or, it could be to set a bit in a memory location to
indicate an error, and then return to the interrupted program using the IRET
instruction.

Single-Step Interrupt - Type 1

When we tell a System to single- Step , it will execute one instruction and stop. We can then
examine the contents of the registers and memory locations. If they are correct, we can tell the
system to go on and execute the next instruction. In other words, when in single-Step mode, a
system will stop after it executes each instruction and wait for further directions from the user. The
8086 trap flag and type 1 interrupt make it quite easy to implement a single-Step feature. If the
8086 trap flag is set, the 8086 will automatically do a type 1 interrupt after executing each
instruction. It is an internal interrupt caused by the completion of an instruction execution. It is

useful for debugging a program. The action taken by the 8086 when T flag is set to 1, and an
instruction execution is completed is as follows.

1. Flag register values is pushed on to the stack.

2. CS value of the return address and IP value of the return address are pushed on
to the stack.
3. IP is loaded from the contents of the word location, 1x4 = 00004H.
4. CS is loaded from contents of the next word location, 00006H.
5. Interrupt Flag and trap Flag are reset to 0.
The action taken by the ISS could be to display the contents of the various registers
on the CRT and then return to the interrupted program using the IRET program.

Software interrupt Instructions

There are instructions in 8086 which cause an interrupt. They are

1. INT instructions with type number specified.

2. INT 3, Break Point Interrupt instruction.
3. INTO, Interrupt on overflow instruction.
These are instructions at the desired places in a program. When one of these
instructions is executed a branch to an ISS takes place. Because their execution
results in a branch to an ISS, they are called interrupts. Software Interrupt
instructions can be used to test the working of the various Interrupt handlers- For
example, we can execute INTO instruction to execute type 0 ISS, with out really
having to divide a number by 0. Similarly, we can execute INT 2 instruction to test
NMI ISS.

INT-Interrupt Instruction with Type number Specified

The mnemonic for this is INT. It is a 2 byte instruction. The first byte provides the
op-code and the second byte the Interrupt type number. Op-code for this
instruction is CDH.
The execution of an INT instruction, say INTN, when N is the value in the range
00H to FFH, results in the following:
1. Flag register value is pushed on to the stack.
2. CS value of the Return address and IP value of the Return address are pushed
on to the stack.
3. IP is loaded from the contents of the word location N x 4.
4. CS is loaded from the contents of the next word location.
5. Interrupt Flag and Trap Flag are reset to 0.
Thus a branch to the ISS take place. During the ISS, interrupts are disabled because
the Interrupt flag is reset to 0. At the end of the ISS, there will be an IRET
instruction. Thus a return back to the interrupted program takes place with Flag
registers unchanged.

INT 3-Break Point Interrupt Instruction

When a break point is inserted, the system executes the instructions upto the
breakpoint, and then goes to the break point procedure. Unlike the single-Step
feature which stops execution after each instruction, the breakpoint feature
executes all the instructions upto the inserted breakpoint and then stops execution.
The mnemonic for the instruction is INT3. It is a 1 byte instruction Op-code for this
is CCH.
The execution of INT3 instruction results in the following.
1. Flag register value is pushed on to the Stack.
2. CS value of the return address and IP value of the return address are pushed on
to the Stack.
3. IP is loaded from the contents of the word location 3x4 = 0000CH.
4. CS is loaded from the contents of the next word location.
5. Interrupt Flag and Trap Flag are reset to 0.
Thus a branch to the ISS takes place. During the ISS, interrupts are disabled
because Interrupt flag is reset to 0. At the end of the ISS, there will be an IRET
instruction to return back to the interrupted program. A break point interrupt
service procedure usually saves all the register contents on the Stack. Depending
upon the system, it may then send the register contents to the CRT display and wait
for the next command from the user.

INTO - Interrupt on overflow instruction

The 8086 overflow flag, OF, will be set if the signed result of an arithmetic
operation on two signed numbers is too large to be represented in the destination
register or memory location. For example, if we add the 8-bit signed number
01101100 and the 8-bit signed number 01010001, the signed result will be 10111101.
This is correct if we add unsigned binary numbers, but it is not the correct signed
result. There are two ways to detect and respond to an overflow error in a
program. One way is to put the jump if overflow instruction, JO, immediately after
the arithmetic instruction. If the overflow flag is Set, execution will jump to the
address specified in the JO instruction. At this address an error routine may be put
which respond to the overflow. The second way is to put the INTO instruction
immediately after the arithmetic instruction in the program. The mnemonic for the
instruction is INTO. It is a 1 byte instruction. The op-code for this is CEH. It is a
conditional interrupt instruction. Only if the overflow flag is Set, a branch takes
place to an interrupt handler whose interrupt type number is 4. If the overflow flag
is reset, the execution continues with the next instruction.
The execution of INTO results in the following.
1. Flag register values are pushed on to the Stack.

2. CS value of the return address and IP value of the return address and IP value of
the return address are pushed on to the stack.
3. IP is loaded from the contents of word location 4x4 = 00010H.
4. CS is loaded from the contents of next word location.
5. Interrupt flag and Trap flag are reset to 0.
Thus a branch to ISS takes place. During the ISS, interrupts are disabled. At the end
of ISS, there will be an IRET instruction, returning back to the interrupted
program. Instructions in the ISS procedure perform the desired response to the
error condition.

Priority of Interrupts
The internal interrupts which result is an error, like Divide by Zero error, as well as
software interrupt instructions have the highest priority. Next priority is NMI. The
next lower priority is assigned to INTR. The lowest priority is assigned to single
Step interrupt. In reality, NMI is always serviced on top most priority.

ADDRESSING MODES
8086 Addressing Modes
The 8086 has 12 basic addressing modes(AM) and can be classified into
5 groups
I.
II.
III.
IV.
V.

Addressing modes for accessing immediate & register data

Addressing modes for accessing data in memory
Addressing modes for accessing I/O ports
Relative Addressing modes
Implied Addressing modes

I Addressing modes for accessing Immediate & Register data

1.Register
AM
In this mode the source operand,destination operand or both are to be contained
in
the
8086
register.
eg:MOV
DX,CX
MOV CL,DL

2.Immediate
AM
In this mode a 8 or 16 bit data can be specified as part of the instruction
eg:MOV
CL,03H
MOV DX,0502H
II Addressing modes for data in memory (Memory mode)
3.Direct
AM
In this mode the 16 bit effective address (EA) is taken directly from the
displacement field of the instruction.This EA or displacement is the distance of the
memory location from the current value in the data segment (DS) register in which
the
data
are
stored.
The BIU shifts the [DS] 4 times to left & adds the EA to generate the 20 bit
physical
address.
eg:MOV
CX,START
MOV
START,BL
START can be defined as an address by using the assembler DB(Define Byte) or
DW(Define
Word)
pseudoinstructions.
Suppose
if
START=0040(16)
&
[DS]=3050(16)
then
305 0

Shift
Left

0 0 4 0 (EA)
20 bit
3 0 5 4 0 physical
address
4.Register
Indirect
AM
In this mode the EA is specified in either a pointer register or an index
register.The pointer register can be either base register(BX) or base pointer(BP)
and Index register can either be Source index(SI) or Destination index(DI) register
eg:MOV
[DI],BX
The instruction moves the 16 bit content of BX into a memory location offset by
the value of EA (EA is specified in DI) from the current contents in DS.
If
[DS]=5004(16)
[DI]=0020(16)
and
[BX]=2456(16)
then

5004

Shift
Left

0 0 2 0 (EA)
20 bit
5 0 0 6 0 physical
address
the contents of BX (2456) is moved into memory locations 50060(16) & 50061(16)
5.Based
AM
In this mode EA is obtained by adding a displacement (signed 8 bit or unsigned 16
bit) value to the contents of BX or BP.The segment registers used are DS & SS.
When Memory is accessed,the 20 bit physical address is computed from BX and
DS.On the other hand,when the stack is accessed,the 20 bit physical address is
computed from BP and SS.
eg:- MOV AL,START[BX] or MOV AL,[BX+START]
Where START=02H(8 bit displacement),BX=2000H
Now the 20 bit Physical address is computed from DS and EA
If [DS]=5004(16),then

2000H BX
02H

Displacement

2002H EA

5004
2 0 0 2 EA
5 2 0 4 0 20 bit Physical Address

Here the source operand is in based Addressing Mode.EA is obtained by adding

the value of START and [BX].The 20 bit physical address is produced from DS and
EA.The 8 bit content of this memory location is moved to AL register.
Therefore the contents of the memory location 52042 is moved in to AL register.
6.Indexed AM
In this mode,the EA is calculated by adding the unsigned 16 bit or signed extended
8 bit displacement and the contents of SI or DI.

eg:- MOV BH,START[SI]

moves the contents of the 20 bit address computed from the displacement
START,SI and DS into BH register.The 8 bit displacement is provided by the
programmer using the assembler pseudoindtruction such as EQU.For 16 bit
displacement,the EU adds this to SI to determine EA.On the other hand,for 8 bit
displacement the EU sign extends it to 16 bits and then adds to SI for determining
EA.
7.Based Indexed AM
In this mode,the EA is computed by adding a base register(BX or BP),an index
register(SI or DI),and a displacement(unsigned 16 bit or sign extended 8 bit)
eg:- MOV ALPHA[SI][BX],CL
If [BX]=0200H,[SI]=1000H,ALPHA=08H and [DS]=3000H

0200H [BX]
1000H [SI]
08H

Displacement

1208H EA

3000
1 2 0 8 EA
3 1 2 0 8 20 bit Physical address

Based Indexed AM provides a convinient way for a subroutine to address an array

allocated on a stack.
8.String AM
This mode uses index registers.The string instructions automatically assume SI to
point to the first byte or word of the source operand and DI to point to the first byte
or word of the destination operand.
The segment register for the source is DS and may be overridden.The segment
register for the destination must be ES and cannot be overridden.
The contents af SI and DI are automatically incremented by clearing DF (Direction
Flag) to 0 by CLD instruction or automatically decremented by setting DF to 1 by
STD instruction.
III Addressing Modes for accessing I/O ports

9.Direct AM
Here the port number is a 8 bit immediate operand.This allows fixed access to ports
numbered 0 to 255.
eg:- OUT 05H,AL
outputs [AL] to 8 bit port 05H
10.Indirect AM
The port number is taken from DX allowing 64K 8 bit ports or 32K 16 bit ports.
eg:- IN AX,DX
If [DX]=5040,Inputs the 8 bit content of port 5040 into AL and 5041 into AH.
IV Relative Addressing Mode
11.
In this mode,the operand is specified as a signed 8 bit displacement,relative to
PC(Program Counter).
eg:- JNC START
then,if carry=0,PC is loaded with current PC contents plus the 8 bit signed value of
START,otherwise the next instruction is executed.
V Implied Addressing Mode
12.
Instructions using this mode have no operands.
eg:- CLC
this clears the carry flag to zero.

8086 instruction set

QUESTION BANK
1. How many bits does 8086 microprocessor have?
2. What is the size of data bus in 8086?
3. What is the size of address bus in 8086?
4. What is the max memory addressing capacity of 8086?
5. Which are the basic parts of 8086?
6. What are the functions of BIU?
7. What are the functions of EU?
8. How many pin IC 8086 is?
9. What IC8086 is?
10. What is the size of instruction queue in 8086?
11. What is the size of instruction queue in 8088?
12. Which are the registers present in 8086?
13. What is pipelining in 8086?
14. How many 16 bit registers are available in 8086?
15. Specify addressing modes for any instruction?
16. What is assembler directives?
17. What .model small stands for?
18. What is the supply requirement of 8086?
19. What is the relation between 8086 processor frequency & crystal
frequency?
20. Functions of Accumulator or AX register?
21. Functions of BX register?
22. Functions of CX register?
23. Functions of DX register?
24. How Physical address is generated?
25. Which are pointers present in this 8086?
26. Which is by default pointer for CS/ES?
27. How many segments present in it?
28. What is the size of each segment?
29. Basic difference between 8085 and 8086?
30. Which operations are not available in 8085?
31. What is the difference between min mode and max mode of 8086?
32. What is the difference between near and far procedure?
33. What is the difference between Macro and procedure?
34. What is the difference between instructions RET & IRET?
35. What is the difference between instructions MUL & IMUL?
36. What is the difference between instructions DIV & IDIV?
37. What is difference between shifts and rotate instructions?
38. Which are strings related instructions?

39. Which are addressing modes and their examples in 8086?

40. What does u mean by directives?
41. What does u mean by Prefix?
42. What .model small means?
43. Difference between small, medium, tiny, huge?
44. What is dd, dw, db?
45. Interrupts in 8086 and there function.
46. What is the function of 01h of Int 21h?
47. What is the function of 02h of Int 21h?
48. What is the function of 09h of Int 21h?
49. What is the function of 0Ah of Int 21h?
50. What is the function of 4ch of Int 21h?
51. What is the reset address of 8086?
52. What is the size of flag register in 8086? Explain all.
53. What is the difference between 08H and 01H functions of INT 21H?
54. Which is faster- Reading word size data whose starting address is at even or
at odd address of memory in 8086?
55. Which are the default segment base: offset pairs?
56. Can we use SP as offset address holder with CS?
57. Which are the base registers in 8086?
58. Which is the index registers in 8086?
59. What is segment override prefix?
60. Whether micro reduces memory requirements?
61. What is macro?
62. What is diff between macro and procedure?
63. Types of procedure?
64. What TASM is?
65. What TLINK is?
66. What TD is?
67. What do u mean by assembler?
68. What do u mean by linker?
69. What do u mean by loader?
70. What do u mean by compiler?
71. What do u mean by emulator?
72. Stack related instruction?
73. .stack 100 means?
74. What is 20 dup (0)?
75. Which flags of 8086 are not present in 8085?
76. What is the size of flag register?
77. Can you perform 32 bit operation with 8086? How?
78. Whether 8086 is compatible with Pentium processor?

79. What is 8087? How it is different from 8086?

80. While accepting no. from user why u need to subtract 30 from that?
81. While displaying no. from user why u need to add 30 to that?
82. What are ASCII codes for nos. 0 to F?
83. How does U differentiate between positive and negative numbers?
84. What is range for these numbers?
85. Which no. representation system you have used?
86. What is LEA?
87. What is @data indicates in instruction- MOV ax, @data?
88. What is maximum size of the instruction in 8086?
89. Why we indicate FF as 0FF in program?
90. What is mul BX and div BX? Where result goes?
91. Where queue is present?
92. What is the advantage of using internal registers?
93. What is SI, DI and their functions?
94. Which are the pointers used in 8086 and their functions?
95. What is a type of queue in 8086?
96. What is minimum mode of 8086?
97. What is maximum mode of 8086?
98. Which are string instructions?
99. In string operations which is by default string source pointer?
100.
In string operations which is by default string destination pointer?

Appendix

How to write and assemble assembly program?

Which editor can I write my program?

In any editor, e.g. DOS editor, C editor, etc.
In the PC Lab or your own computer DOS prompt1:

Without Debug (no error in your program):

1. Enter the DOS prompt (if in Win95)
2. Go to A drive, which contain your assembly program
Or your own directory for your own computer.
3. Type TASM
<filename.ASM>2
4. Type TLINK
<filename.OBJ>
5. Execute your program by typing <filename.EXE>
With Debug:
6. Enter the DOS prompt (if in Win95)
7. Go to A drive, which contain your assembly program
Or your own directory for your own computer.
Add one more path: C:\TASM\BIN.
8. Type TASM
/zi
/la
<filename.ASM>. Check how
many errors you made.
9. Type TLINK
/v
<filename.OBJ>.
10. Type TD <filename.EXE> and enter the assembly debugger.
The debugger is similar to C debugger in DOS prompt. You can
use it to debug your program by inspecting the variables,
registers or memories, as you like.
With linking of C program:
Replace the two executions by:
1. Type "TASM
2. Type "TCC
directory>

1
2

Use the 16-bit assembler. TASM32 will not work.

You can omit the bold extension.

/zi /la /mx /o

<filename.ASM>".
/M -I<include-file directory>
-L<libraries
<filename.c>
<filename.OBJ>".

Appendix 2: Commands and syntax of Assembly

language
Segment Definition:
<Segment Name> segment (<align>) (<combine>) (<class>)
<code>
<Segment Name> ends
With:
ASSUME CS:<code segment name>, DS:<data segment name>, SS:<stack
segment name>
Program Ending:
END <entry point>
Data Segment:
Data Definition:
<variable name> DB | DW <value>
<arrayname> DB | DW
<size> dup
<stringname>
DB
<string>$

(<element>)

Code Segment:
Label Definition:
<label name> :
Procedure Definition:
<procedure name> PROC {FAR | NEAR}
:
:
;***your (main/ sub) program here***
<procedure name> ENDP
Data Movement:

MOV
MOV
XCHG
LEA

<destination>, <register | immediate>

<destination>, <DISP | [BX | BP] | [SI | DI] >
<operand1>, <operand2>
<destination>, <source>

Arithmetic Operation:
ADD {destination} , {source}
SUB {destination} , {source}
ADC {destination} , {source}
SBB {destination} , {source}
MUL {source}
IMUL {source}
DIV {source}
IDIV {<register> | <memory>}
NEG {<memory> | <register>}
INC {<memory> | <register>}
DEC {<memory> | <register>}
Program Control Flow:
JMP {<address> | <label> | <register>}
<type> PTR <expression>
CALL
<label>
RET
<immediate>
CMP
{destination}, {source}
JXX
{<address> | <label>}
LOOP
<label>

; destination source (set flags)

Logic Operation:
AND {destination}, {source}
OR
{destination}, {source}
XOR {destination}, {source}
NOT {destination}
<expression> <relational operator>
Rotation and Shifting:
SHL
SAL

{<register>, <memory>}, {1 | CL}

{<register>, <memory>}, {1 | CL}

<expression>

SAR
ROL
ROR
ROR
RCR

{<register>, <memory>}, {1 | CL}

{<register>, <memory>}, {1 | CL}
{<register>, <memory>}, {1 | CL}
{<register>, <memory>}, {1 | CL}
{<register>, <memory>}, {1 | CL}

Interrupts:
INT <special code>
IRET
CLI
STI
Stack Segment:
Stack Definition:
DW

<size of stack>

dup

(<initial value>)

Stack Manipulation:
PUSH
POP

{<register> | <memory>}
{<register> | <memory>}

Macro Definition:
<Macro name>
MACRO
(arg1,arg2,....)
: : : : : ;***your macro here***
ENDM
LOCAL
(label_1,label_2,....)
Directives:
REPT
ENDM
IRP
ENDM
IRPC

<expression>
<statements>
<<parameter>, <arguments>>
<statements>
<<parameter>, <string argument>>
<statements>

ENDM
IFXX
<ELSE>

<condition>
<sequence of statements>
;optional
<sequence of statements>

ENDIF
Calling Sequences:
EXTRN <subprogram name> : type
PUBLIC <subprogram name>
***** END of Assembly Programming *****

8086 SYSTEM DESIGN

Syllabus
8086 signals and timing
MIN/MAX mode of operation
Addressing memory and I/O
Multiprocessor configurations
System design using 8086

CLOCK, POWER SUPPLY AND INSTRUCTION CYCLE

Fig 8 shows the 8086 pin diagram. Vcc is on pin 40 and ground on pins 1 and 20.
8086 requires +5v supply. Clock input labeled CLK is on pin 19. An 8086 requires a
clock signal from some external, crystal- controlled clock generator to synchronize
internal operations in the processor. Different versions of the 8086 have maximum
clock frequencies ranging from MHz to 10 MHz.

Pins 2 through 16 and pins 35 through 39 are used for the address bus.
Pins 35 through 38 are used by multiplexing to provide information or status about
the MPU. The status signals are labeled S3, S4, S5 and S6 as shown.
The data bus lines AD0 through AD15 are used at the start of the machine cycle to
send out addresses, and later in the machine cycle they are used to send or receive
data.
The 8086 sends out a signal called address latch enable or ALE on pin 25 to let
external circuitry know that an address is on the data bus.
The upper 4 bits of an address are sent on the lines labeled A16/ S 3 through A19/
S 6. Some of the control bus lines on a microprocessor usually have mnemonics
such as RD, WR and M/ IO.
Pin 32 of the 8086 is labeled RD. A tri-state active-low output signal on pin 32
indicates that the 8086 is reading data from memory or from a port.
Pin 29 has a label WR next to it. However, pin 29 also has a label LOCK next to it,
because this pin has two functions. The function of this pin and the functions of the
pins between 24 and 31 depend on the mode in which the 8086 is operating.
The operating mode of the 8086 is determined by the logic level applied to the MN
/ MX input on pin 33. If pin 33 is asserted high, then the 8086 will function in
minimum mode, and pins 24 through 31 will have functions shown in parentheses
next to the pins in fig. 8.

If the MN / MX pin is asserted low, then the 8086 is in maximum mode. In this
mode pins 24 through 31 will have the functions described by the mnemonics next
to the pins in fig. 8.
A tri-state active-low output signal on pin 29 indicates that MPU has put valid and
stable data on the data bus.
Pin 28 will function as M / IO. The 8086 will assert this signal high if it is reading
from or writing to a memory location, and it will assert a signal low if it is reading
from or writing to a port. In the maximum mode the control bus signals (S0, S1, S2 )
are sent out in encoded form on pins 26,27 and 28.
An external bus controller device decodes these signals to produce the control bus
signals required for a system, which has two or more microprocessors sharing the
same buses.If pin 21, the RESET input is made high, the 8086 will, no matter what it
is doing, reset its DS, SS, ES, IP and flag registers to all 0s. It will set its CS register
to FF. When the RESET signal is removed from pin 21, the 8086 will then fetch its
next instruction from physical address (FFFF0H). This address is produced in the
8086 Bus Interface unit (BIU) by shifting the FFFFH in the CS register 4 bits left by
adding the 0000H in the instruction pointer to it. The first instruction that has to be
executed after a reset is put at this address FFF0H.
8086 has two interrupt inputs, non-maskable interrupt (NMI) input on pin 17 and
the interrupt (INTR) input on pin 18. An active-high on any one of these pins will
cause
the 8086 to stop execution of its current program and go execute a specified
procedure.
At the end of the procedure it can return to executing the interrupted program.
The NMI
cannot be ignored, or masked, by the MPU. The INTR (interrupt request) is
maskable and
can be made to be ignored by the MPU through software control.

A tri-state active-low output signal on pin 26 DEN (data enable) determines

whether the data buffer is enabled or disabled. A tri-state output signal on pin 27
DT / R
(data transmit receive) is used to control the direction of data flow. A logic level 1
indicates data bits are being transmitted from the MPU. A logic level 0 indicates
that data
bits are being received into the MPU.
All microprocessors use an oscillator to generate a master frequency clock to
synchronize or time operations. For the 8086 microprocessor the oscillator
frequency, or
clock frequency is typically 5 MHz. The period of one clock cycle is then equal to.
T = 1/F
= 1/5 x 106 Hz
= 0.2 x 10-6 sec.
= 200 n sec
The 8086 operates in time periods called bus cycles. Each bus cycle requires 4
clock cycles to complete. Therefore, the bus cycle is completed very 800 ns. A
typical bus
cycle is shown in fig 9.
One cycle of this is referred to as a state. A state is measured from the 50 percent
point on the falling edge of one clock pulse to 50 percent point on the falling edge
of the
next clock pulse- T1 in the figure is a state. Each basic bus operation such as reading
a

byte from memory or writing a word to a port requires some number of states. The
group

of states required for a basic bus operation is called a machine cycle. The total time
it
takes the 8086 to fetch and execute an instruction is called an instruction cycle. An
instruction cycle consists of one or more machine cycles. To summarize, an
instruction
cycle is made up of machine cycles, and a machine cycle is made up of states.
Two major bus cycles are the read bus cycle and the write bus cycle. The read bus
cycle is activated when the microprocessor is reading information from the
memory or an
I/O device. During the read bus cycle, there are normally four clock cycles T1 ,T2,
T3 and
T4. However, if the device outputting data to the MPU needs more time to send
the data,
a wait state (Tw) is initiated by placing extra clock cycles (Tws) between cycles T3
and T4.
Fetch-Execute cycle
The microprocessor has two primary functions. Fetch and execute. First it must
fetch or read the program instruction or data. This can take one or more bus cycles.
Once
it has fetched the necessary program instructions and data through the BIU, the
microprocessors next step is to execute the instructions. The EU receives the
instruction
from the instruction queue and executes it. Some instructions may take 2 clock
cycles to
execute, where as others may take as many as 100 clock cycles to execute. In older
microprocessors this left the bus idle while the MPU was executing a long
instruction, as
shown in the fig. 10. however, since the 8086 MPU is broken up into two
functional units,
the BIU and EU, it avoids much of the idle time required by older microprocessors.
It
does this by having the BIU pre fetch instructions and place them into the
instruction
queue and data registers while the EU is executing the program instructions.
Therefore,
while the bus is busy during a read cycle, the EU can be executing the previous

instructions. When the bus is busy during a write cycle, the EU can be executing
another
instruction. This greatly increases the effective speed of the entire system.

Minimum mode 8086 system

 Turns MN/MX pin to logic 1
 Control signals are given by microprocessor chip itself
 Single microprocessor with latches, transrecievers, clock generator memory
& IO devices

 Latches are used to separate valid address from address/data signals

controlled by ALE
 Transrecievers are bidirectional buffers.Also termed as data amplifiers
 Controlled by DEN or DT/R

 A minimum mode of 8086 configuration depicts a stand alone system of

computer where no other processor is connected.
 The Data transceiver block which helps the signals traveling a longer
distance to get boosted up.
 Two control signals data transmit/ receive are connected to the direction
input of transceiver (Transmitter/Receiver) and DEN* signal works as
enable for this block

In the bus timing diagram, data transmit / receive signal goes low (RECEIVE) for
Read operation. To validate the data, DEN* signal goes low. The Address/ Status
bus carries A16 to A19 address lines during BHE* (low) and for the remaining time
carries Status information. The Address/Data bus carries A0 to A15 address
information during ALE going high and for the remaining time it carries data. The
RD* line going low indicates that this is a Read operation. The curved arrows
indicate the relationship between valid data and RD* signal
The TW is Wait time needed to synchronize the fast processor with slow memory
etc. The Ready pin is checked to see whether any peripheral needs more time for
data transmission.

This is the same as Read cycle Timing Diagram except that the DT/R* line goes
high indicating it is a Data Transmission operation for the processor to memory /
peripheral. Again DEN* line goes low to validate data and WR* line goes low,
indicating a Write operation.

The HOLD and HLDA timing diagram indicates in Time Space HOLD (input)
occurs first and then the processor outputs HLDA (Hold Acknowledge).

MAXIMUM MODE

In the maximum mode of operation of 8086, wherein either a numeric

coprocessor of the type 8087 or another processor is interfaced with 8086.

The Memory, Address Bus, Data Buses are shared resources between the
two processors.

The control signals for Maximum mode of operation are generated by the
Bus Controller chip 8788.

The three status outputs S0*, S1*, S2* from the processor are input to
8788.

The outputs of the bus controller are the Control Signals, namely DEN,
DT/R*, IORC*, IOWTC*, MWTC*, MRDC*, ALE etc.

These control signals perform the same task as the minimum mode
operation. However the DEN is an active HIGH signal which has to be
converted to active LOW by means of an inverter.

Here MRDC* signal is used instead of RD* as in case of Minimum Mode S0* to
S2* are active and are used to generate control signal.

Here the maximum mode write signals are shown. Please note that the T states
correspond to the time during which DEN* is LOW, WRITE Control goes LOW,
DT/R* is HIGH and data output in available from the processor on the data bus.

Request / Grant pin may appear that both signals are active low. But in reality,
Request signal goes low first (input to processor), and then the processor grants
the request by outputting a low on the same pin.

ADDRESSING MEMORY AND i/o

BUS CONCEPT, DATA BUS, ADDRESS BUS, CONTROL
BUS
A Bus is a group of common wires in which signals travel. The three types of buses
used are the Address Bus, the Data Bus and the control Bus.

Address Bus
 An address is a unique location in memory. It is like a mailbox in the post
office,
 where each mail box has its own unique number to identify its location.
 An address bus consists of 16,20,24 or more parallel signal lines. On these
lines the CPU sends out the addresses of the memory location that is to be
written to or read from.
 In the 8086 theaddress is determined by a 20-bit number.
 This gives us 220 possible address locations, or1,048,576 bytes of memory.
An address bus is made up of 20 wires, or conductors, labeled A0 through A19 ,
with A0 as the LSB and A19 as the MSB. It is used to locate or find information in

memory. It is also used to define a location in memory where information is to be

stored.
The address bus is some times used to identify which I/O port is used for
input/output
operations.

Data Bus
A data bus is used to move information ( data and instruction ) from the MPU to
memory and other devices. This is referred to as a write operation. The data bus is
also
used to receive information into the MPU. This is called as a read operation.
Because the
data bus receives and transmits information, it is known as a bi-directional bus.
However,
it cannot receive and transmit data at the same time.
The Intel 8086 has a 16-bit data bus labeled D0 to D15, where D0 is the LSB and
D15 is the MSB. The 8086 microprocessor multiplex the address and data buses.
Multiplexing is the process of using the same wires or pins to do different things at
different times. When acting as a data bus, the signal lines carry read/write
information for
memory or input/output information for I/O devices. When acting as an address
bus, the
same signal lines are used to locate information.

Control Bus
22
The CPU sends out signals on the control bus to enable the outputs of addressed
memory devices or port devices. The control line determines the sequence of
operations to
be performed. The control bus consists of 4 to 10 parallel signal lines. Typical
control bus
signals are memory read, memory write, I/O read, and I/O write. To read a byte of
data

from a memory location, for example, the CPU sends out the address of the desired
byte
on the address byte and then sends out a memory read signal on the control bus.
The
memory read signal enables the addressed memory device to output the byte of
data on to
the data bus where it is required by the CPU.
23

Chapter 5

RAM & ROM, ADDRESSING MODES & CONTEXT

SWITCHING
Memory
A memory stores large number of binary words. Since the early 1970s, ICs or semi
conductor memory have been the most widely used type of primary memory found
in
micro computers. The simplest form of computer memory is the basic flip-flop and
a flipflop
is called a memory cell which can be used store a single bit ( 0 or 1). 8 or 16 cells are
connected together to form a memory byte or memory word. Each memory byte or
word
has a unique location in the memory called an address. Therefore, memory is a
place
where data bits ( 0 or 1) can be stored and then later retrieved when the computer
needs
it. The process of storing data into the memory is called writing. The process of
retrieving
data from the memory is called reading. Accordingly, we say that a microprocessor
is in a
write cycle or performing a write operation when it is storing data into memory.
The
process by which a microprocessor retrieves data from memory is called a read
cycle or

read operation.

Memory classification
Memory can be classified into three general types, ROM and RAM. ROM stands
for read- only memory. ROM generally contains permanently stored data that
cannot be
changed. It can be read but not written into. The main feature of ROMs is that they
are
non-volatile, which means that the information stored in them is not lost when the
power
is removed.
RAM, on the other hand, is memory that can be read from or written to. RAM
stands for random-access memory, but since ROMs are also random access, the
major
difference is that RAM is memory that can be read or written to. RAM is actually
read/write memory. RAM memory is volatile memory, that is, it is lost whenever
the
power is switched off.

ROM
ROMs can be classified into three general types. A maskable ROM is a ROM that
is programmed with information or data by the manufacturer. Once programmed
these
data bits cannot be altered or changed. A programmable ROM, or PROM, is a
device that
can be programmed by a user. Once programmed, the data in a PROM, like a
ROM,
cannot be altered or changed . An erasable PROM, or EPROM, is a type of ROM
that

24
can be programmed by an user but whose data may be erased or changed with use
of
specialized equipment.
A summary of the different types of ROMs is given below:

Mask-programmed ROM -Programmed during manufacture; cannot be

changed.
PROM- user programs by blowing fuses; cannot be erased except to
blow additional fuses.
EPROM- Electrically programmable by the user; erased by passing
ultra violet light through a quartz window in the package.
EEPROM-Electrically programmable by the user; erased with electrical
signals instead of ultra violet light.

RAM
RAM or read/write memory, is a type of volatile memory from which data can be
read and into which data can be written. RAM can be classified as either Static or
dynamic. A Static RAM is essentially a matrix of flip-flops. Therefore, we can write
a new
data word in a RAM location at any time by applying the word to the flip-flop data
input
and clocking the flip-flops. The stored data word will remain on the flip-flop
outputs as
long as the power is left on. This type of memory is volatile because data is lost
when the
power is turned off. These types of storage device is called static RAM. In dynamic
RAMs, binary 1s and 0s are stored as an electrical charge or no charge on a tiny
capacitor.
The internal capacitance of a MOSFET is great enough to make it appear that a
small
capacitor (a few pico-farads ) exists in the MOSFET. Each memory cell is
essentially a
single MOSFET. A logic 1 or a charged capacitor must be refreshed, or recharged,
at least
once every 2 ms, or the capacitor will lose its charge and the data.

Addressing Modes
The different ways that a processor can access data are referred to as its
addressing modes. It is the way by which the location of the operand is determined.
How

an operand is addressed in a program depends on the types and location of the

data.
There are three general types of addressing modes:
Immediate addressing modes.
Register addressing modes.
25
Memory addressing modes.

Immediate Addressing mode

Suppose that in a program we need to put the number 526AH in the CX register.
The MOV CX, 526AH instruction can be used to do this. This instruction will put
the
immediate hexadecimal number 526AH in the 16- bit CX register. This is referred to
as
immediate addressing mode because the number to be loaded into the CX register
will be
put in two memory locations immediately following the code for the MOV
instruction.
A similar instruction, MOV CL, 48H could be used to load the 8-bit immediate
number 48H into the 8-bit CL register. It is also possible to write instructions to
load an 8bit immediate number into an 8-bit memory location or to load a 16-bit number
into two
consecutive memory locations.

Register Addressing mode

Register is the source of an operand for an instruction in Register Addressing
mode. For example, the instruction MOV CX, AX copies the contents of the 16-bit
AX
register into the 16-bit CX register. Destination register is specified in the
instruction
before the source. When it executes, the contents of AX are just copied to CX, not
actually moved. In other words, the previous contents of CX are written over, but
the

contents of AX are not changed. For example, if CX contains 2A84H and AX

contains
4971H before the execution, then after the execution of the instruction CX will
contain
4971H and AX will still contain 4971H. The contents of any 16-bit register can be
moved
into any 16-bit register, or the contents of any 8-bit register can be moved into any
8-bit
register. However, an instruction of the type MOV CX, AL cannot be used because
this is
an attempt to copy a byte- type operand (AL) into a word type destination (CX). A
byte in
AL would fit in CX, but the 8086 would not know which half of CX to put it in. But
if the
byte from AL is to be copied into the high byte of CX, the instruction MOV CH, AL
could
execute it. The instruction MOV CL, AL will copy the byte from AL to CL, the low
byte
of CX.

Memory Addressing Modes

To access data in memory the 8086 must produce a 20-bit physical address. It is
done by adding a 16-bit value called the effective address to one of the four
segment
bases. This effective address (EA) represents the displacement or offset of the
desired
operand from the segment base. Any of the segment bases can be specified, but
the data

26
segment is the one most often used. Fig 11(a) shows a graphic form how EA is
added to
the data segment base to point an operand in the memory. The fig 11(b) shows how
the
20-bit physical address is generated by the BIU. The starting address for the data
segment

in fig 10 (b) is 2000H so that the data segment register will contain 2000 H. The
BIU
shifts the 2000 H four bit positions left and adds the effective address, 437AH, to
the
result. The 20-bit physical address sent out to memory by the BIU will then be
2437AH.
The physical address can be represented either as a single number, 2437AH, or in
the
segment base; offset form as 2000 : 437AH

Direct Addressing Mode

For the simplest memory addressing mode the effective address is just an 8-bit or
16-bit number written directly in the instruction. The instruction MOV CL
,[437AH] is an

example. The brackets around the 437AH are shorthand for the contents of the
memory
location at a displacement from the segment base of. When executed, this
instruction will
copy the contents of the memory location, at a displacement of 437AH from the
data
segment base into the CL register. The actual 20-bit physical memory address will
be
produced by shifting the data segment base in DS four bits left and adding the
effective

27
address 437AH to the result. Fig 10(b) shows how the operation is done. This
addressing
mode is called direct because the displacement of the operand from the segment
base is
specified directly in the instruction.
Another example of this addressing mode is the instruction MOV BX, [437AH].
When executed, this instruction copies a word from memory into BX register.
Since each
memory address of the 8086 represents a byte of storage, the word must come
from two
memory locations. The byte at a displacement of 437AH from the data segment
base will
be copied into BL. The contents of the next higher address, displacement 437BH
will be
copied into BH register. The 8086 will automatically access the required number of
bytes
in memory for a given instruction.
The previous examples showed how the direct addressing mode can be used to
specify the source of an operand. It can also be used to specify the destination of an
operand. The instruction MOV[437AH], BX for example will copy the contents of
the
BX register to two memory locations in the data segment. The contents of BL will
be

copied to the memory location as a displacement of 437AH and the contents of BH

will be
copied to the memory location at a displacement of 437BH.

Indirect Addressing mode

In the direct addressing mode, either the source or the destination operand is a
specific memory location defined by the address number or a label. For example, in
the
instruction MOV AX, MEM 1 the contents of the memory address labeled MEM 1 is
copied or moved into AX register.
In the indirect addressing mode, the memory address is not directly given. A
register is used to indicate the address where the data can be found. Therefore ,
the
register acts as an indirect address to locate the data. For example, in the
instruction
MOV (BX), CX the source of data is the CX register. The destination where the
data are
to be placed or copied to, is the address pointed to by the BX register. The brackets
()
around BX indicate that the BX register contains an address and not a numeric
value.

Segmentation
Intel has designed the 8086 family devices to use memory segmentation. By
working with only 64 K bytes segments of memory at a time, the 8086 only has to
work
with 16-bit effective addresses to access any location in the segment. In other
words,
because of the segmentation scheme the 8086 has to manipulate and store 16-bit
address

28
components. Also, in a time-share microcomputer system several users share a
CPU. The

CPU works on one users program for perhaps 20 milliseconds. After working for
20 m
sec on one users program, it then works on the next users program for 20
milliseconds.
After working for 20 milliseconds for each of the other users, the CPU comes back
to
working on the first users program again. Each time the CPU switches from one
users
program to the next it must access a new section of code and sections of data.
Segmentation makes this switching quite easy. Each users program can be
assigned a
separate set of logical segments for its code and data. The users program will
contain
offsets or displacements from these segment bases to change from one users
program to a
second users program all that has to be done is to reload the four segment
registers with
the segment base address assigned to the second users program. In other words,
segmentation makes it easy to keep users programs and data separate from each
other,
and segmentation makes it easy to switch from one users program to another
users
program.

I/O CONCEPT ( I/O MAPPED AND

MEMORY MAPPED)
The I/O Sub System
The I/O Sub System is responsible for the movement of data between the basic
microcomputer system and the peripheral or external devices connected to it. It
performs
the same functions as a seaport or airport for a city. Data bits are moved in and out
of the
I/O Sub System in the same way as people and goods are moved in and out of the
seaport
or airport. The I/O sub system exchanges data with peripheral devices through
interface
circuitry known as ports. The peripheral device is physically connected to the port.
The
port is physically connected to the control circuitry as shown in fig 13. The port will
then became a path way for data as it is transferred between the microprocessor
and its peripherals.
There are two types of I/O ports; parallel and serial. Parallel port is the easiest to
implement as the microprocessor works with data in 8- or 16- bit groups. All bits
comprising the data word are input and output together in parallel.

A serial I/O port is quite different. The data bits are lined up and transmitted in
single file fashion one bit at a time. This technique will be slower than parallel port
design.
Regardless of the I/O port design- parallel or serial- the microprocessor must be
synchronized to the speed of the peripheral. Some peripherals like printers and
plotters,

cannot accept data as the microprocessor would like to output it. On the other hand
floppy- disk drives and Winchester disks may require data faster than the processor
can
supply it.
The major types of I/O operations are;
Parallel I/O.
Serial I/O.
Programmed I/O.
Interrupt-Driven I/O.
Direct Memory Access.

Parallel I/O
The hardware requirements for a Parallel I/O port are similar to those of a RAM or

ROM interface. When the CPU performs an output instruction (I/O write cycle)
the data
on the bus must be stored by the port. When an input instruction ( I/O read cycle)
is
executed, the I/O port must gate its data on to the data bus lines. Just as each
memory
location has its own (memory) address, each I/O port has its own ( port) address.
The 8086 has two I/O instructions IN AL ( or AX),port and OUT port, AL (or
AX). There are two forms each of the instruction. In the direct form, IN AL (or AX)
port
or OUT port, AL ( or AX), the I/O port address is supplied within the instruction
and
restricts the access to ports with adds between 0 and 255. The indirect Form, IN AL
( or
AX), DX and OUT DX, AL ( or AX) uses register DX to hold the port address. This
allows access to the full range of I/O ports from 0 to 65,535.
The advantage of the indirect form is that an I/O procedure can be setup and
shared between several peripherals by passing the port address ( in register DX) to
the
procedure.
The address bus carries the port address on A0-A7 for direct I/O cycles, and A0 A15 for indirect I/O cycles. The D0-D7 data bus lines are used to transfer data form
evenaddressed
ports, and D8-D15 are used for odd-addressed ports. The BHE and A0 are used to
identify the type of transfer.
In the minimum mode, the condition M/I/O =0 is used to identify the current bus
cycle as an I/O operation. RD and WR then indicate the direction of data flow.
In the maximum mode the 8288 bus controller provides separate I/O read and
write
commands.
Table 2 indicates the two forms of each instruction.
39

Table 2 8086 I/O INSTRUCTIONS

Memory- Mapped I/O

The address space of the 8086 is divided into 1,048,576 bytes of memory space
and 65,536 bytes of I/O space. These two registers do not overlap because
memory
addresses are selected with the memory commands (MEMR, MRDC, MEMW,
MWTC),
while the I/O addresses are selected with the I/O commands (IOR, IORC, IOW,
IOWC).
But consider designing a one byte read/write memory. we would use latches to
store the data during a memory write cycle, and tri-state gates to drive the bus
during a
memory read cycle- exactly the same hardware that we would use for an output or
input
port.
This is the essence of memory-mapped I/O. In hardware it appears to be a
conventional I/O port. But because it is mapped to a memory address, it is
accessible in

software using any of the memory read or write instructions. For example, the
instruction
MOV BH, MEMBDS becomes an input instruction ( input the data at port
MEMBDS
to register BH). Indirect I/O is also possible. The instruction sequence.
LEA SI, MEMWDS : Point SI at the port
MOV (S.I), CX : output CX to port
allows CX to be output to the 16-bit port at address DS:MEMWDS.

40
The advantage of memory- mapped I/O is the large number of instructions and
addressing modes available for refreshing memory. This is compared to the single
input
and output commands available with an I/O mapped port.

Serial I/O
The two basic methods used for serial data transmission and reception are
Asynchronous and Synchronous serial communication.

Asynchronous serial communication

One of the most common applications for a serial I/O port is to interface the
keyboard on a Video display terminal(VDT). In this circuit each key stroke
generates a 7bit ASCII code which is converted to a bit-by-bit serial and then transmitted to a

computer over a two-or three- conductor cable. Because, even the fastest typist
cannot
exceed data rates of 60 to 100 words per minute, it is a good match for the slow
transmission rate of the serial port. At some times the serial port will be required to
transfer data at 10 to 20 characters/S, but at other times the data rate may be only 1
to 2
characters/S. Most of the time the key board is not in use and the data rate is zero.
Because of this erratic data rate, an asynchronous communications protocol must
be
established.
The accepted technique for asynchronous serial communication is to hold the
serial output line to a logic 1 level until data is to be transmitted. Each character is
required to begin with a logic 0 for one bit time. The first bit is called the start bit
and is
used to synchronize the transmitter and receiver. The data is sent least significant
bit first
and framed between a start bit (always a 0) and one or two stop bits ( always a 1).
The
start and stop bits carry no information but are required because of the
asynchronous
nature of the data. Fig. 14 illustrates how the data byte 7BH would look when
transmitted
in the asynchronous serial format.

41
Writing a program compatible with all the different asynchronous communication
protocols can be a difficult task. It is also an inefficient use of the microprocessor, as
much
of its time will be spent in timing loops waiting to transmit or receive another
character.
Because of this, the semiconductor companies have developed the universal,
Asynchronous Receiver/Transmitter (UART)
It is interesting to note that to the microprocessor a serial port (the UART)
appears as a conventional parallel port. When the transmitter buffer is empty, all
the bits in

the word to be transmitted are output to the port at once ( in parallel) similarly, all
bits of
the received word are input at once when the received data is ready.
The job of converting the data from serial to parallel, or parallel to serial, has been
transferred to the UART.

Synchronous Serial communication

The start and stop bits of asynchronous serial data represent wasted overhead
bytes that reduce the overall character rate. Even adding a parity bit can reduce the
transfer rate by 10%. But giving up the start and stop bits will require some means
of
synchronizing the data. The two common synchronous serial protocols that are
used for
Synchronizing the data are the Bisync Protocol and Serial Data Link Control
(SDLC).

Bisync Protocol
Because there is no start bit, a special Sync, character is required to all
synchronous serial formats. This character tells the receives that data is about to
follow.
The USART ( Universal Synchronous/Asynchronous Receiver/Transmitter),
accordingly,
must have a special hunt or search mode so that the Sync. Character can be
found.

42
In Bisync protocol several special characters are used to control the data transfer.
Fig 15 illustrates one frame of a Synchronous message.
In fig. 15 two sync. Characters are output followed by STX- start of text, ETX
signifies end of text BCC is a block check character used for error detector. Pad is
the
character output when no data is being transmitted and corresponds to the mark
output
in asynchronous serial.

Serial Data Link Control (SDLC)

This format was developed by IBM for use with their Systems Network
Architecture (SNA) communications package. Fig. 16 illustrates one frame of data
using
this protocol. It is similar to bisync but it is not byte oriented.

The SDLC receiver searches for the beginning flag (01111110) as its sync
character. An 8-bit address field follows, allowing each frame to be addressed to a
particular station among a network of stations. Control characters are identified by
a
sequence of six or more logic 1s. The information field may be of any format. The
transmitter will automatically insert 0s in this field if five or more log 1s should
appear in
sequence. This will avoid inadvertent control characters appearing in the
information
field. The receiver automatically deletes these 0s. The 16-bit frame check is used
for error
detection. The frame ends with the ending flag.

Programmed I/O
43
Program instructions are controlling the transfer of data during the IN and OUT

operations. The software therefore initiates, as well as, controls the process of data
transfer. The hardwares responsibilities are confined to merely performing the
necessary
operations. The appropriate device is first checked in the device interface to
determine
whether it is ready. Device readiness must be tested because the CPU is much
faster than
peripheral devices. The test is followed by a conditional skip instruction. If the
ready flag
is 1 (device ready), the program proceeds to the next step. If the Ready Flag is 0,
the
program loops back to the test instruction. The CPU, therefore, waits for a slow
device by
continually testing the readiness of the device, until it reports ready. When the I/O
device
is ready, the data transfer operation takes place. Immediately after the transfer of
one
character, the CPU reset the ready Flag to 0. The device then sets the Flag back to
1,
when it is again ready to receive the data.
Programmed data transfer has the advantage that it allows simple hardware
interfaces, because most of the management of the I/O operations is performed by
software. The disadvantage of this technique is that valuable CPU time is wasted
while
the CPU waits for the peripheral device to get ready.

Interrupt Driven I/O

When interfacing a peripheral to a microprocessor, the microprocessor is not
knowing when the peripheral is ready. That is, the peripheral operates
asynchronously with
respect to the microprocessor. One solution is to programme the CPU to
repeatedly check
the peripherals READY flag. However, this has a built-in disadvantage in that all
the

resources of the processor are devoted to waiting for this flag. No other task can be
performed. If the peripheral is READY once in every 10,000 sec, the CPU will
spend
most of its time idling. A more logical approach would be to have the peripheral
tell the
CPU when it is ready. This is the purpose of the microprocessors interrupt input.
An
interrupt is used to cause a temporary halt in the execution of a program. The
microprocessor responds to the interrupt with an Interrupt Service Sub-routine
(ISS)
which is a short programme or a subroutine that instructs the microprocessor on
how to
handle the interrupt.
Fig. 17 diagrams the CPUs response to an interrupt. During time 1 the processor
is assumed to be executing its main task. At time 2 the peripherals READY flag
causes an
interrupt to occur. After finishing the current instruction at time 3, the CS, IP and
flag

44
registers are pushed on to the stack at time 4. Control then transfers to the ISS at
time 5.
During time 6, the ISS is executed, terminating with the instruction IRET (interrupt
return). The CS, IP and flag registers are recovered from the stack during time 7
and the
original task is resumed at time 8.
If we assume that 100 s is required to respond to the interrupt and supply the
peripheral with data, then in the case of a 10,000 s per character printer, 9900 s
will be
available to the processor for its main task.

The 8086 has two interrupt pins labeled INTER and NM1. NM1 is a nonmaskable
interrupt, which means that it requires an immediate response from the processor
and it
cannot be blocked. INTR is maskable via the IF flag. Only when this flag is set will
interrupts on this input be accepted. Interrupts can be generated by both hardware
and
software. Interrupts are also prioritized to allow for the case when more than one
interfere
Because the NMI input is nonmaskable, care must be taken when using this
interrupt. This is because there may be some programs which we do not want to
interruptreading
or writing data to a disk drive, for example. For this reason, NMI input is
normally reserved for catastrophic events like memory error or impending power
failure.

Direct Memory Access

DMA is a type of I/O technique in which data can be transferred between the
micro computer memory and an external device without utilising the
microprocessor. The
DMA is typically used to transfer blocks of data between the memory Subsystem
and an
external device . A DMA write operation transfers data from an external device to
memory.

45
Since the main purpose of DMA operation is to transfer data between external
devices and memory without involving the MPU, another device is required. This
device is
called a DMA controller. The DMA controller must be capable of performing read
and
write operations in the same manner as the MPU. Therefore, the DMA controller
is
actually a special- purpose microprocessor whose only task is to perform highspeed data
transfer between memory and an external device. The major difference between
an I/O
program controlled transfer and DMA is that data transfer does not employ the
registers
of the CPU.
The primary advantage of the DMA data transfer technique is that it provides an
efficient transfer of large amount of data between storage devices and the main
memory
without involving the CPU.
Several DMA transfer combinations are possible.
1. Memory to peripheral.
2. Peripheral to memory.
3. Memory to memory.
4. Peripheral to peripheral
DMA request takes precedence over all other bus activities, including interrupts. In
fact, no interrupt- maskable or non-maskable- will be recognised during a DMA
operation.