8086 MICROPROCESSOR ARCHITECTURE:

1. D r a w & E x p l a i n Vo n - n e u m a n n a r c h i t e c t u r e o f 8 0 8 6
microprocessor
2. Draw & explain architecture of 8086 microprocessor
3. Draw & explain block diagram of 8086 microprocessor
4. Draw & Explain BIU & EU –functional unit of 8086
microprocessor.
5. Explain different types of register used in 8086 microprocessor.
6. Describe flag registers.
7. Describe segment registers .
8. What is instruction pointer & stack pointer registers ?What is
size of instruction pointer & stack pointer registers?
9. Describe Pointer & Index Registers (General and Index registers)
10. What is pipelining concept? What is Instruction queue?
11. Explain Programming model of 8086 microprocessor.
Features of 8086 Microprocessor
1. Intel 8086 was launched in 1978.
2. It was the first 16-bit microprocessor.
3. This microprocessor had major improvement over
the execution speed of 8085.
4. It is available as 40-pin Dual-Inline-Package (DIP).
5. It is available in three versions:
a. 8086 (5 MHz)
b. 8086 (8 MHz)
c. 8086 (10 MHz)
6. It consists of 29,000 transistors.
7. It had Multiply and Divide instructions.
 Data Structure
• For multiple-byte data items stored in memory, need to
specify which order:

• Most Significant byte at lowest address ("Big Endian"), OR

• Least Significant byte at lowest address ("Little Endian")
• 8086 has a little Endian data structure
 Block Diagram of Intel
8086
The 8086 CPU is divided into two functional
units:

1. Bus Interface Unit (BIU)

2. Execution Unit (EU)
Internal (Block Diagram) Architecture of
8086 CPU

Fig. 1: Block Diagram of Intel

 Bus Interface Unit (BIU)
The BIU provides hardware functions. Including generation of the
memory and I/0 addresses for the transfer of data between itself
and the outside world.
Fetch the instruction or data from memory.
Write the data to memory.
BIU takes care of all data and addresses transfers on the buses for
the EU like sending addresses, fetching instructions from the
memory, reading data from the ports and the memory as well as
writing data to the ports and the memory. EU has no direction
connection with System Buses so this is possible with the BIU. EU
and BIU are connected with the Internal Bus.
 Bus Interface Unit (BIU)
• It has the following functional parts −
• Instruction queue
• Pipelining
• Segment register
• Instruction pointer
Instruction Queue & Pipelining
To increase the execution speed, BIU fetches as many as
six instruction bytes ahead to time from memory.

All six bytes are then held in first in first out 6 byte
register called instruction queue.

Then all bytes have to be given to EU one by one.

This pre fetching operation of BIU may be in parallel with

execution operation of EU, which improves the speed
execution of the instruction.

Fetching the next instruction while the current instruction

executes is called pipelining.
Instruction Queue & Pipelining (Fetch
and Execute cycle)
• The BIU outputs the contents of the instruction pointer

register (IP) onto the Address bus, causing the selected byte
or word in memory to be read into the BIU.

• Register IP is incremented by one to prepare for the next

instruction fetch.

• Once inside the BIU, the instruction is passed to the queue:

a first-in/first-out storage register sometimes likened to a

pipeline.

• Assuming that the queue is initially empty, the EU

immediately draws this instruction from the queue and

begins execution.
 Instruction Queue & Pipelining
(Fetch and Execute cycle)
• While the EU is executing this instruction, the BIU

proceeds to fetch a new instruction. Depending on the

execution time of the first instruction, the BIU may fill
the queue with several new instructions before the EU
is ready to draw its next instruction.

• The cycle continues, with the BIU filling the queue

with instructions and the EU fetching and executing

these instructions.
Instruction Queue & Pipelining
(Fetch and Execute cycle)
 Execution Unit (EU)
The functions of execution unit are:

Execution unit gives instructions to BIU stating from where to

fetch the data

To decode the instructions.

To execute the instructions.

EU receives the program instruction codes and data from

the BIU, executes these instructions and store the result
in general purpose registers. By passing the data back to
the BIU data can be stored in a memory location or
written to an output device.

It receives and outputs all its data through BIU.

 Programming model of 8086
• The programming model for a microprocessor shows

the various internal registers that are accessible to the

programmer. The Following Figure is a model for the
8086.Ingeneral, each register has a special function.
 Registers
• General Purpose Registers:
• There are 8 general purpose registers, i.e., AH, AL, BH, BL, CH, CL,
DH, and DL. These registers can be used individually to store 8-bit
data and can be used in pairs to store 16bit data. The valid
register pairs are AH and AL, BH and BL, CH and CL, and DH and
DL. It is referred to the AX, BX, CX, and DX respectively.
• AX register − It is also known as accumulator register. It is used
to store operands for arithmetic operations.
• BX register − It is used as a base register. It is used to store the
starting base address of the memory area within the data
segment.
• CX register − It is referred to as counter. It is used in loop
instruction to store the loop counter.
• DX register − This register is used to hold I/O port address for I/O
instruction.
 Registers
• Pointer Group Registers:
• The pointer and index group are all 16 bit registers.
These registers are used as memory pointers.
• Instruction pointer
• Register IP is included into memory pointer but this
re g i s t e r h a s o n l y o n e f u n c t i o n t o p o i n t t h e n ex t
instruction to be fetched to the BIU.
• It is a 16-bit register used to hold the address of
the next instruction to be executed.
• Stack pointer register
• It is a 16-bit register, which holds the address from the
start of the segment to the memory location, where a
word was most recently stored on the stack.
 Segment Registers
• Segment Register

•M o s t o f t h e re g i s t e r s c o n t a i n

data/instruction offsets within 64 KB

memory segment. There are four
different 64 KB segments for
instructions, stack, data and extra
data. To specify where in 1 MB of
processor memory these 4
segments are located the processor
uses four segment registers:
 CONT…
1. Code Segment (CS): is a 16-bit register containing
address of 64 KB segment with processor instructions.

• The processor uses CS segment for all accesses to

instructions referenced by instruction pointer (IP) register.

• CS register cannot be changed directly.

• The CS register is automatically updated during far jump,

far call and far return instructions.

 CONT…
• 2. Stack segment (SS) is a 16-bit register containing

address of 64KB segment with program stack.

• By default, the proc e ssor a ssu m e s t h a t a ll da t a

referenced by the stack pointer (SP) and base pointer

(BP) registers is located in the stack segment.

• S S re g i s t e r c a n b e c h a n g e d d i re c t l y u s i n g P O P

instruction.
 CONT…
3. Data segment (DS) is a 16-bit register containing
address of 64KB segment with program data.

• By default, the proc e ssor a ssu m e s t h a t a ll da t a

referenced by general registers (AX, BX, CX, DX) and

index register (SI, DI) is located in the data segment.
DS register can be changed directly using POP and LDS
instructions.
 CONT…
4 . E x t r a s e g m e n t ( E S ) i s a 1 6 - b i t re g i s t e r
containing address of 64KB segment, usually with
program data.

• By default, the processor assumes that the DI

register references the ES segment in string

manipulation instructions. ES register can be
changed directly using POP and LES instructions.

• It is possible to change default segments used by

general and index registers by prefixing

General and Index registers
• The following registers are both general and index registers:
• Stack Pointer (SP) is a 16-bit register pointing to program
stack.
• Base Pointer (BP) is a 16-bit register pointing to data in stack
segment. BP register is usually used for based, based indexed
or register indirect addressing.
• Source Index (SI) is a 16-bit register. SI is used for indexed,
based indexed and register indirect addressing, as well as a
source data address in string manipulation instructions.
• Destination Index (DI) is a 16-bit register. DI is used for
indexed, based indexed and register indirect addressing, as well
as a destination data address in string manipulation
instructions.
 23

Flag Registers of 8086

Flag register in EU is of 16-bit and is shown in fig. :

Flags Register determines the current state of the

processor. They are modified automatically by CPU
a ft e r m a t h e m a t i c a l o p e r a t i o n s , t h i s a l l o w s t o
determine the type of the result, and to determine
conditions to transfer control to other parts of the
program.
 CONT…
8086 has 9 flags and they are divided into two
categories:

• 1. Conditional Flags
• 2. Control Flags
 25

Conditional Flags
 Conditional flags represent result of last arithmetic or

logical instruction executed. Conditional flags are as

follows:
 Carry Flag (CF)

 Auxiliary Flag (AF)

 Parity Flag (PF)

 Zero Flag (ZF)

 Sign Flag (SF)

 Overflow Flag (OF)

 26

Conditional flag
• Carry Flag (CF) - this flag is set to 1 when there is an
carry out from MSB.
• Parity Flag (PF) - this flag is set to 1 when there is
even number of one bits in result, and to 0 when there
is odd number of one bits.
• Auxiliary Flag (AF) - set to 1 when there is a carry
from low nibble to upper nibble(4 bits).
• Zero Flag (ZF) - set to 1 when result is zero. For non-
zero result this flag is set to 0.
• Sign Flag (SF) - set to 1 when result is negative.
When result is positive it is set to 0. (This flag takes
the value of the most significant bit.)
• Overflow Flag (OF):Used for signed arithmetic
operations.
 27

Control Flags
 Control flags are set or reset deliberately to
control the operations of the execution unit.
Control flags are as follows:
1. Trap Flag (TP):
2. Interrupt Flag (IF):
3. Direction Flag (DF):
 28

Control Flags
• Trap Flag (TF) - Used for on-chip debugging.

• Interrupt enable Flag (IF) - when this flag is set to 1

CPU reacts to interrupts from external devices.

• Direction Flag (DF) –Causing the string instruction to

auto decrement the index register when set and Clearing

DF causes the Auto increment.