Unit - Iii Instruction Set of 8086 Microprocessor: (16 - Marks)

I – Scheme Microprocessors (22415) SEM IV
UNIT – III
INSTRUCTION SET OF 8086
MICROPROCESSOR
(16 – Marks)
Machine Language Instruction Format: -

1) A machine language instruction format has one or more number of fields
associated with it.
2) The first field is called as Operation Code Field or Opcode Field, which
indicates the type of the operation to be performed by the CPU.
3) The instruction format also contains other fields known as Operand Fields. The
CPU executes the instructions using the information which reside in these fields.
4) The standard assembly language statement format having four fields as follows
–
a) Label Field.
b) Opcode Field.
c) Operand Field.
d) Comment Field.
5) The example of standard assembly language statement is as follows –
NEXT: ADD AL , ; Add the contents of AL & BL register

BL
Label Opcode Destination Source Comment

Field Field Operand Field Field
Let us see these fields in details.
a) Label Field: -
1) The first field is the label field. A label is a symbol or group of symbols used to
represent an address which is not specifically known at the time the statement is
written.
Prof. Ratna S. Patil Page No. 1

2) Labels are usually followed by colons. They are used only if required
(Optional).
b) Opcode Field: -
1) The second field is the opcode field. It contains the mnemonic that represents
the instructions or the type of operation to be performed.
2) Mnemonics are hence called operation code or opcode. It is compulsory field.
For e.g.: - ADD mnemonic indicates addition operation.
c) Operand Field: -
1) The third field is the operand field. It contains data, the memory address, the
port address or the name of the register on which the operation is to be
performed.
2) Operand refers to the data items acted upon by an instruction.
3) Operands may be specified in an instruction implicitly or explicitly, and hence
they are called as implicit operand or explicit operand.
4) If there are two operands, then one operand is called as source operand (right
hand side operand), and the other is called as destination operand (left hand side
operand).
For e.g.: - ADD AL,BL
5) In above example, there are two operands AL and BL, which are the name of
registers. BL is source operand whereas AL is the destination operand.
6) The instruction in an example adds the contents of AL and BL registers, and by
the INTEL convention, the result is stored in the register or memory location
(address) specified before the comma (destination operand) in the operand field,
i.e. in above example, the result is stored in AL register.
d) Comment Field: -
1) The fourth field is the comment field. The comment field starts with a
semicolon and is the optional field.

2) Comments do not form the part of the machine language program.

3) Comments are included in the program to indicate the significance of the
instruction.
There are six general formats of instructions in 8086 instruction set. The length
of an instruction may vary from one byte to six bytes. These instruction formats
are as follows -
1) One Byte Instruction.
2) Register to Register.
3) Register to / from Memory with no Displacement.
4) Register to / from Memory with Displacement.
5) Immediate Operand to Register.
6) Immediate Operand to Memory with 16 bit Displacement.
1) One Byte Instruction: -
D7 D0
OPCODE
1) This format is only one byte long and may have the implied data or register
operands.
2) The least significant 3 bits of the opcode are used for specifying the register
operand, if any.
3) Otherwise, all the 8 bits form an opcode and the operands are implied.
2) Register to Register: -
D7 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
OPCODE W 1 1 REG R/M
1) This format is two bytes long.

2) The first byte of the code specifies the operation code and width of the operand
by W bit.

3) The second byte of the code shows the register operands and R/M field, as
shown.
4) The register represented by the REG field is one of the operands.
5) The R/M field specifies another register or memory location, i.e. the other
operand.
3) Register to / from Memory with no Displacement: -
D7 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
OPCODE W MOD REG R/M
1) This format is also 2 bytes long and similar to the register to register format
except for the MOD field as shown.
2) The MOD field shows the mode of addressing. The R/M, REG, and the W fields
are same as in above format.
4) Register to / from Memory with Displacement: -
D7 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D0 D7 D0
Lower Byte Higher Byte
OPCODE MOD REG R/M
of Disp. of Disp.
1) This type of instruction format contains one or two additional bytes for
displacement along with 2 byte the format of the register to / from memory
without displacement. The format is as shown.
5) Immediate Operand to Register: -
D7 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D0 D7 D0
OPCODE 11 REG R/M
of DATA of DATA

1) In this format, the first byte as well as 3 bits from the second byte, which are
used for REG field in case of register to register format are used for opcode.
2) In also contains one or two bytes of immediate data. The complete instruction
format is as shown.
6) Immediate Operand to Memory with 16 bit Displacement: -
D7 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D0 D7 D0
OPCODE MOD REG R/M
of Disp. of Disp.
D7 D0 D7 D0
of DATA of DATA
1) This type of instruction format requires 5 or 6 bytes for coding. The first 2 bytes
contain the information regarding opcode, MOD, and R/M fields.
2) The remaining 4 bytes contains 2 bytes of displacement and 2 bytes of data as
shown.
3) The opcode usually appears in the first byte, but in a few instructions, a register
destination is in the first byte and few other instructions may have their 3 bits of
opcode in the second byte.
4) The opcodes have the single bit indicators. Their definitions as follows –
a) W – bit: -
i) This indicates whether the instruction is to operate over an 8 bit or 16 – bit
data / operands.
ii) If W bit is 0, the operand is of 8 bits and if W is 1, the operand is of 16 bits.
b) D – bit: -
i) This is valid in case of double operand instruction. One of the operands must
be a register specified by the REG field.

ii) The register specified by REG is source operand if D=0, else, it is a

destination operand.
c) S – bit: -
i) This is a sign extension bit and is used with W bit to show the type of
operation.
ii) For e.g.: - 8 bit operation with 8 bit immediate operand is indicated by S=0,
W=0.
iii) 16 bit operation with 16 bit immediate operand is indicated by S=0, W=1.
iv) 16 bit operation with a sign extended immediate data is given by S=1, W=1.
d) V – bit: -
i) This bit used in case of shift and rotate instruction. This bit is set to 0, if shift
count is 1 and is set to 1, if CL contains the shift count.
e) Z – bit: -
i) This bit is used by REP instruction to control the loop.
ii) If Z Bit is equal to 1, the instruction with REP prefix is executed until the
zero flag matches the Z bit.
Addressing Modes of 8086: -

1) Addressing mode indicates a way of locating data or operands.
2) Depending upon the data types used in the instructions and the memory
addressing modes, any instruction may belongs to one or more addressing
modes, or some instructions may not belong to any of the addressing modes.
3) The different ways with which a processor can access operands are referred to
as its addressing modes.
4) According to the flow of instruction execution, the instructions may be
categorized as –
A) Sequential Control Flow Instructions and
B) Control Transfer Instructions.

A) Sequential Control Flow Instructions: -

1) Sequential control flow instructions are the instructions which after execution,
transfer control to the next instruction appearing immediately after it (in the
sequence) in the program.
2) For e.g.: - The arithmetic, logical, data transfer and processor control
instructions are sequential control flow instructions.
3) The addressing modes for sequential control flow instructions are as follows –
a) Immediate Addressing Mode.
b) Direct Addressing Mode.
c) Register Addressing Mode.
d) Register Indirect Addressing Mode.
e) Indexed Addressing Mode.
f) Register Relative Addressing Mode.
g) Based Indexed Addressing Mode.
h) Relative Based Indexed Addressing Mode.
a) Immediate Addressing Mode: -

1) In this type of addressing, immediate data is a part of instruction, and appears in
the form of successive byte or bytes.
2) In other words, if the data operand is directly specified in the instruction
immediate after the opcode then it is called as immediate mode of addressing.
For e.g.: -
(i) MOV BL, 79H
(ii) MOV AX, 1235H
3) In the first instruction of above example, data 79H (8 bit data) is directly given
in the instruction and transferred to the specified register BL immediately.

4) In the second instruction of above example, data 1235H (16 bit data) is directly
given in the instruction and transferred to the specified register AX
immediately.
b) Direct Addressing Mode: -

1) In the direct addressing mode, a 16 bit memory address (offset) is directly
specified in the instruction as a part of it.
For e.g.: - MOV AX, [5000H]
2) In the above example, data resides in a memory location in the data segment,
whose effective address may be computed using 5000H as the offset address
and content of DS as segment address. The effective address, here, is
10H*DS+5000H.
c) Register Addressing Mode: -

1) In register addressing mode, the data is stored in a register and it is referred
using the particular register.
2) All the registers, except IP, may be used in this mode.
For e.g.: - MOV BX, AX
3) In the above example, a 16 bit data is stored in AX register, and is transferred to
BX register.
d) Register Indirect Addressing Mode: -

1) Sometimes, the address of the memory location which contains data or operand
is determined in an indirect way, using the offset registers. This mode of
addressing is known as register indirect mode.
2) In this addressing mode, the offset address of data is in either BX or SI or DI
register.
3) The default segment is either DS or ES. The data is supposed to be available at
the address pointed to by the content of any of the above registers in the default
data segment.
For e.g.: - MOV AX, [BX]

4) In the above example, data is present in a memory location in DS whose offset

address is in BX. The effective address of the data is given as 10H*DS+[BX].
e) Indexed Addressing Mode: -

1) In this addressing mode, offset of the operand is stored in one of the index
registers SI or DI.
2) DS and ES are the default segments for index registers SI and DI respectively.
For e.g.: - MOV AX, [SI]
3) In the above example, data is available at an offset address stored in SI in DS,
and its effective address is computed as 10H*DS+[SI].
f) Register Relative Addressing Mode: -

1) In this addressing mode, the data is available at an effective address formed by
adding an 8 bit or 16 bit displacement with the content of any one of the
registers BX, BP, SI and DI in the default data segment DS or ES.
For e.g.: -
(i) MOV AX, 50H [BX]
(ii) MOV AX, 1234H [BX]
2) In the above first example, 50H is an 8 bit displacement, and its effective
address is given as 10H*DS+50H+[BX].
3) In the second example, 1234H is a 16 bit displacement, and its effective address
is given as 10H*DS+1234H+[BX].
g) Based Indexed Addressing Mode: -

1) In this addressing mode, the effective address of data is formed by adding
content of a base register (any one of BX or BP) to the content of an index
register (any one of SI or DI).
2) The default segment registers in this mode are either DS or ES.
For e.g.: - MOV AX, [BX] [SI]

3) In the above example, BX is the base register and SI is the index register. The
effective address is computed as, 10H*DS+[BX]+[SI].
h) Relative Based Indexed Addressing Mode: -

1) The effective address is formed by adding an 8 bit or 16 bit displacement with
the sum of contents of any one of the base registers (BX or BP) and any one of
the index registers (SI or DI), in a default segment (either DS or ES).
For e.g.: - MOV AX, 50H [BX] [SI]
2) In the above example, 50H is an 8 bit immediate displacement, BX is a base
register and SI is an index register. The effective address of data is computed as
10H*DS+[BX]+[SI]+50H.
B) Control Transfer Instructions: -

1) The control transfer instructions transfer control to some predefined address or
the address somehow specified in the instruction, after their execution.
For e.g.: - INT, CALL, RET, and JUMP instructions fall under this category.
2) For the control transfer instructions, the addressing modes depend upon whether
the destination location is within the same segment or a different one.
3) It also depends upon the method of passing the destination address to the
processor.
4) Basically, there are two addressing modes for the control transfer instructions as
follows –
a) Intersegment Addressing Mode.
b) Intrasegment Addressing Mode.
5) If the location to which the control is to be transferred lies in a different
segment other than the current one, the mode is called intersegment mode.
6) If the destination location lies in the same segment, the mode is called
intrasegment mode.

Modes for Control Transfer Instructions
Intersegment Intrasegment
Intersegment Intersegment Intrasegment Intrasegment
Direct Indirect Direct Indirect
Figure: - Addressing Modes for Control Transfer Instructions.
i) Intrasegment Direct Addressing Mode: -

1) In this mode, the address to which the control is to be transferred lies in the
same segment in which the control transfer instruction lies and appears directly
in the instruction as an immediate displacement value.
2) In this addressing mode, the displacement is computed relative to the content of
the instruction pointer IP.
3) The effective address to which the control will be transferred is given by the
sum of 8 bit or 16 bit displacement and current content of IP.
4) In case of jump instruction, if the signed displacement is of 8 bits, we term it as
short jump and if it is of 16 bits, it is termed as long jump.
ii) Intrasegment Indirect Addressing Mode: -

1) In this mode, the displacement to which the control is to be transferred is in the
same segment in which the control transfer instruction lies, but it is passed to
the instruction indirectly.
2) This addressing mode may be used in unconditional branch instructions. The
branch address is found as the content of a register or memory location.

iii) Intersegment Direct Addressing Mode: -

1) In this mode, the address to which the control is to be transferred is in a
different segment and appears directly in the instruction.
2) This addressing mode provides a means of branching from one code segment to
another code segment.
3) The CS and IP of the destination address are specified directly in the instruction.
iv) Intersegment Indirect Addressing Mode: -

1) In this mode, the address to which the control is to be transferred lies in a
different segment and it is passed to the instruction indirectly, i.e. contents of a
memory block containing four bytes, i.e. IP (LSB), IP (MSB), CS (LSB), and
CS (MSB) sequentially.
2) The starting address of the memory block may be referred using any of the
addressing modes, except immediate mode.
Instruction Set of 8086: -

The 8086 instructions are categorized in following main types.
A) Data Copy / Transfer Instructions: -
1) These types of instructions are used to transfer data from source operand to
destination operand. All the store, move, load, exchange, input, and output
instructions belong to this category.
B) Arithmetic and Logical Instructions: -

1) All the instructions performing arithmetic, logical, increment, decrement, compare
and scan instructions belong to this category.
C) Branch Instructions (Control Transfer Instructions): -

1) These instructions transfer control of execution to the specified address. All the call,
jump, interrupt, and return instructions belong to this class.

D) Loop Instructions: -
1) If these instructions have REP prefix with CX used as count register, they can be
used to implement unconditional and conditional loops as well as these are
useful to implement different loop structures. The LOOP, LOOPNZ and
LOOPZ instructions belong to this category.
E) Machine (Processor) Control Instructions: -

1) These instructions control the machine status. NOP, HLT, WAIT, and LOCK
instructions belong to this class.
F) Flag Manipulation Instructions: -

1) All the instructions which directly affect the flag register, come under this group of
instructions. Instructions like CLD, STD, CLI, STI, etc. belong to this category.
G) Shift and Rotate Instructions: -

1) These instructions involve the bitwise shifting or rotation in either direction
with or without a count in CX.
H) String Instructions: -
1) These instructions involve various string manipulation operations like load,
move, scan, compare, store, etc.
Now let us see the instructions of each category in detail.
A) Data Copy / Transfer Instructions: -

1) MOV: – Move
i) Syntax: - MOV Destination, Source
ii) The MOV instruction copies a word or byte of data from a specified source to a
specified destination. MOV instruction does not affect any flag.
iii) The destination can be a register or a memory location (memory address).

iv) The source can be a register, a memory location or an immediate number

(immediate data).
v) The source and destination in an instruction, both can be of same type, i.e. both
can be of type byte (8 bit) or type word (16 bit).
vi) The source and destination in an instruction, both cannot be memory locations
(except for string instructions).
Examples: - The examples with addressing modes are as follow –
1. MOV AX, 5000H ; Immediate Addressing Mode
2. MOV AX, [2000H] ; Direct Addressing Mode
3. MOV AX, BX ; Register Addressing Mode
4. MOV AX, [BX] ; Register Indirect Addressing Mode
5. MOV AX, [SI] ; Indexed Addressing Mode
6. MOV AX, 50H [BX] ; Register Relative Addressing Mode
7. MOV AX, [BX] [SI] ; Based Indexed Addressing Mode
8. MOV AX, 10H [BX] [SI] ; Relative Based Indexed Addressing Mode
vii) In case of immediate addressing mode, a segment register cannot be a
destination register.
For e.g.: - MOV DS, 5000H ; Not Permitted (Invalid)
viii) To load the segment registers with immediate data, we have to load any general
purpose register with the data and then it will have to be moved to that
particular segment register.
For e.g.: - MOV AX, 5000H ; Permitted
MOV DS, AX ; (Valid)
2) PUSH: – Push to Stack

i) Syntax: - PUSH Source
ii) This instruction pushes the contents of the specified source on to the stack. No
flags are affected by this instruction.
iii) The source may be a general purpose register, a segment register or memory
location.

iv) Before PUSH, the stack pointer is decremented by 2, and then stores the two
byte contents of the operand onto the location in stack segment where the stack
pointer points.
v) The higher byte is pushed first and then the lower byte is pushed. Thus out of
two bytes, higher byte occupies the higher address and lower byte occupies the
lower address.
Examples: -
1. PUSH BX ; Decrement SP by 2, copy BX to stack
2. PUSH DS ; Decrement SP by 2, copy DS to stack
3. PUSH [5000H] ; Content of location 5000H and 5001H in DS are
; pushed onto the stack
4. PUSH AL ; Invalid, must push a word
3) POP: – Pop from Stack

i) Syntax: - POP Destination
ii) The POP instruction copies a word from the stack location pointed to by the
stack pointer to a destination specified in the instruction. No flags are affected
by the POP instruction.
iii) The destination can be a general purpose register, a segment register, or a
memory location. The data in the stack is not changed.
iv) After the word is copied to the specified destination, the stack pointer is
automatically incremented by 2 to point to the next word on the stack.
Examples: -
1. POP BX ; Copy a word from top of stack to BX
; Increment SP by 2
2. POP DS ; Copy a word from top of stack to DS
; Increment SP by 2
3. POP [5000H] ; Copy a word from top of stack to location 5000H
; and 5001H in DS
; Increment SP by 2

4) XCHG: – Exchange
i) Syntax: - XCHG Destination, Source
ii) The XCHG instruction exchanges the contents of a specified source with the
contents of a specified destination. No flags are affected by this instruction.
iii) The source and destination both can be a registers (but not the segment
registers) or one of them is memory location.
iv) Both the operands cannot be a memory location. In other words, this instruction
cannot directly exchange the contents of two memory locations.
v) The source and destination must both be words, or must both be bytes.
Examples: -
1. XCHG AX, DX ; Exchange word in DX with word in AX
2. XCHG BL, CH ; Exchange byte in CH with byte in BL
3. XCHG [5000H], AX ; Exchange word in location [5000H] in data
; Segment with word in AX
4. XCHG BX ; Exchange word in BX with word in AX
5) IN: – Input the Port

i) Syntax: - IN Destination, Source
ii) IN instruction will copy (read) the data from an input port whose address is
specified in the instruction directly or indirectly as a source. No flags are
affected by this instruction.
iii) The AL and AX are the allowed destinations for 8 and 16 bit input operations.
iv) DX is the only register (implicit) which is allowed to carry the port address.
Examples: -
1. IN AL, 0300H ; Input a byte from port 0300H to AL
2. IN AX, 34H ; Input a word from port 34H to AX
3. IN AX ; Input a word from DX (implicit) to AX

6) OUT: – Output to the Port

i) Syntax: - OUT Destination, Source
ii) The OUT instruction will copy (write) the data from source to an output port
whose address is specified in the instruction directly or indirectly (implicitly in
DX) as a destination. No flags are affected by this instruction.
iii) The AL and AX are the allowed source for 8 and 16 bit output operations.
Examples: -
1. OUT 0300H, AL ; Copy the 8 bit contents of AL to port 0300H
2. OUT 34H, AX ; Copy the 16 bit contents of AX to port 34H
3. OUT AX ; Copy the 16 bit contents of AX to DX (implicit)
7) XLAT: – Translate
i) Syntax: - XLAT
ii) This instruction is used to translate a byte from one code to another code. This
instruction does not affect any flag.
iii) The XLAT instruction replaces a byte in AL register with a byte pointed to by
BX in a lookup table in memory.
iv) Suppose, a hexadecimal key pad having 16 keys from 0 to F is interfaced with
8086 using 8255.
v) Whenever a key is pressed, a code of that key (0 to F) is returned in AL. For
displaying the number corresponding to the pressed key on the 7-segment
display device, it is required that the 7-segment code corresponding to the key
pressed is found out and sent to the display port.
vi) This translation from the code of the pressed key to the corresponding 7-
segment code is performed using XLAT instruction.
Example: -
MOV AX, SEG TABLE ; Address of the segment containing look up
MOV DS, AX ; table is transferred in DS
MOV AL, CODE ;Code to the pressed key is transferred in AL
MOV BX, OFFSET TABLE ; Offset of the code lookup table in BX
XLAT ;Find the equivalent code and store in AL

8) LEA: – Load Effective Address

i) Syntax: - LEA Register, Source
ii) The LEA instruction loads (determines) the offset of the operand (variable) or
memory location named as source and stores (put) this offset in the specified
(destination) register. LEA does not change any flag.
Example: -
LEA BX, ADR ; Loads the offset of the label ADR in BX
9) LDS/LES: – Load Pointer to DS/ES

i) Syntax: - LDS / LES Register, Memory Address of First Word
ii) The instruction, Load DS/ES with pointer, loads the DS or ES register and the
specified destination register in the instruction with the content of four memory
locations specified as source in the instruction.
iii) The word from the first two memory locations is copied into the specified
register, and the word from the next two memory locations is copied into the
DS/ES register.
iv) The LDS is useful for pointing SI and DS, and LES is useful for pointing DI and
ES at the start of a string before using one of the string instructions. The LDS /
LES instruction does not affect flag register.
Example: -
LDS / LES BX, 5000H
7 0 15 8 7 0
BX Y X
5000 XX Y X
5001 YY
5002 mm DS/ES nn mm
5003 nn
10) LAHF: – Copy Lower Byte of Flag Register to AH Register

i) Syntax: - LAHF
ii) LAHF instruction loads the AH register with the lower byte of flag register.
This instruction does not change any flags.
iii) The LAHF instruction may be used to observe the status of all the condition
code flags (except overflow) at a time.
11) SAHF: – Copy AH Register to Lower Byte of Flag Register

i) Syntax: - SAHF
ii) The SAHF instruction sets or resets the condition code flags (except overflow)
in the lower byte of the flag register depending upon the corresponding bit
positions in AH.
iii) If a bit in AH is 1, the flag corresponding to the bit position is set, else it is
reset.
12) PUSHF: – Push Flag Register on to the Stack

i) Syntax: - PUSHF
ii) The PUSHF (push flag) instruction pushes the flag register on to the stack; first
the upper byte and then the lower byte will be pushed on to the stack.
iii) The SP is decremented by 2 before each push operation. The stack segment
register is not affected.
iv) This instruction does not affect the flag register. The general operation of this
instruction is similar to PUSH operation.
13) POPF: – Pop Flag Register from Stack

i) Syntax: - POPF
ii) This instruction copies a word from the two memory locations at the top of the
stack to the flag register and increment the SP by 2.
iii) The stack segment register is not affected by this instruction. All the flags are

B) Arithmetic and Logical Instructions: -

a) Arithmetic Instructions: -
1) ADD: – Add
i) Syntax: - ADD Destination, Source
ii) The ADD instruction adds the contents of a source operand with the content of a
destination operand and stores the result in the destination operand. All the
condition code flags are affected by this instruction, depending upon the result.
iii) The source may be an immediate data (number), a register, or a memory
location.
iv) The destination may be a register or a memory location but it cannot be an
immediate data.
v) The source and destination in an instruction cannot both be memory locations.
Also the content of the segment registers cannot be added using this instruction.
vi) The source and destination must be of the same type i.e. both are of type byte (8
bit) or of type word (16 bit).
vii) If we want to add a byte to a word, we must copy the byte to a word location
and fill the upper byte of the word with 0’s before adding. Examples: - The
examples with addressing modes are as follow –
1. ADD AX, 0100H ; Immediate Addressing Mode
2. ADD AX, [5000H] ; Direct Addressing Mode
3. ADD AX, BX ; Register Addressing Mode
4. ADD AX, [BX] ; Register Indirect Addressing Mode
5. ADD AX, [SI] ; Indexed Addressing Mode
6. ADD 0100H ; Immediate Mode (Destination AX (implicit))
2) ADC: – Add with Carry

i) Syntax: - ADC Destination, Source
ii) This instruction performs the same operation as ADD instruction, but adds the
carry flag bit to the result.

iii) The carry flag bit may be set as a result of the previous calculations. All the
condition code flags are affected by this instruction.
1. ADC AX, 0100H ; Immediate Addressing Mode
2. ADC AX, [5000H] ; Direct Addressing Mode
3. ADC AX, BX ; Register Addressing Mode
4. ADC AX, [BX] ; Register Indirect Addressing Mode
5. ADC AX, [SI] ; Indexed Addressing Mode
6. ADC 0100H ; Immediate Mode (Destination AX (implicit))
3) INC: – Increment
i) Syntax: - INC Destination
ii) This instruction increments the content of the specified destination by 1. In
other words, this instruction adds 1 to the content of the destination specified in
an instruction.
iii) The destination may be a register or a memory location but it cannot be an
immediate data. All the condition code flags are affected except the carry flag
(CF) by this instruction.
1. INC [5000H] ; Direct Addressing Mode
2. INC AX ; Register Addressing Mode
3. INC [BX] ; Register Indirect Addressing Mode
4. INC [SI] ; Indexed Addressing Mode
4) DEC: – Decrement
i) Syntax: - DEC Destination
ii) This instruction decrements the content of the specified destination by 1. In
other words, this instruction subtracts 1 from the content of the destination
specified in an instruction.

iii) The destination may be a register or a memory location but it cannot be an

immediate data. All the condition code flags are affected except the carry flag
(CF) by this instruction.
1. DEC [5000H] ; Direct Addressing Mode
2. DEC AX ; Register Addressing Mode
3. DEC [BX] ; Register Indirect Addressing Mode
4. DEC [SI] ; Indexed Addressing Mode
5) SUB: – Subtract
i) Syntax: - SUB Destination, Source
ii) The SUB instruction subtracts the contents of a source operand from the content
of a destination operand and stores the result in the destination operand. All the
condition code flags are affected by this instruction, depending upon the result.
iii) The source may be an immediate data (number), a register, or a memory
location.
immediate data.
v) The source and destination in an instruction cannot both be memory locations.
Also the content of the segment registers cannot be subtracted using this
instruction.
vi) The source and destination must be of the same type i.e. both are of type byte (8
vii) If we want to subtract a byte from a word, we must copy the byte to a word
location such as a 16 bit register and fill the upper byte of the word with 0’s.
1. SUB AX, 0100H ; Immediate Addressing Mode
2. SUB AX, [5000H] ; Direct Addressing Mode
3. SUB AX, BX ; Register Addressing Mode

4. SUB AX, [BX] ; Register Indirect Addressing Mode

5. SUB AX, [SI] ; Indexed Addressing Mode
6. SUB 0100H ; Immediate Mode (Destination AX (implicit))
6) SBB: – Subtract with Borrow

i) Syntax: - SBB Destination, Source
ii) The SBB instruction subtracts the contents of specified source and the contents
of a CF from the contents of specified destination, and store the result in the
destination operand. All the condition code flags are affected by this instruction,
depending upon the result.
iii) For subtraction, carry flag (CF) functions as a borrow flag. The carry flag will
be set after a subtraction if the number in the specified source is larger than the
number in the specified destination.
iv) The source may be an immediate data (number), a register, or a memory
location.
v) The destination may be a register or a memory location but it cannot be an
immediate data.
vi) The source and destination in an instruction cannot both be memory locations.
Also the content of the segment registers cannot be subtracted using this
instruction.
vii) The source and destination must be of the same type i.e. both are of type byte (8
viii) If we want to subtract a byte from a word, we must copy the byte to a word
location such as a 16 bit register and fill the upper byte of the word with 0’s.
1. SBB AX, 0100H ; Immediate Addressing Mode
2. SBB AX, [5000H] ; Direct Addressing Mode
3. SBB AX, BX ; Register Addressing Mode
4. SBB AX, [BX] ; Register Indirect Addressing Mode
5. SBB AX, [SI] ; Indexed Addressing Mode

6. SBB 0100H ; Immediate Mode (Destination AX (implicit))
7) CMP: – Compare
i) Syntax: - CMP Destination, Source
ii) The CMP instruction compares the content of source operand with the content
of destination operand. All the condition code flags are affected by this
instruction, depending upon the result.
iii) For comparison, this instruction subtracts the content of source operand from
the content of destination operand, but does not store the result anywhere.
iv) The source and destination are not changed, but the flags are set to indicate the
results of the comparison.
v) If both the operands are equal, zero flag is set i.e. ZF=1. If the source operand is
greater than the destination operand, carry flag and sign flag (since the result is
negative) both are set i.e. CF=1, SF=1. If the source operand is less than the
destination operand, carry flag and sign flag both are reset i.e. CF=0, SF=0.
vi) The source may be an immediate data (number), a register, or a memory
location.
vii) The destination may be a register or a memory location but it cannot be an
immediate data.
viii) The source and destination in an instruction cannot both be memory locations.
1. CMP BX, 0100H ; Immediate Addressing Mode
2. CMP 0100H ; Immediate Addressing Mode
3. CMP BX, [1234H] ; Direct Addressing Mode
4. CMP BX, AX ; Register Addressing Mode
5. CMP AX, [BX] ; Register Indirect Addressing Mode
6. CMP AX, [SI] ; Indexed Addressing Mode

8) AAA: – ASCII Adjust After Addition

i) Syntax: - AAA
ii) The AAA instruction is executed after an ADD instruction that adds two ASCII
coded operands to give a byte of result in AL. The AAA instruction converts the
resulting contents of AL to unpacked decimal digits.
iii) After the addition, the AAA instruction examines the lower 4 bits of AL to
check whether it contains a valid BCD number in the range 0 to 9.
iv) If it is in between 0 to 9 and AF is zero, AAA sets the 4 high order bits of AL to
0. The AH must be cleared before addition.
For e.g.: - AL 5 7 – Before to AAA
AL 0 7 – After AAA execution
v) It the lower digit of AL is between 0 to 9 and AF is set, 06 is added to AL. The
upper 4 bits of AL are cleared and AH is incremented by 1.
vi) If the value in the lower nibble of AL is greater than 9 then the AL is
incremented by 06, AH is incremented by 1, the AF and CF flags are set to 1,
and the higher 4 bits of AL are cleared to 0. The remaining flags are unaffected.
The AH is modified as sum of previous contents and carry from the adjustment.
For e.g.: - AL 5 A Previous to AAA

A
AH> 9, 0hence 0A + 6 = 1010 + 0110
= 10000 B
= 10H
AX 0 0 5 A – Previous to AAA
AX 0 1 0 0 – After AAA
execution
9) AAS: – ASCII Adjust AL After Subtraction

i) Syntax: - AAS
ii) AAS instruction corrects the result in AL register after subtracting two
unpacked ASCII operands. The result is in unpacked decimal format.

iii) If the lower 4 bits of AL register are greater than 9 or if the AF flag is 1, the AL
is decremented by 6 and AH register is decremented by 1, the CF and AF are set
to 1.
iv) Otherwise, the CF and AF are set to 0, the result needs no correction. As a
result, the upper nibble of AL is 00 and the lower nibble may be any number
from 0 to 9.
v) The procedure is similar to the AAA instruction. AH is modified as difference
of the previous contents of AH and borrow for adjustment.
10) AAM: – ASCII Adjust for Multiplication

i) Syntax: - AAM
ii) The AAM instruction is used after multiplication instruction, and after
execution, this instruction converts the product (result) in AL into unpacked
BCD format.
iii) The lower byte of result (unpacked) remains in AL and the higher byte of result
remains in AH. The condition code flags (PF, SF, and ZF) are affected by this
iv) Suppose the product in AL is 5DH. The AAM instruction will form unpacked
BCD result in AX.
v) DH is greater than 9, so add 6 (0110) to it, i.e. D+6=13H. LSD of 13H is the
lower unpacked byte for the result. Increment AH by 1, i.e. 5+1=6 will be the
upper unpacked byte of the result. Thus after the execution, AH=06 and AL=03.
11) AAD: – ASCII Adjust for Division

i) Syntax: - AAD
ii) The AAD instruction converts two unpacked BCD digits in AH and AL to the
equivalent binary number in AL. The PF, SF, and ZF are affected whereas CF,
AF, and OF are undefined after AAD.

iii) This adjustment must be made before dividing the two unpacked BCD digits in
AX by an unpacked BCD byte. This means that AAD instruction is executed
before the DIV instruction.
Example: -
; AX = 0607H unpacked BCD for 67 decimal
; CH = 09H, now adjust to binary
AAD ; Result: AX = 0043 = 43H = 67 decimal
DIV CH ; Divide AX by unpacked BCD in CH
; Quotient: AL = 07 unpacked BCD
; Remainder: AH = 04 unpacked BCD
; Flags undefined after DIV
12) DAA: – Decimal Adjust Accumulator

i) Syntax: - DAA
ii) The DAA instruction is used to convert the result of the addition of two packed
BCD numbers to a valid BCD number. The result has to be only in AL. All the
condition code flags (except SF and OF - undefined) are affected by this
iii) If the lower nibble is greater than 9, after addition or if AF is set, it will add 06
to the lower nibble in AL.
iv) After adding 06 in the lower nibble of AL, if the upper nibble of AL is greater
than 9 or if carry flag is set, DAA instruction adds 60H to AL. Examples: -
1. AL = 53
CL = 29
ADD AL, CL ; AL (AL) + (CL)
; AL 53 + 29
; AL 7C
DAA ; AL 7C + 06 (as C>9)
; AL 82

2. AL = 73
CL = 29
ADD AL, CL ; AL AL + CL
; AL 73 + 29
; AL 9C
DAA ; AL 02 and CF = 1
13) DAS: – Decimal Adjust After Subtraction

i) Syntax: - DAS
ii) The DAS instruction is used to convert the result of the subtraction of two
packed BCD numbers to a valid BCD number. The result has to be only in AL.
All the condition code flags (except OF - undefined) are affected by this
iii) If the lower nibble is greater than 9, after subtraction or if AF is set, it will
subtract 06 from the lower nibble in AL.
iv) After subtracting 06 from the lower nibble of AL, if the upper nibble of AL is
greater than 9 or if carry flag is set, DAA instruction subtracts 60H from AL.
Examples: -
1. AL = 75
BH = 46
SUB AL, BH ; AL 2 F = (AL) – (BH)
; AF = 1
DAS ; AL 2 9 (as F>9, F – 6 = 9)
2. AL = 38
CH = 61
SUB AL, CH ; AL D7 CF = 1 (borrow)
DAS ; AL 77 (as D>9, D – 6 = 7)
; CF = 1 (borrow)

14) NEG: – Negate

i) Syntax: - NEG Destination
ii) The negate instruction forms 2’s complement of the specified destination in
the instruction. All the condition code flags are affected by this instruction,
iii) For obtaining 2’s complement, it subtracts the contents of destination from
zero. The result is stored back in the destination operand which may be a
register or memory location.
iv) If the operation could not be completed unsuccessful, then the OF is set.
Examples: -
1. NEG AL ; Replace byte in AL with its 2’s complement
2. NEG BX ; Replace word in BX with its 2’s complement
3. NEG BYTE PTR [BX] ; Replace byte at offset [BX] in DS with its
; 2’s complement
4. NEG WORD PTR [BP] ; Replace word at offset [BP] in SS with its
; 2’s complement
15) MUL: – Unsigned Multiplication Byte or Word

i) Syntax: - MUL Source
ii) This instruction multiplies an unsigned byte or word specified as source operand
by the contents of AL that act as destination operand. All the flags are modified
iii) The unsigned byte or word (source) may be in any one of the registers or
memory locations. The destination operands are implicit and they are AL and
AX in case of 8 bits and 16 bits multiplications respectively.
iv) In case of 8 bit multiplication, the result can be as large as 16 bits. So the 16 bit
destination is required to store the result and that destination is AX.
v) In such a case, the most significant byte of the result is stored AH, and the least
significant byte of the result is stored in AL.

vi) Similarly, in case of 16 bit multiplication, the result can be as large as 32 bits.
So 32 bit destination is required to store the result and that destination is DX
and AX register respectively.
vii) In such a case, the most significant word of the result is stored in DX, while the
least significant word of the result is stored in AX.
Examples: -
1. MUL BH ; (AX) (AL) × (BH)
2. MUL CX ; (DX) (AX) (AX) × (CX)
3. MUL WORD PTR [SI] ; (DX) (AX) (AX) × ([SI])
16) IMUL: – Signed Multiplication

i) Syntax: - IMUL Source
ii) This instruction multiplies a signed byte in source operand by a signed byte in
AL or signed word in source operand by signed word in AX. All the condition
code flags are affected, depending upon the result.
iii) The source can be a register or memory location, but it cannot be an immediate
data.
iv) In case of 32 bit results, the higher word is stored in DX and the lower word is
stored in AX.
Examples: -
1. IMUL BH ; (AX) (AL) × (BH)
2. IMUL CX ; (DX) (AX) × (CX)
(AX)
3. IMUL [SI] ; (DX) (AX) × ([SI])
(AX)
17) CBW: – Convert Signed Byte to Word

i) Syntax: - CBW
ii) This instruction converts a signed byte to a signed word. It copies a sign bit of a
byte to be converted to all the bits in the higher byte of the result word.
iii) The byte to be converted must be in AL. The result will be in AX. No flags are

iv) The CBW operation must be done before a signed byte in AL can be divided by
another signed byte.
18) CWD: – Convert Signed Word to Double Word

i) Syntax: - CWD
ii) This instruction converts a signed word to a signed double word. It copies the
sign bit of AX to all the bits of the DX register.
iii) This operation is to be done before signed division. No flags are affected by this
instruction.
19) DIV: – Unsigned Division

i) Syntax: - DIV Source
ii) The DIV instruction performs unsigned division. It divides an unsigned word or
double word by a 16 bit or 8 bit operand. No flags are affected by this
instruction.
iii) The dividend must be in AX for 16 bit operation and divisor may be specified
using any one of the addressing modes except immediate.
iv) The result will be in AL (quotient) while AH will contain the remainder. If the
result is too big to fit in AL, type 0 (divide by zero) interrupt is generated.
v) In case of double word dividend (32 bit), the higher word should be in DX
(Remainder) and the lower word should be in AX (Quotient).
Examples: -
1. DIV BL ; Divide word in AX by byte in BL
2. DIV CX ; Divide double word in DX and AX by word in CX
20) IDIV: – Signed Division

i) Syntax: - IDIV Source
ii) The IDIV instruction performs signed division. It divides a signed word or
double word by a 16 bit or 8 bit operand. No flags are affected by this
instruction.

iii) The dividend must be in AX for 16 bit operation and divisor may be specified
using any one of the addressing modes except immediate.
iv) The result will be in AL (quotient) while AH will contain the remainder. If the
result is too big to fit in AL, type 0 (divide by zero) interrupt is generated.
v) In case of double word dividend (32 bit), the higher word should be in DX
(Remainder) and the lower word should be in AX (Quotient).
Examples: -
1. IDIV BL ; Divide word in AX by byte in BL
2. IDIV CX ; Divide double word in DX and AX by word in CX
b) Logical Instructions: -
1) AND: – Logical AND
i) Syntax: - AND Destination, Source
ii) The AND instruction bit by bit ANDs the content of source operand with the
content of destination operand. The result is stored in the destination operand.
All the condition code flags are affected by this instruction.
iii) The source may be an immediate data, a register or a memory location.
immediate data.
v) Both the operands can be a register but both cannot be a memory location.
Examples: -
1. AND AX, 0008H ; Immediate Addressing Mode
This instruction bit by bit ANDs 0008H immediate data with the content of
destination i.e. AX, the result is stored in AX. Suppose AX=3F0FH, then the
output will be as,
0011 1111 0000 1111 = 3F0FH [AX]
0000 0000 0000 1000 = 0008H
0000 0000 0000 1000 = 0008H [AX]
2. AND AX, [5000H] ; Direct Addressing Mode
3. AND AX, BX ; Register Addressing Mode

2) OR: – Logical OR
i) Syntax: - OR Destination, Source
ii) The OR instruction bit by bit ORs the content of source operand with the
content of destination operand. The result is stored in the destination operand.
All the condition code flags are affected by this instruction.
iii) The source may be an immediate data, a register or a memory location.
immediate data.
v) Both the operands can be a register but both cannot be a memory location.
Examples: -
1. OR AX, 0098H ; Immediate Addressing Mode
This instruction bit by bit ORs 0098H immediate data with the content of
output will be as,
0011 1111 0000 1111 = 3F0FH [AX]
0000 0000 1001 1000 = 0098H
0011 1111 1001 1111 = 3F9FH [AX]
2. OR AX, [5000H] ; Direct Addressing Mode
3. OR AX, BX ; Register Addressing Mode
3) NOT: – Logical Invert

i) Syntax: - NOT Destination
ii) The NOT instruction bit by bit complements (inverts) the contents of a specified
destination operand, that may be a register or memory location. No flags are
affected by the NOT instruction.
Examples: -
1. NOT AX ; Register Addressing Mode
If the content of AX is 200FH, the output after execution is,
0010 0000 0000 1111 = 200FH [AX]
1101 1111 1111 0000 = DFF0H [AX]
2. NOT [5000H] ; Direct Addressing Mode

4) XOR: – Logical Exclusive OR

i) Syntax: - XOR Destination, Source
ii) The XOR instruction bit by bit XORs the content of source operand with the
content of destination operand. The XOR operation gives a high output, when
the 2 input bits are dissimilar. Otherwise, the output is zero.
iii) The result is stored in the destination operand. All the condition code flags are
iv) The source may be an immediate data, a register or a memory location.
immediate data.
vi) Both the operands can be a register but both cannot be a memory location.
Examples: -
1. XOR AX, 0098H ; Immediate Addressing Mode
This instruction bit by bit XORs 0098H immediate data with the content of
output will be as,
0011 1111 0000 1111 = 3F0FH [AX]
0000 0000 1001 1000 = 0098H
0011 1111 1001 0111 = 3F97H [AX]
2. XOR AX, [5000H] ; Direct Addressing Mode
3. XOR AX, BX ; Register Addressing Mode
5) TEST: – Logical Compare Instruction

i) Syntax: - TEST Destination, Source
ii) The TEST instruction bit by bit ANDs the contents of a source operand with the
contents of a destination operand, but does not store the result anywhere. All the
condition code flags are affected by TEST instruction.
iii) The TEST instruction is often used to set flags before a conditional jump
instruction.
iv) The source may be an immediate data, a register or a memory location.


immediate data.
vi) Both the operands can be a register but both cannot be a memory location.
Examples: -
1. TEST AX, 2000H ; Immediate Addressing Mode
2. TEST [0500H], AX ; Direct Addressing Mode
C) Branch Instructions (Control Transfer Instructions): -

1) The control transfer instruction transfer the flow of execution of the program to
a new address specified in the instruction directly or indirectly.
2) When this type of instruction is executed, the CS and IP registers get loaded
with new values of CS and IP corresponding to the location where the flow of
execution is going to be transferred.
3) Depending upon the addressing modes, the CS may or may not be modified.
This type of instructions are classified in two types as,
a) Unconditional Control Transfer (Branch) Instructions
b) Conditional Control Transfer (Branch) Instructions
a) Unconditional Branch Instructions: -

i) In case of unconditional control transfer instructions, the execution control is
transferred to the specified location independent of any status or condition. The
CS and IP are unconditionally modified to the new CS and IP.
1) CALL: – Unconditional Call

i) Syntax: - CALL
ii) The CALL instruction is used to transfer the control of execution to the
subprogram or subroutine or procedure from a main program.
iii) The address of the procedure may be specified directly or indirectly depending
upon the addressing mode.
iv) There are two basic types of calls to a procedure, near and far.

v) A near call is a call to a procedure which is in the same code segment that
contains a CALL instruction.
vi) A far call is a call to a procedure which is in a different code segment from the
one that contains the CALL instruction.
vii) When 8086 executes a near CALL instruction, it decrement the SP by 2 and
copies the offset of next instruction after the CALL on to the stack.
viii) This offset saved on the stack is referred to as the return address, because this is
the address that execution will return to after the procedure executes.
ix) A near CALL instruction will also load IP with the offset of the first instruction
in the procedure.
x) When 8086 executes a far CALL instruction, it decrement the SP by 2 and
copies the contents of CS register to the stack. It then decrements the SP by 2
again and copies the offset of the instruction after the CALL instruction to the
stack.
xi) Finally, it loads CS with the segment base of the segment which contains the
procedure, and loads IP with the offset of the first instruction of the procedure in
that segment.
2) RET: – Return from the Procedure

i) Syntax: - RET
ii) The RET instruction will return execution control from a procedure to the
calling program at next instruction after the call instruction which was used to
call the procedure.
iii) At each CALL instruction, the IP and CS of the next instruction are pushed onto
stack, before the control is transferred to the procedure.
iv) At the end of the procedure, the RET instruction is executed, and when it is
executed, the previously stored content of IP and CS along with flags are
retrieved into the CS, IP and flag registers from the stack and the execution of
the main program is continues further.

v) In case of a FAR procedure, the current contents of SP points to IP and CS at

the time of return. While in case of a NEAR procedure, it points to only IP.
3) INT N: – Interrupt Type N

i) Syntax: - INT Type
ii) In the interrupt structure of 8086, 256 interrupts are defined from type 00H to
FFH.
iii) When an INT N instruction is executed, the TYPE byte N is multiplied by 4 and
the contents of IP and CS of the interrupt service routine will be taken from the
hexadecimal multiplication (N × 4) as offset address and 0000 as segment
address.
iv) For execution of this instruction, the IF must be enabled.
Example: -
The instruction INT 20H will find out the address of the ISR as follows.
INT 20H
TYPE × 4 = 20 × 4 = 80H.
The address of ISR obtained is 0000 : 0080 to which IP and CS points.
Memory
Contents
CS High 0000 : 0083

CS Low 0000 : 0082
IP High 0000 : 0081
IP Low 0000 : 0080
4) INTO: – Interrupt on Overflow

i) Syntax: - INTO
ii) The INTO instruction is executed, when the overflow flag is set i.e. OF=1.
iii) The new content of IP and CS are taken from the address 0000:0000.
iv) This is equivalent to a TYPE 4 interrupt instruction.

5) JMP: – Unconditional Jump

i) Syntax: - JMP Destination
ii) The JMP instruction unconditionally transfers the control of execution to the
destination address that may be specified by the register or memory location
(label) using an 8 bit or 16 bit displacement or CS:IP. No flags are affected by
this instruction.
iii) If the destination is in the same code segment as the JMP instruction, then only
the IP will be changed to get to the destination location. This is referred to as a
near jump.
iv) If the destination for the JMP instruction is in another segment, then both the IP
and the CS register contents will be changed to get to the destination location.
This is referred to as a far jump.
Examples: -
1. JMP NEXT
2. JMP BX
3. JMP WORD PTR [BX]
6) IRET: – Return from ISR

i) Syntax: - IRET
ii) The IRET instruction is used at the end of the interrupt service routine (ISR) to
return execution to the interrupted program.
iii) When an ISR is to be called, before transferring control to it, the IP, CS and flag
register are stored on to the stack to indicate the location from where the
execution is to be continued, after the ISR is executed.
iv) So, at the end of each ISR, when IRET is executed, the values of IP, CS and
flags are retrieved from the stack to continue the execution of the main program.
b) Conditional Branch Instructions: -

i) In the conditional control transfer instructions, the control is transferred to the
specified location provided the result of the previous operation satisfies

a particular condition, otherwise, the execution continues in normal flow

sequence.
ii) Using this type of instruction the control will be transferred to a particular
specified location, if a particular flag satisfies the condition.
iii) The condition means the status of condition code flags. These type of
instructions do not affect any flag.
iv) Only short jumps (in the range -128 to 127 bytes) can be implemented using
conditional branch instructions. A label may represent the displacement, if it lies
within the specified range.
1) JZ/JE: – Jump if Zero/Jump if Equal

i) Syntax: - JZ/JE Label
ii) This instruction, after execution transfer the execution control to the address
specified by the label, if zero flag is set i.e. ZF=1.
2) JNZ/JNE: – Jump if Not Zero/Jump if Not Equal

i) Syntax: - JNZ/JNE Label
specified by the label, if zero flag is reset i.e. ZF=0.
3) JS: – Jump if Signed or Jump if Negative

i) Syntax: - JS Label
specified by the label, if sign flag is set i.e. SF=1.
4) JNS: – Jump if Not Signed or Jump if Positive

i) Syntax: - JNS Label
specified by the label, if sign flag is reset i.e. SF=0.

5) JO: – Jump if Overflow

i) Syntax: - JO Label
specified by the label, if overflow flag is set i.e. OF=1.
6) JNO: – Jump if No Overflow

i) Syntax: - JNO Label
specified by the label, if overflow flag is reset i.e. OF=0.
7) JP/JPE: – Jump if Parity/Jump of Parity Even

i) Syntax: - JP/JPE Label
specified by the label, if parity flag is set i.e. PF=1.
8) JNP/JPO: – Jump if No Parity/Jump if Parity Odd

i) Syntax: - JNP/JPO Label
specified by the label, if parity flag is reset i.e. PF=0.
9) JB/JNAE/JC: – Jump if Below/Jump if Not Above or Equal/Jump if Carry

i) Syntax: - JB/JNAE/JC Label
ii) The terms above and below are generally used for unsigned numbers.
iii) This instruction, after execution transfer the execution control to the address
specified by the label, if carry flag is set i.e. CF=1.
10) JNB/JAE/JNC: – Jump if Not Below/Jump if Above or Equal/Jump if No

Carry
i) Syntax: - JNB/JAE/JNC Label
specified by the label, if carry flag is reset i.e. CF=0.

11) JBE/JNA: – Jump if Below or Equal/Jump if Not Above

i) Syntax: - JBE/JNA Label
specified by the label, if carry flag or zero flag is set i.e. CF=1 or ZF=1.
12) JNBE/JA: – Jump if Not Below or Equal/Jump if Above

i) Syntax: - JNBE/JA Label
specified by the label, if carry flag or zero flag is reset i.e. CF=0 or ZF=0.
13) JL/JNGE: – Jump if Less Than/Jump if Not Greater Than or Equal

i) Syntax: - JL/JNGE Label
ii) The terms less and greater are generally used for signed numbers.
iii) This instruction, after execution transfer the execution control to the address
specified by the label, if neither sign flag nor overflow flag is set i.e. neither
SF=1 nor OF=1.
14) JNL/JGE: – Jump if Not Less Than/Jump if Greater Than or Equal

i) Syntax: - JNL/JGE Label
specified by the label, if neither sign flag nor overflow flag is reset
i.e. neither SF=0 nor OF=0.
15) JLE/JNG: – Jump if Less Than or Equal/Jump if Not Greater

i) Syntax: - JLE/JNG Label
specified by the label, if zero flag is set i.e. ZF=1 or neither sign flag nor
overflow flag is set i.e. neither SF=1 nor OF=1.

16) JNLE/JG: – Jump if Not Less Than or Equal/Jump if Greater

i) Syntax: - JNLE/JG Label
specified by the label, if zero flag is reset i.e. ZF=0 or atleast any one of sign
flag or overflag flag is set i.e. SF=1 or OF=1 (both SF and OF are not 0).
17) JCXZ: – Jump if CX is Zero

i) Syntax: - JCXZ Label
ii) This instruction does not check status flags for condition testing.
iii) The JCXZ instruction, after execution transfer execution control to the address
specified by the label, if content of CX register is zero i.e. CX=0.
D) Loop Instructions: -
1) LOOP: – Loop Unconditionally
i) Syntax: - LOOP Label
ii) This instruction executes the part of the program from the label or address
specified in the instruction up to the LOOP instruction, CX number of times.
iii) At each iteration, CX is decremented automatically. This instruction implements
DECREMENT COUNTER and JUMP IF NOT ZERO structure.
iv) No flags are affected by this instruction.
Example: -
MOV CX, 0005 ; Number of times in CX
MOV BX, 1234H ; Data to BX
LABEL: MOV AX, CODE1
OR BX, AX
AND DX,
AX LOOP
LABEL
In the above example, the part of a program from label LABEL up to the LOOP
instruction is executed repeatedly until the count in CX become zero.

2) LOOPZ/LOOPE: – Loop While Zero/Loop While Equal

i) Syntax: - LOOPZ/LOOPE Label
ii) The LOOPZ/LOOPE instruction is a conditional loop instruction and these
types of instructions are used for implementing structures like DO_WHILE,
REPEAT_UNTIL, etc.
iii) This instruction, after execution implements the loop structure from the
specified label up to the LOOPZ/LOOPE instruction while ZF=1 and CX≠0.
3) LOOPNZ/LOOPNE: – Loop While Not Zero/Loop While Not Equal

i) Syntax: - LOOPNZ/LOOPNE Label
ii) This instruction, after execution implements the loop structure from the
specified label up to the LOOPNZ/LOOPNE instruction while ZF=0 and CX≠0.
E) Machine (Processor) Control Instructions: -

1) WAIT: – Wait for Test Signal or Interrupt Signal
i) Syntax: - WAIT
ii) The WAIT instruction when executed holds the operation of processor with the
current status till the logic level on the TEST pin goes low.
iii) The processor goes on inserting WAIT states in the instruction cycle, till the
TEST pin goes low.
iv) Once the TEST pin goes low, the processor continues further execution.
2) HLT: – Halt Processing

i) Syntax: - HLT
ii) The HLT instruction will cause the 8086 to stop fetching and executing
instructions. The 8086 will enter into a halt state.
iii) Two ways to pull out the processor from the halt state are to reset the processor
by the signal on the RESER input pin or to interrupt the processor by the
interrupt signal on the INTR pin or NMI pin.

3) NOP: – No Operation
i) Syntax: - NOP
ii) When NOP instruction is executed, the processor does not perform any
operation till 4 clock cycles, except incrementing the IP by one.
iii) It then continues with further execution after 4 clock cycles. No flags are
4) ESC: – Escape
i) Syntax: - ESC
ii) This instruction is used to pass instruction to a coprocessor, such as the 8087
math coprocessor which shares the address and data bus with an 8086.
iii) When ESC instruction executes, 8086 frees the bus for an external master like
coprocessor or peripheral devices.
5) LOCK: – Assert Bus Lock Signal

i) Syntax: - LOCK
ii) The LOCK prefix allows a microprocessor to make sure that another processor
does not take control of the system bus till the lock prefixed instruction is
executed completely.
F) Flag Manipulation Instructions: -

1) CLC: – Clear the Carry Flag
i) Syntax: - CLC
ii) The CLC instruction resets the carry flag to 0 i.e. CF=0. No other flags are
2) CMC: – Complement the Carry Flag

i) Syntax: - CMC
ii) The CMC instruction is used to complement the content of the carry flag. No
other flags are affected by this instruction.

iii) If the carry flag is 0 before this instruction, it will be set to 1 after the instruction
executes.
iv) If the carry flag is 1 before this instruction, it will be reset to 0 after the
instruction executes.
3) STC: – Set the Carry Flag to a 1

i) Syntax: - STC
ii) The STC instruction sets the carry flag to 1 i.e. CF=1. No other flags are
4) CLD: – Clear Direction Flag

i) Syntax: - CLD
ii) The CLD instruction resets the direction flag to 0 i.e. DF=0. No other flags are
iii) If direction flag is reset, SI and DI will automatically be incremented when one
of the string instructions, such as MOVS, CMPS, or SCAS, executes.
5) STD: – Set the Direction Flag to a 1

i) Syntax: - STD
ii) The STD instruction sets the direction flag to 1 i.e. DF=1. No other flags are
iii) If the direction flag is set, SI and/or DI will be decremented by 1 for byte
strings, and by 2 for word strings.
6) CLI: – Clear Interrupt Flag

i) Syntax: - CLI
ii) The CLC instruction resets the interrupt flag to 0 i.e. IF=0. No other flags are
iii) If the interrupt flag is reset, the 8086 will not respond to an interrupt signal on
its INTR input pin.

7) STI: – Set the Interrupt Flag

i) Syntax: - STI
ii) The STI instruction sets the interrupt flag to 1 i.e. IF=1. No other flags are
iii) Setting the interrupt flag to 1 enables the INTR interrupt input of the 8086.
iv) When the INTR input is enabled, an interrupt signal on this input will then
cause the 8086 to interrupt program execution, push the return address and flags
on the stack, and executes an interrupt service routine.
G) Shift and Rotate Instructions: -

a) Shift Instructions: -
1) SHL/SAL: – Shift Logical/Arithmetic Left
i) Syntax: - SHL/SAL Destination, Count
ii) These instructions shift the operand word or byte bit by bit to the left either by 1
or by the count specified in the CX/CL register and insert zeros in the newly
introduced least significant bits.
iii) MSB bit shifted into the carry flag and remaining bits are shifted towards left by
one bit position.
iv) In case of all the SHIFT and ROTATE instructions, the count is either 1 or
specified by register CX/CL. All flags are affected depending upon the result.
v) The destination operand may be a register or a memory location but it cannot be
an immediate data.
Example: -
MOV CL, 02 ; Move 02 count in CL register
SHL/SAL AX, CL ; Shift content of AX by 2 bit position
Suppose AX=1234H, then after execution, the contents are as follows
Bits C 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
F
Operand 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0
Result 1st 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 inserted
Result 2nd 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 0 inserted

2) SHR: – Shift Logical Right

i) Syntax: - SHR Destination, Count
ii) This instruction shift the operand word or byte bit by bit to the right either by 1
or by the count specified in the CX/CL register and insert zeros in the newly
introduced most significant bits.
iii) LSB bit shifted into the carry flag and remaining bits are shifted towards right
by one bit position. All flags are affected depending upon the result.
iv) The destination operand may be a register or a memory location but it cannot be
an immediate data.
Example: -
SHR AX, CL ; Shift content of AX by 2 bit position Suppose
AX=1234H, then after execution, the contents are as follows
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 C
F
Operand 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0
Result 1st inserted 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0
Result 2nd inserted 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0
3) SAR: – Shift Arithmetic Right

i) Syntax: - SHR Destination, Count
ii) This instruction shift the operand word or byte bit by bit to the right either by 1
or by the count specified in the CX/CL register and insert ones in the newly
introduced most significant bits.
iii) LSB bit shifted into the carry flag and remaining bits are shifted towards right
by one bit position. All flags are affected depending upon the result.
iv) The destination operand may be a register or a memory location but it cannot be
an immediate data.
Example: -
SHR AX, CL ; Shift content of AX by 2 bit position Suppose
AX=1234H, then after execution, the contents are as follows

Bits 15 14 13 12 11 10 9 8 765 4 321 0 CF

Operand 0 00 1 001 0 001 1 0100
Result 1st inserted 1 00 0 100 1 000 1 101 0 0
Result 2nd inserted 1 10 0 010 0 1000 1101 0
b) Rotate Instructions: -
1) ROR: – Rotate Right without Carry
i) Syntax: - ROR Destination, Count
ii) The ROR instruction rotates the contents of the specified destination operand bit
by bit to the right either by one or by the count specified in CL, excluding carry.
iii) The LSB is pushed into the carry flag and simultaneously it is transferred into
the MSB position at each operation. The remaining bits are shifted right by the
specified count positions.
iv) The destination operand can be a register (except a segment register) or a
memory location but it cannot be an immediate data.
v) Only CF and OF are affected by this instruction. The remaining bits are left
unchanged by the rotate operation.
Example: -
ROR AX, CL ; Rotate content of AX by 2 bit position
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CF
Operand 0 001
0 0 0 0 01 00 10 01 00 00 10 11 01 10 01 00 ×
Result 1st
0
Result 2nd 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1
0
2) ROL: – Rotate Left without Carry

i) Syntax: - ROL Destination, Count

ii) The ROL instruction rotates the contents of the specified destination operand bit
by bit to the left either by one or by the count specified in CL, excluding carry.
iii) The MSB is pushed into the carry flag and simultaneously it is transferred into
the LSB position at each operation. The remaining bits are shifted left by the
specified count positions.
Example: -
ROL AX, CL ; Rotate content of AX by 2 bit position
Bits C 15 14 13 12 11 10 9 8 7 6 5 4 321 0
F
Operand 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0
Result 1st 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0
Result 2nd 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 0
3) RCR: – Rotate Right through Carry

i) Syntax: - RCR Destination, Count
ii) The RCR instruction rotates the contents of the specified destination operand bit
by bit to the right either by one or by the count specified in CL through carry
flag bit.
iii) The carry flag bit is pushed into the MSB of the operand, and the LSB is pushed
into carry flag. The remaining bits are shifted right by the specified count
positions.

Example: -
RCR AX, CL ; Rotate content of AX by 2 bit position
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CF
Operand 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 1 0
Result 1st 0 0 0 0 1 0 0 1 0 0 0 1 101 0 1
Result 2nd 1 0 0 0 0 1 0 0 1 0 0 0 110 1 0
4) RCL: – Rotate Left through Carry

i) Syntax: - RCL Destination, Count
ii) The RCL instruction rotates the contents of the specified destination operand bit
by bit to the left either by one or by the count specified in CL through carry flag
bit.
iii) The carry flag bit is pushed into the LSB of the operand, and the MSB is pushed
into carry flag. The remaining bits are shifted left by the specified count
positions.
Example: -
ROR AX, CL ; Rotate content of AX by 2 bit position
Bits C 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Operand F 0 1 0 1 0 0 1 0 0 0 1 1 0 1 0 0
Result 1st 1 1 0 1 0 0 1 0 0 0 1 1 0 1 0 0 1
Result 2nd 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 1 0
1

H) String Instructions: -
1) REP/PEPE/REPZ/REPNE/REPNZ: – Repeat Instruction Prefix
i) Syntax: - REP Instruction
ii) REP is a prefix which is written before one of the string instructions.
iii) The instruction, to which the REP prefix is provided, is executed until the CX
register becomes zero. Flags are affected by this instruction.
iv) At each iteration CX is automatically decremented by one. When CX becomes
zero, the execution proceeds to the next instruction in sequence.
v) REPE and REPZ stand for Repeat if Equal and Repeat if Zero, often used with
the Compare String instruction or with the Scan String instruction.
vi) REPE or REPZ will cause the string instruction to be repeated as long as the
compared bytes or words are equal (ZF=1) and CX is not zero.
vii) REPNE and REPNZ stand for Repeat if Not Equal and Repeat if Not Zero,
often used with the Scan String instruction.
viii) REPNE or REPNZ will cause the string instruction to be repeated until the
compared bytes or words are equal (ZF=1) or until CX=0 (end of string).
Examples: -
1. REP MOVSB
This instruction continues to copy string bytes until CX becomes zero.
2. REPE CMPSB
This instruction compares string bytes until end of string or until string bytes
not equal.
3. REPNE SCASW
This instruction scan a string of words until a word in the string matches the
word in AX or until all of the string has been scanned.
2) MOVS/MOVSB/MOVSW: – Move String Byte or String Word

i) Syntax: - MOVS Destination String Name, Source String Name
ii) This instruction copies a byte or a word from a location in data segment to a
location in the extra segment. No flags are affected by this instruction.

iii) The address of the source string is pointed by DS:SI pair while the address of
the destination string is pointed by ES:DI pair.
iv) The length of the byte string or word string must be stored in CX register. The
REP instruction prefix is used with MOVS instruction to repeat it by a value
given in counter CX.
v) After MOVS instruction is executed once, the index registers are automatically
incremented and CX is decremented. The incrementing or decrementing of the
pointers SI and DI depend upon the direction flag.
vi) If DF=0, the index registers are incremented, otherwise, they are decremented,
in case of all the string manipulation instructions.
Example: -
LEA SI, STR1 ; Load offset of source string in DS into SI
LEA DI, STR2 ; Load offset of destination string in ES into DI
CLD ; Clear direction flag to increment SI and DI
MOV CX, 04H ; Set counter CX by loading length of string
REP MOVSB ; Decrement CX and copy string bytes until CX=0
3) CMPS/CMPSB/CMPSW: – Compare String Bytes or String Words

i) Syntax: - CMPS
ii) The CMPS instruction can be used to compare two strings of bytes or words.
The length of the string must be stored in the register CX.
iii) If both the byte or word strings are equal, zero flag is set i.e. ZF=1. If source
string is greater than destination, carry flag is set i.e. CF=1, else CF=0.
iv) The DS:SI and ES:DI point to the two strings. The REP instruction prefix is
used to repeat the operation till CX becomes zero or the condition specified by
the REP prefix is false.
v) The comparison is done byte by byte, and after each comparison, the index
register are updated depending upon the direction flag and the counter is
decremented.

vi) This byte by byte or word by word comparison continues till a mismatch is
found or a CX becomes zero. When a mismatch is found, the carry and zero
flags are modified appropriately and the execution proceeds further. Example: -
LEA SI, STR1 ; Load offset of source string in DS into SI
LEA DI, STR2 ; Load offset of destination string in ES into DI
CLD ; Clear direction flag to increment SI and DI
REP CMPSB ; Repeat comparison of string bytes until end of
; String or until compared bytes are not equal
4) SCAS/SCASB/SACSW: – Scan String Byte or String Word

i) Syntax: - SCAS
ii) This instruction scans (compares) a string of bytes or words for an operand byte
or word specified in the register AL or AX. The string is pointed to by ES:DI
register pair.
iii) The length of the string is stored in CX. The DF controls the mode for scanning
of the string same as MOVSB instruction.
iv) Whenever a match to the specified operand is found in the string, execution
stops and the zero flag is set i.e. ZF=1. If no match is found, the zero flag is
reset i.e. ZF=0.
v) The REPNE prefix is used with the SCAS instruction. The pointers and counters
are updated automatically, till a match is found.
Example: -
LEA DI, STR2 ; Load offset of string in ES into DI
MOV AL, 0DH ; Byte to be scanned for into AL
CLD ; Clear direction flag to increment DI
REPNE SCAS STR2 ; Comparison byte in string with byte in AL

5) LODS/LODSB/LODSW: – Load String Byte or String Word

i) Syntax: - LODS
ii) The LODS instruction loads the AL/AX register by the content of a string
pointed to by DS:SI register pair. The SI is modified automatically depending
upon DF. No flags are affected by this instruction.
iii) If DF=0, then for byte transfer (LODSB), the SI is incremented by one, and for
word transfer (LODSW), the SI is incremented by two.
iv) If DF=1, then for byte transfer (LODSB), the SI is decremented by one, and for
word transfer (LODSW), the SI is decremented by two.
Example: -
CLD ; Clear direction flag to increment SI
LEA SI, STR ; Load offset of string in DS into SI
LODS STR ; Copy byte or word from string to AL or AX
6) STOS/STOSB/STOSW: – Store String Byte or String Word

i) Syntax: - STOS
ii) The STOS instruction stores the AL/AX register contents to a location in the
string pointed by ES:DI register pair. The DI is modified automatically
depending upon DF. No flags are affected by this instruction.
iii) If DF=0, then for byte string (STOSB), the DI is incremented by one, and for
word string (STOSW), the DI is incremented by two.
iv) If DF=1, then for byte string (STOSB), the DI is decremented by one, and for
word string (STOSW), the DI is decremented by two.
Example: -
CLD ; Clear direction flag to increment SI
LEA DI, STR ; Load offset of string in DS into SI
STOSB ; Copy byte from AL to string in DI
References: The contents and diagrams for notes preparation are taken from
1) Douglas V. Hall, Microprocessors and Interfacing, Second Edition, Tata McGraw Hill publications.
2) A. K. Ray, K. M. Bhurchandi, Advanced Microprocessors and Peripherals, Second Edition, Tata McGraw
Hill Publications.

Unit - Iii Instruction Set of 8086 Microprocessor: (16 - Marks)

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Unit - Iii Instruction Set of 8086 Microprocessor: (16 - Marks)

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I – Scheme Microprocessors (22415) SEM IV

Machine Language Instruction Format: -

NEXT: ADD AL , ; Add the contents of AL & BL register

Label Opcode Destination Source Comment

Prof. Ratna S. Patil Page No. 1

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2) Comments do not form the part of the machine language program.

1) One Byte Instruction: -

1) This format is two bytes long.

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3) Register to / from Memory with no Displacement: -

4) Register to / from Memory with Displacement: -

5) Immediate Operand to Register: -

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6) Immediate Operand to Memory with 16 bit Displacement: -

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ii) The register specified by REG is source operand if D=0, else, it is a

Addressing Modes of 8086: -

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A) Sequential Control Flow Instructions: -

a) Immediate Addressing Mode: -

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b) Direct Addressing Mode: -

c) Register Addressing Mode: -

d) Register Indirect Addressing Mode: -

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4) In the above example, data is present in a memory location in DS whose offset

e) Indexed Addressing Mode: -

f) Register Relative Addressing Mode: -

g) Based Indexed Addressing Mode: -

Prof. Ratna S. Patil Page No. 9

h) Relative Based Indexed Addressing Mode: -

B) Control Transfer Instructions: -

Prof. Ratna S. Patil Page No. 10

Modes for Control Transfer Instructions

Intersegment Intersegment Intrasegment Intrasegment

Direct Indirect Direct Indirect

Figure: - Addressing Modes for Control Transfer Instructions.

i) Intrasegment Direct Addressing Mode: -

ii) Intrasegment Indirect Addressing Mode: -

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iii) Intersegment Direct Addressing Mode: -

iv) Intersegment Indirect Addressing Mode: -

Instruction Set of 8086: -

B) Arithmetic and Logical Instructions: -

C) Branch Instructions (Control Transfer Instructions): -

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E) Machine (Processor) Control Instructions: -

F) Flag Manipulation Instructions: -

G) Shift and Rotate Instructions: -

Now let us see the instructions of each category in detail.

A) Data Copy / Transfer Instructions: -

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iv) The source can be a register, a memory location or an immediate number

2) PUSH: – Push to Stack

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3) POP: – Pop from Stack

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5) IN: – Input the Port

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6) OUT: – Output to the Port

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8) LEA: – Load Effective Address