AL-BAHA UNIVERSITY ‫ﺟﺎﻣﻌﺔ اﻟﺒﺎﺣـﺔ‬

FACULTY OF ENGINEERING ‫ﻛﻠﻴﺔ اﳍﻨﺪﺳـﺔ‬

Electrical Engineering Department ‫ﻗﺴﻢ اﳍﻨﺪﺳﻪ اﻟﻜﻬﺮ ﺋﻴﺔ‬
MID-TERM EXAM.
Course: EENG1755_Embedded Systems Date: 3/7/1444 H Marks: 20 Time: 90 min.

:‫اﻟﺪرﺟﺔ‬............................. :‫اﻟﺮﻗﻢ اﻟﺠﺎﻣﻌﻲ‬ ..........:‫اﻟﻤﺠﻤﻮﻋﺔ‬................................... :‫اﺳﻢ اﻟﻄﺎﻟﺐ‬

Question 1: Multiple choice (7Marks)
1. CISC stands for ____________
a) Complex Information Sensed CPU b) Complex Instruction Set Computer
c) Complex Intelligence Sensed CPU d) none of the mentioned
2. If M denotes the number of memory locations and N denotes the word size, then an expression that
denotes the storage capacity is ______________
a) M*N b) M+N c) 2M+N d) 2M-N
3. Whenever the data is found in the cache memory it is called as _________
a) HIT b) MISS c) FOUND d) ERROR
4. Brain of computer is ____________
a) Central Processing Unit b) Memory c) Control unit d) Arithmetic and Logic unit
5. Which memory storage is widely used in PCs and Embedded Systems?
a) EEPROM b) Flash memory c) SRAM d) DRAM
6. Name a volatile memory.
a) RAM b) EPROM c) ROM d) EEPROM
7. What is approximate data access time of SRAM?
a) 2ms b) 10ns c) 60ns d) 4ns
8. Which of the following is the common method for connecting the peripheral to the processor?
a) software b) exception c) external interrupts d) polling
9. Which can activate the ISR?
a) interrupt b) function c) procedure d) structure
10. What does ISR stand for?
a) interrupt standard routine b) interrupt service routine
c) interrupt software routine d) interrupt synchronous routine
11. Which of the following statements are true for von Neumann architecture?
a) separate bus between the program memory and data memory
b) external bus for program memory and data memory
c) external bus for data memory only
d) shared bus between the program memory and data memory
12. How a software interrupt is created?
a) instruction set b) sequential code c) concurrent code d) porting
13. If the address bus width (in bits) for a certain microprocessor is 19, the number of memory
locations that can be accessed by this microprocessor is -----.
a) 1M bytes b) 64K bytes c) 512K bytes d) None of the choices are correct
14. The maximum number of memory locations that can be accessed by a microprocessor is determined
by the number of bits in its -----.
a) control bus b) data bus c) accumulator d) None of the choices are correct
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Question 2(Memory Interface):
I. An embedded system uses a memory unit with 512K words of 16 bits each. A binary instruction
code is stored in two word of memory. The instruction has three parts: an operation code, a register
code part to specify one of 128 registers, and an address part.
a) How many bits are there in the operation code, the register code part, and the address part?
Address Register Code Operation Code

b) Draw the instruction word format and indicate the number of bits in each part.

II. An embedded system employs RAM chips of 1024 x 8 and ROM chips of 256 x 8. The system
needs 2K bytes of RAM and 512 bytes of ROM. The module should be connected on an 8-bit
processor with a 16-bit address bus, and occupy the address range starting from the address 1000H
for RAM and 8000H for ROM.
a) How many RAM and ROM chips are needed?
(Number) RAM (Number) ROM

b) How many lines of the address bus must be used to RAM and ROM memory access?
(Address bus) RAM (Address bus) ROM

c) How many lines of the address bus must be decoded for RAM and ROM chip select? Specify
the size of the decoders.
(Decoder) RAM (Decoder) ROM

d) Give the address range in hexadecimal for RAM and ROM.

A15 A14 A13 A12 A11 A10 A9 A8 A7………..A0 Mem. Map

Question 3 (Interrupt):
a) Using the Interrupt Vector Table shown below, determine the address of the ISR of a device
with interrupt vector 65. 0 1 2 3 4 5 6 7 8 9 A B C D E F
00000 3C 22 10 38 6F 13 2C 2A 33 22 21 67 EE F1 32 25
00010 11 3C 32 88 90 16 44 32 14 30 42 58 30 36 34 66
......... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ...
00100 4A 33 3C 4A AA 1A 1B A2 2A 33 3C 4A AA 1A 3E 77
00110 C1 58 4E C1 4F 11 66 F4 C5 58 4E 20 4F 11 F0 F4
......... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ...
00250 00 10 10 20 3F 26 33 3C 20 26 20 C1 3F 10 28 32
00260 20 4E 00 10 50 88 22 38 10 5A 38 10 4C 55 14 54
......... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ...
003E0 3A 10 45 2F 4E 33 6F 90 3A 44 37 43 3A 54 54 7F
003F0 22 3C 80 01 3C 4F 4E 88 22 3C 50 21 49 3F F4 65

b) Which interrupts are generally used for critical events?

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 AL-BAHA UNIVERSITY ‫ﺟﺎﻣﻌﺔ اﻟﺒﺎﺣـﺔ‬
FACULTY OF ENGINEERING ‫ﻛﻠﻴﺔ اﳍﻨﺪﺳـﺔ‬
Electrical Engineering Department ‫ﻗﺴﻢ اﳍﻨﺪﺳﻪ اﻟﻜﻬﺮ ﺋﻴﺔ‬
MID-TERM EXAM-Sol..
Course: EENG1755_Embedded Systems Date: 3/7/1444 H Marks: 20 Time: 90 min.

:‫اﻟﺪرﺟﺔ‬............................. :‫اﻟﺮﻗﻢ اﻟﺠﺎﻣﻌﻲ‬ ..........:‫اﻟﻤﺠﻤﻮﻋﺔ‬................................... :‫اﺳﻢ اﻟﻄﺎﻟﺐ‬

Question 1: Multiple choice (7Marks)

1. CISC stands for ____________
a) Complex Information Sensed CPU b) Complex Instruction Set Computer
c) Complex Intelligence Sensed CPU d) none of the mentioned
2. If M denotes the number of memory locations and N denotes the word size, then an expression that
denotes the storage capacity is ______________
a) M*N b) M+N c) 2M+N d) 2M-N
3. Whenever the data is found in the cache memory it is called as _________
a) HIT b) MISS c) FOUND d) ERROR
4. Brain of computer is ____________
a) Central Processing Unit b) Memory c) Control unit d) Arithmetic and Logic unit
5. Which memory storage is widely used in PCs and Embedded Systems?
a) EEPROM b) Flash memory c) SRAM d) DRAM
6. Name a volatile memory.
a) RAM b) EPROM c) ROM d) EEPROM
7. What is approximate data access time of SRAM?
a) 2ms b) 10ns c) 60ns d) 4ns
8. Which of the following is the common method for connecting the peripheral to the processor?
a) software b) exception c) external interrupts d) polling
9. Which can activate the ISR?
a) interrupt b) function c) procedure d) structure
10. What does ISR stand for?
a) interrupt standard routine b) interrupt service routine
c) interrupt software routine d) interrupt synchronous routine
11. Which of the following statements are true for von Neumann architecture?
a) separate bus between the program memory and data memory
b) external bus for program memory and data memory
c) external bus for data memory only
d) shared bus between the program memory and data memory
12. How a software interrupt is created?
a) instruction set b) sequential code c) concurrent code d) porting
13. If the address bus width (in bits) for a certain microprocessor is 19, the number of memory
locations that can be accessed by this microprocessor is -----.
a) 1M bytes b) 64K bytes c) 512K bytes d) None of the choices are correct
14. The maximum number of memory locations that can be accessed by a microprocessor is determined
by the number of bits in its -----.
a) control bus b) data bus c) accumulator d) None of the choices are correct

‫ﻣﻊ ﺗﻤﻨﯿﺎﺗﻲ ﺑﺎﻟﺘﻮﻓﯿﻖ‬ 3/2

 Question 2(Memory Interface): (4+5(7)=9Marks)
I. An embedded system uses a memory unit with 512K words of 16 bits each. A binary instruction
code is stored in two word of memory. The instruction has three parts: an operation code, a register
code part to specify one of 128 registers, and an address part.
a) How many bits are there in the operation code, the register code part, and the address part?
Address Register Code Operation Code
512K=219 19 bits 128=27 7bits 32-26= 6bits
b) Draw the instruction word format and indicate the number of bits in each part.
6 7 19

II. An embedded system employs RAM chips of 1024 x 8 and ROM chips of 256 x 8. The system
needs 2K bytes of RAM and 512 bytes of ROM. The module should be connected on an 8-bit
processor with a 16-bit address bus, and occupy the address range starting from the address 1000H
for RAM and 8000H for ROM.
a) How many RAM and ROM chips are needed?
(Number) RAM (Number) ROM
2K/1024 = 211 /210=2 512/256 = 2
b) How many lines of the address bus must be used to RAM and ROM memory access?
(Address bus) RAM (Address bus) ROM
10 ⇒ (A0...A9) 8 ⇒ (A0...A7)
c) How many lines of the address bus must be decoded for RAM and ROM chip select? Specify
the size of the decoders.
(Decoder) RAM (Decoder) ROM
1X2 ⇒ (A10) 1X2 ⇒ (A8)
d) Give the address range in hexadecimal for RAM and ROM.
A15…..A12 A11 A10 A9 A8 A7………..A0 Mem. Map
0 0 0 1 0 0 x x x ………. x RAM1: 1000-13FF
0 0 0 1 0 1 x x x ………. x RAM2: 1400-17FF
1 0 0 0 0 0 0 0 x ………. x ROM1: 8000-80FF
1 0 0 0 0 0 0 1 x ………. x ROM2: 8100-81FF
Question 3 (Interrupt): (5Marks):
Using the Interrupt Vector Table shown below, determine the address of the ISR of a device with
interrupt vector 65. 0 1 2 3 4 5 6 7 8 9 A B C D E F
00000 3C 22 10 38 6F 13 2C 2A 33 22 21 67 EE F1 32 25
00010 11 3C 32 88 90 16 44 32 14 30 42 58 30 36 34 66
......... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ...
00100 4A 33 3C 4A AA 1A 1B A2 2A 33 3C 4A AA 1A 3E 77
00110 C1 58 4E C1 4F 11 66 F4 C5 58 4E 20 4F 11 F0 F4
......... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ...
00250 00 10 10 20 3F 26 33 3C 20 26 20 C1 3F 10 28 32
00260 20 4E 00 10 50 88 22 38 10 5A 38 10 4C 55 14 54
......... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ...
003E0 3A 10 45 2F 4E 33 6F 90 3A 44 37 43 3A 54 54 7F
003F0 22 3C 80 01 3C 4F 4E 88 22 3C 50 21 49 3F F4 65

Answer: Address in table = 4 X 41H = 104H (Multiply by 4 since each entry is 4 bytes) (1)
• Offset Low = [118] =AAH, Offset High = [119] =1AH (1)
• Segment Low = [11A] = 1BH, Segment High = [11B] = A2H (1)
• Address = A21B:1AAA = A21BH+1AAAH = A3C5A H (1)
Which interrupts are generally used for critical events?
Ans. Non-Maskable interrupts are used in critical events. Such as Power failure, Emergency, Shut off etc.
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