PIN DIAGRAM

MEMORY SEGMENTATION
AND INTERFACING
[ECEg 4161] – Microcomputer and interfacing

Presented by: Mr. Shadab Ahmad

Assistant Professor
Department of Electrical and Computer Engineering
Samara University
8086 Microprocessor
Pins and Signals Common signals

AD0-AD15 (Bidirectional)

Address/Data bus

Low order address bus; these are

multiplexed with data.

When AD lines are used to transmit

memory Address the symbol A is used
instead of AD, for example A0-A15.

When Data are transmitted over AD lines

the symbol D is used in place of AD, for
example D0-D7, D8-D15 or D0-D15.

A16/S3, A17/S4, A18/S5, A19/S6

High order address bus. These are

multiplexed with status signals.

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8086 Microprocessor
Pins and Signals Common signals

𝐁𝐇𝐄 (Active Low)/S7 (Output)

Bus High Enable/Status

BHE stands for Bus High Enable. It is

used to indicate the transfer of data
using data bus D8-D15. BHE is Active
Low signal.
It is multiplexed with status signal S7.

MN/𝐌𝐗
MINIMUM/MAXIMUM
This pin signal indicates what mode the
processor is to operate in. When it is
high, it works in the minimum mode and
vice-versa.

𝐑𝐃 (Read-Active Low)
The signal is used for read operation.
It is an output signal.
It is active when low.
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8086 Microprocessor
Pins and Signals Common signals

𝐓𝐄𝐒𝐓

𝐓𝐄𝐒𝐓 input is tested by the ‘WAIT’

instruction.

This signal is like wait state and is

available at pin 23. When this signal is
high, then the processor has to wait for
IDLE state, else the execution continues.

This is used to synchronize an external

activity to the internal operation.

READY

This is the acknowledgement from the

slow device or memory that they have
completed the data transfer.

The signal is active high.

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8086 Microprocessor
Pins and Signals Common signals

RESET

Causes the processor to immediately

terminate its present activity.

The signal must be active HIGH.

CLK

It provides timing to the processor for

operation and bus control activity.

INTR (Interrupt Request)

This is sampled during the last clock

cycles of each instruction to determine
the availability of the request.

This signal is active high.

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MIN/ MAX PINS

MINIMUM MODE
AND
MAXIMUM MODE

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8086 Microprocessor
Pins and Signals Min/ Max Pins

The 8086 microprocessor can work in two

modes of operations : Minimum mode and
Maximum mode.

When this pin is high 8086 operates in

Minimum mode otherwise it operates in
Maximum mode.

In the minimum mode of operation the

microprocessor do not associate with any
co-processors and can not be used for
multiprocessor systems.

In the maximum mode the 8086 can work

in multi-processor or co-processor
configuration.

Minimum or maximum mode operations

are decided by the pin MN/ MX (Active low
or high).

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8086 Microprocessor
Pins and Signals Minimum mode signals

*The transreceiver is a Pins 24 -31

device used to separate data
from the address/data bus.
For minimum mode operation, the MN/ 𝐌𝐗 is tied
to VCC (logic high)

8086 itself generates all the bus control signals

DT/𝐑 (Data Transmit/ Receive) Output signal from the

processor to control the direction of data flow
through the data transceivers*

𝐃𝐄𝐍 (Data Enable) Output signal from the processor

used as output enable for the transceivers*

ALE (Address Latch Enable) Used to de-multiplex the

address and data lines using external latches.

M/𝐈𝐎 Used to differentiate memory access and I/O

access. For memory instructions, it is high.
For I/O instructions, it is low.

𝐖𝐑 Write control signal; asserted low whenever

processor writes data to memory or I/O port.

𝐈𝐍𝐓𝐀 (Interrupt Acknowledge) When the interrupt

request is accepted by the processor, the signal is
low.
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8086 Microprocessor
Pins and Signals Minimum mode signals

Pins 24 -31

For minimum mode operation, the MN/ 𝐌𝐗 is tied

to VCC (logic high)

8086 itself generates all the bus control signals

HOLD This signal indicates to the processor that

external devices are requesting to access
the address/data buses.

Usually used by the DMA controller to get the

control of the A/D buses.

HLDA (Hold Acknowledge)

This signal acknowledges the HOLD signal.

The acknowledge is high, when the

processor accepts HOLD signal.

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8086 Microprocessor
Pins and Signals Maximum mode signals

During maximum mode operation, the MN/ 𝐌𝐗 is

grounded (logic low)

Pins 24 -31 are reassigned

𝑺𝟎 Status signals; provided the status of

𝑺𝟏 operation, which is used by the Bus
𝑺𝟐 Controller to generate memory & I/O
control signals.

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8086 Microprocessor
Pins and Signals Maximum mode signals

During maximum mode operation, the MN/ 𝐌𝐗 is

grounded (logic low)

Pins 24 -31 are reassigned

𝑸𝑺𝟎 (Queue Status)

𝑸𝑺𝟏 These signals provide the status of
instruction queue in microprocessor.

The output on QS0 and QS1 can be

interpreted as shown in the table.

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8086 Microprocessor
Pins and Signals Maximum mode signals

During maximum mode operation, the MN/ 𝐌𝐗 is

grounded (logic low)

Pins 24 -31 are reassigned

𝐑𝐐/𝐆𝐓𝟎 These are the Request/Grant signals

𝐑𝐐/𝐆𝐓𝟏 used by the other processors Requesting
the CPU to release the system bus.

When the signal is received by CPU, then

it sends acknowledgment Grant.

𝐑𝐐/𝐆𝐓𝟎 has a higher priority than 𝐑𝐐/𝐆𝐓𝟏

𝐋𝐎𝐂𝐊 When this signal is active, it indicates to

the other processors not to ask the CPU
to leave the system bus

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 MEMORY
SEGMENTATION

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 What is Memory Segmentation?

It is a process in which the main memory of

Computer is divided in to different segments and
each segment has its own base address.

Segmentation is used to increase the execution

speed of computer system so that the processor
can able to fetch and execute the data from
memory easily and fastly.

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Memory Segmentation

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16
Memory Segmentation

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INTERFACING
 INTERFACING
Interface is the path for communication between two components.
Interfacing is of two types, memory interfacing and I/O interfacing.

1. Memory Interfacing:
 When we are executing any instruction, we need the microprocessor to access
the memory for reading instruction codes and the data stored in the memory.
For this, both the memory and the microprocessor requires some signals to read
from and write to registers.
 The interfacing circuit therefore should be designed in such a way that it
matches the memory signal requirements with the signals of the
microprocessor.
2. I/O Interfacing:
 There are various communication devices like the keyboard, mouse, printer,
etc. So, we need to interface the keyboard and other devices with the
microprocessor by using latches and buffers. This type of interfacing is known
as I/O interfacing.
Interfacing of memory & I/O
to Microprocessor

Fig: Block Diagram of Memory and I/O Interfacing

I/O Interface with 8086 Microprocessor

 The I/O (Input/Output) interface permits the microprocessor

to communicate with the outside world.

 In the 8086 microprocessor, I/O devices are connected via

the control, address and data buses and the mechanism is
similar to the memory interface.

 Data transfer takes place over the multiplexed address/data

buses.

 In addition to memory, a computer system must also provide

interfaces with other external devices (I/O devices), such as
display unit, keyboard etc.
 Interfacing of memory & I/O
to Microprocessor

Fig: Block Diagram of Memory and I/O Interface with 8086 microprocessor
 I/O Interface with 8086 Microprocessor

 The last figure shows how the memory and I/O devices are
connected to the system.

As you can see the major difference between connection to a

memory and connecting to I/O devices is the signal level of M/IO.

When accessing memory devices M/IO is ‘1’

While M/IO is ‘0’ when accessing I/O devices
Minimum mode 8086 system I/O interface
8255A - Programmable Peripheral Interface

 8255-PPI (programmable
peripheral interface) is a
programmable I/O device
that acts as interface between
peripheral devices and the
microprocessor for parallel
data transfer.
 8255 PPI is programmed in a
way such as to transfer data in
different conditions according
to the need of the system.
 A1 A0 Port Selection
0 0 Port A
0 1 Port B
1 0 Port C (U/L)
1 1 Control Register

Note : -
 There is no separate selection for Port C (Upper) or Port C (Lower).
 Port C is selected as a whole i.e. Both ports upper (U) and lower (L)
ports are selected when A1= 1, and A0 = 0
8255 PPI – 8086 Interfacing - 8 Bit I/O

RD RD
control bus WR A0-A7
WR
8255 B0-B7
8086 Data bus
D0
D7 PPI
µP C4-C7 (U)
Address bus A0
M / IO A1 C0-C3 (L)
CS

EN Decoder

Fig: Interfacing the 8255 PPI to the 8086 microprocessor