MICROPROCESSOR SYSTEMS AND

INTERFACING (EEE342)

Dr. Omer Chughtai

EE Dept. CUI/Wah
8086 VS 8088 MICROPROCESSORS

8086 MICROPROCESSOR 8088 MICROPROCESSOR

The data bus is of 16 bits The data bus is of 8 bits

It has 3 available clock speeds It has 2 available clock speeds

(5 MHz, 8 MHz, and 10 MHz) (5 MHz, 8 MHz)

The memory capacity is implemented as a single

The memory capacity is 512 kB
1 M x 8 memory banks

It has complemented memory control pin

It has memory control pin (M/IO) signal
(IO/M) signal of 8086

It has Bank High Enable (BHE) signal It has Status Signal (SSO)

It can read or write either 8-bit or 16-bit at the

It can read/write 8-bit at the same time
same time

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GENERAL BUS OPERATION
 The 8086 multiplexed address and data bus
 The bus can be de-multiplexed using a few latches and transceivers

 The negative edge of the ALE pulse is used to separate the address and
the data or status information
 In maximum mode, the status lines S0, S1 and S2 are used to indicate the
type of operation
 Status bits S3 to S7 are multiplexed with higher order address bits and the
BHE signal.
 Address is valid during T1 while status bits S3 to S7 are valid during T2
through T4.

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THE 8088 AND 8086 MICROPROCESSORS (CONT.)

Pin layout of the 8086 and 8088 microprocessor

MINIMUM-MODE AND MAXIMUM-MODE SYSTEM (CONT.)

Common Pin functions

Most pins are independent and serve a single function
Examples:
• CLK—clock
• INTR—interrupt request
• READY—bus ready

Some multi-functions pins–different times/different mode

Examples:
• AD0-AD15– multiplexed address/data lines at different times
• A16/S3—multiplexed address and status line at different
times
• IO/M or S2 Control line in one mode or bus status line in other mode

Signals common to both minimum and maximum mode

TWO OPERATING MODES OF 8088/8086.

• Minimum mode—small system/single processor configuration

• Maximum mode—large system single multi-processor configuration
• Hardware connection at MN/MX pin 33 selects mode
• 1 = +Vcc = Minimum mode
• 0 = GND = Maximum mode
• 8088 signals/pins categorized as
• Common—same function both modes
Examples: Pin 9 (AD7)- pin 16 (AD0)
• Minimum Mode—special minimum mode operations
Examples: pins 26-28 are DEN, DT/R, and IO/M
• Maximum Mode—special maximum mode operations
Example: pins 26-28 are S0, S1, and S2.
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MINIMUM-MODE AND MAXIMUM-MODE SYSTEM (CONT.)

Unique minimum-mode signals

MINIMUM-MODE AND MAXIMUM-MODE SYSTEM (CONT.)

Address bus status codes

Unique maximum-mode signals

MINIMUM MODE INTERFACE
 Block diagram of the minimum-mode 8086 and 8088 MPU

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MINIMUM-MODE INTERFACES– 8088 INTERFACE
 MPU provides all of the interface signals
 Address/data bus
 Status
 Control
 Interrupt
 DMA
 Multiplexed address/data bus
 20-bit address (A19-A0) 1MByte address space
 8-bit data bus (D7-D0)
 Signals of the address/data bus
 AD0-AD7
 Lower 8 address output lines
 8 bi-directional data bus lines
 A8-A15
 Next 8 address lines
 A16/S3-A19/S6
 Four most significant address lines
 S3–S6 status signals

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MEMORY/IO CONTROL SIGNALS

o Support signals for controlling the memory

 RD* = read active 0
and I/O interface circuitry
 Signalsthat a read/input bus cycle is in
• All but READY are outputs
progress
o ALE= address latch enable
• Signals external circuitry that a valid address in on the address
 WR* = write active 0
bus and it should be latched  Signals that a write/output bus
o IO/M* = IO/memory cycle is in progress
o Identifies type of data transfer taking place over the data bus;  DEN* = data enable active 0
used to enable/disable memory and/or IO
 Signal when the data bus should be enabled
interface
o IO/M* = 1 = input/output data  READY = ready
 1= Acknowledges that the memory
o IO/M* = 0 = memory data
subsystem is ready to complete the bus cycle
o DT/R* = data transmit/receive  0= Memory subsystem is not ready; insert
o Tells external circuitry which way data is to be transferred over
wait sates to extend the bus cycle
the bus; used to set direction of data bus interface
circuits  SSO* = status
o DT/R* = 1 = transmit mode(write/output)  0= instruction code read
 1= data access
o DT/R* = 0 = read mode (read/input)

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 INTERRUPT INTERFACE
 Support signals for implementing an interrupt
driven I/O interface
 Maskable interrupt interface—INTR and
INTA*
 Nonmaskable interrupt interface—NMI
 Reset interface—RESET
 INTR = interrupt request input active 1 (level
triggered)
 Externaldevice signals the MPU that it needs
maskable interrupt service
 INTA* = interrupt acknowledge output active 0
 MPU acknowledges to an external devices that its
maskable interrupt request is being serviced
 NMI = nonmaskable interrupt input
 External device initiates NMI request with 0 to 1
transition (edge triggered)
 RESET = reset input, active 1
 Logic 1 initiates hardware reset of MPU
 Initializes internal registers and reset
service routine
DMA INTERFACE
 Support signals for implemented a direct
memory access interface
 Permits direct transfer of
information between parts of
memory or between memory
and I/O devices.
 External devices, such as a DMA controller,
perform these operations independent of MPU
 HOLD= Hold request input active 1 (level
triggered)
 External device request the MPU give it
control of the system bus
 HOLDA* = Hold acknowledge output
active 1
 MPU tri-states its bus lines
 Acknowledges to an external
devices that the MPU bus is in
the hold state
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MINIMUM MODE -8086 INTERFACE
 Data bus (16-bit wide)
 D15-D0
 Multiplexed with A15 through A0
 Allows 3 types of data transfers
 Word—over D15-D0
 Low byte—over D7-D0

 High byte—over D15-D8

 Memory/IO Controls
 SSO*  BHE* (bank high enable)
 Used to signal external circuitry whether or not a byte transfer is taking place
over the upper 8 data bus lines
 A0 now does the same for a byte transfer over the lower 8 data bus
line

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MAXIMUM-MODE INTERFACE

 In
  maximum-mode, MPU does not directly provide all the signals
 , , , ALE, and signals are no longer produced by the 8088
 Three signal lines identifies which type of bus cycle is to follow
 MRDC – Memory Read Command
 MWTC – Memory Write Command
 AMWC – Advanced Memory Write Command

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MAXIMUM-MODE INTERFACE
 8086 and 8088 maximum-mode block diagram

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MAXIMUM-MODE INTERFACE
 8288 bus controller

 Block diagram and pin layout of 8288

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EVEN AND ODD MEMORY BANKS OF 8086
  
Physically (i.e., in the hardware), the 1Mb memory space is divided into
two banks of 512kb (512kb + 512kb = 1Mb). The two memory banks are
called Even (or Lower) bank and Odd (or Upper) bank.
 The data lines D0-D7 are connected to even bank and the data lines D8 -

D15 are connected to odd bank.

 The even memory bank is selected by the address line Ao and the odd
memory bank is selected by the control signal .
 Any memory location in the memory bank is selected by the address line
A1 to A19

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EVEN AND ODD MEMORY BANKS OF 8086
High/Odd Bank Low/Even Bank

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HARDWARE ORGANIZATION OF THE MEMORY ADDRESS
SPACE
 1Mx8 memory bank of the 8088

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HARDWARE ORGANIZATION OF THE MEMORY ADDRESS
SPACE
 High and low memory banks of the 8086

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HARDWARE ORGANIZATION OF THE MEMORY ADDRESS
SPACE
 Byte transfer by the 8088

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HARDWARE ORGANIZATION OF THE MEMORY ADDRESS
SPACE
 Word transfer by the 8088

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HARDWARE ORGANIZATION OF THE MEMORY ADDRESS
SPACE
 Even address byte transfer by the 8086

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HARDWARE ORGANIZATION OF THE MEMORY ADDRESS
SPACE
 Odd address byte transfer by the 8086

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HARDWARE ORGANIZATION OF THE MEMORY ADDRESS
SPACE
 Even address word transfer by the 8086

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HARDWARE ORGANIZATION OF THE MEMORY ADDRESS
SPACE
 Odd-address word transfer by the 8086

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HARDWARE ORGANIZATION OF THE MEMORY ADDRESS
SPACE
 EXAMPLE
 Is the word at memory address 0123116 of an 8086-based microcomputer aligned or
misaligned? How many cycle are required to read it from memory?
 Solution:
 The first byte of the word is the second byte at the aligned-word address 0123016.
Therefore, the word is misaligned and required two bus cycles to be read from
memory.

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EXAMPLES
 Give
  an overview of how a byte of data is read from memory address 0xB0003
of an 8088-based microcomputer, and list the memory control signals along
with their active logic levels that occur during the memory read bus cycle
 Solution:
 Address 0xB0003 is applied over the lines A0 through A19 of the address bus, and a
byte of data is fetched over data bus lines D0 through D7.
 Only one bus cycle is required
 To read a byte from memory. Control signals in minimum mode at the time of the read
are
 A0= 1
 =1

 =0

 =0

 DT/ = 0

 =0

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EXAMPLES
 Give
  an overview of how a word of data is written to memory starting at address
0xA0000 of an 8088-based microcomputer, and list the memory control signals
along with their active logic levels that occur during the memory write bus cycle
 Solution:
 Two bus cycles must take place to write the word of data to memory. During the first bus
cycle, the least significant byte of the word is written to the byte storage location at
address 0xA0000. Next the 8088 automatically increments the address so that it points
to the byte storage location 0xA0001. The most significant byte of the word is written
into this storage location with a second write bus cycle. During both bus cycles, address
information is applied to the memory subsystem over address lines A0 through A19 and
data are transferred over data bus lines D0 through D7. The minimum mode control
signals during the write are:
 =0
 DT/ = 1

 =0

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MEMORY ACCESSED IN 8088 AND 8086

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MEMORY ORGANIZATION

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MEMORY ORGANIZATION

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MEMORY ORGANIZATION

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MEMORY ORGANIZATION

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MEMORY ORGANIZATION

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MEMORY ORGANIZATION

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MEMORY ORGANIZATION

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