Microprocessor Systems

and
Interfacing

• Hardware Specification of 8086/8088

Microprocessors

Slides courtesy:
1. Book ‘The Intel Microprocessors, Architecture,
Programming and Interfacing” , 7ed, by Barry B. Brey
2. http://www.pcpolytechnic.com/computer/ppt/micro/Chap
%203_1.pptx
 Microprocessor Functional blocks

Various conditions of the

Computational Unit;
results are stored as
performs arithmetic and Internal storage of data
status bits called flags in
logic operations
flag register

Register array or Data Bus

internal memory
ALU
Generates the
address of the
Instruction
Flag instructions to be
decoding unit
Register fetched from the
memory and send
through address
bus to the
Timing and memory
control unit PC/ IP

Control Bus Address Bus

Generates control signals for Decodes instructions; sends

internal and external operations information to the timing and
of the microprocessor control unit 2
8086 Microprocessor
Pins and Signals Common signals

Min Mode Pins Max Mode Pins

In the maximum mode,

the microprocessor is
connected with a
coprocessor

The rest of pins are

common in both modes

3
8086 Microprocessor
Pins and Signals Common signals

AD0-AD15 (Bidirectional)

Address/Data bus

Low order address bus; these are

multiplexed with data.

When AD lines are used to transmit

memory address the symbol A is used
instead of AD, for example A0-A15.

When data are transmitted over AD lines

the symbol D is used in place of AD, for
example D0-D7, D8-D15 or D0-D15.
These multiplexed pins are de-
multiplexed using ALE pin

A16/S3, A17/S4, A18/S5, A19/S6

High order address bus. These are

multiplexed with status signals
Status pin S7 is always logic 0, S5
indicates condition of IF, while S4 and
4 S3
identify the current segment.
8086 Microprocessor
Pins and Signals Common signals

BHE (Active Low)/S7 (Output)

Bus High Enable/Status

It is used to enable data onto the most

significant half of data bus, D8-D15. 8-bit
device connected to upper half of the
data bus use BHE (Active Low) signal. It
is multiplexed with status signal S7.
Status S7 is always logic 1.
MN/ MX
MINIMUM / MAXIMUM

This pin signal indicates what mode the

processor is to operate in. When MN/MX
= 1, the minimum mode is selected,
otherwise, maximum mode is selected.

RD (Read) (Active Low)

The signal is used for read operation.

It is an output signal.
It is active when low.
5
8086 Microprocessor
Pins and Signals Common signals

  TEST

input is tested by the ‘WAIT’ instruction.

8086 will enter a wait state after

execution of the WAIT instruction and
will resume execution only when the is
made low by an active hardware.

This is used to synchronize an external

activity to the processor internal
operation.

READY
Used to insert wait state into the timing
of MP. If it is logic 1, the MP enters into
wait state and remains idle. This is the
acknowledgement from the slow device
or memory that they have completed the
data transfer.
The signal made available by the devices
is synchronized by the 8284A clock
generator to provide ready input to the
8086.
The signal is active high. 6
8086 Microprocessor
Pins and Signals Common signals

RESET (Input)

Causes the processor to immediately

terminate its present activity.

The signal must be active HIGH for at

least four clock cycles.

CLK

The clock input provides the basic timing

for processor operation and bus control
activity. Its an asymmetric square wave
with 33% duty cycle.

INTR Interrupt Request

Interrupt request is used to request a

hardware interrupt. This is a triggered
input. It is sampled during the last clock
cycles of each instruction to determine
the availability of the request. If any
interrupt request is pending, the
processor enters the interrupt
acknowledge cycle.
7
8086 Microprocessor
Pins and Signals Min/ Max Pins

The 8086 microprocessor can work in two

modes of operations : Minimum mode and
Maximum mode.

In the minimum mode of operation the

microprocessor do not associate with any
co-processors and can not be used for
multiprocessor systems.

In the maximum mode the 8086 can work

in multi-processor or co-processor
configuration.

Minimum or maximum mode operations

are decided by the pin MN/ MX(Active
low).

When this pin is high 8086 operates in

minimum mode otherwise it operates in
Maximum mode.

8
8086 Microprocessor
Pins and Signals Minimum mode signals

  Pins 24 -31

For minimum mode operation, the MN/ is tied to

VCC (logic high)

8086 itself generates all the bus control signals

DT/ (Data Transmit/ Receive) Output signal from the

processor to control the direction of data flow
through the data transceivers

(Data Enable) Output signal from the processor

used as out put enable for the transceivers

ALE (Address Latch Enable) Used to demultiplex the

address and data lines using external latches

M/ Used to differentiate memory access and I/O

access. For memory reference instructions, it is
high. For IN and OUT instructions, it is low.

Write control signal; asserted low Whenever

processor writes data to memory or I/O port

(Interrupt Acknowledge) When the interrupt

request is accepted by the processor, the output is
low on this line.
9
8086 Microprocessor
Pins and Signals Minimum mode signals

  Pins 24 -31

For minimum mode operation, the MN/ is tied to

VCC (logic high)

8086 itself generates all the bus control signals

HOLD Input signal to the processor form the bus masters

as a request to grant the control of the bus.

Usually used by the DMA controller to get the

control of the bus.

HLDA (Hold Acknowledge) Acknowledge signal by the

processor to the bus master requesting the control
of the bus through HOLD.

The acknowledge is asserted high, when the

processor accepts HOLD.

10
8086 Microprocessor
Pins and Signals Maximum mode signals

  During maximum mode operation, the MN/ is

grounded (logic low)

Pins 24 -31 are reassigned

,, Status signals; used by the 8086 bus controller to

generate bus timing and control signals. These are
decoded as shown.

11
8086 Microprocessor
Pins and Signals Maximum mode signals

  During maximum mode operation, the MN/ is

grounded (logic low)

Pins 24 -31 are reassigned

, (Queue Status) The processor provides the status

of queue in these lines.

The queue status can be used by external device to

track the internal status of the queue in 8086.

The output on QS0 and QS1 can be interpreted as

shown in the table.

12
8086 Microprocessor
Pins and Signals Maximum mode signals

  During maximum mode operation, the MN/ is

grounded (logic low)

Pins 24 -31 are reassigned

Locks peripherals off the system

13
 8086 Vs 8088 Microprocessors

8086 MICROPROCESSOR 8088 MICROPROCESSOR

The data bus is of 16 bits The data bus is of 8 bits
It has 3 available clock It has 2 available clock
speeds speeds
(5 MHz, 8 MHz, and 10 MHz) (5 MHz, 8 MHz)
It has complemented memory
It has memory control pin
control pin (IO/M) signal of
(M/IO) signal
8086
It has Bank High Enable (BHE)
It has Status Signal (SSO)
signal
It can read or write either 8-bit
It can read only 8-bit word at
or 16-bit word at the same
the same time
time

14
The 8088
and 8086
Microproc
essors
(cont.)
 Minimum Mode Interface

• Block diagram of the minimum-mode

8086 and 8088

16
Minimum-Mode Interfaces– 8088 Interface

• MP provides all of the interface signals

– Address/data bus
– Status
– Control
– Interrupt
– DMA
• Multiplexed address/data bus
– 20-bit address (A19-A0) 1MByte address space
– 8-bit data bus (D7-D0)
– Signals of the address/data bus
– AD0-AD7—bi-directional
• Lower 8 address output lines
• 8 bi-directional data bus lines
– A8-A15—output
• Next 8 address lines
– A16/S3-A19/S6—output
• Four most significant address
lines
• S3–S6 status signals
17
Memory/IO Control Signals
o Support signals for controlling
• RD* = read active 0
the memory and I/O interface
– Signals that a read/input bus
circuitry cycle is in progress
• All but READY are outputs
• WR* = write active 0
o ALE= address latch enable
– Signals that a write/output bus
• Signals external circuitry that a valid
address in on the address bus and it
cycle is in progress
should be latched • DEN* = data enable active 0
o IO/M* = IO/memory – Signal when the data bus
o Identifies type of data transfer taking should be enabled
place over the data bus; used to • READY = ready
enable/disable memory and/or IO
– 1= Acknowledges that the
interface
memory subsystem is ready to
o IO/M* = 1 = input/output complete the bus cycle
data – 0= Memory subsystem is not
ready; insert wait sates to
o IO/M* = 0 = memory data extend the bus cycle
o DT/R* = data • SSO* = status
transmit/receive – 0= instruction code read
o Tells external circuitry which way data – 1= data access
is to be transferred over the bus; used
to set direction of data bus interface
circuits 18
 Interrupt Interface
• Support signals for implementing an
interrupt driven I/O interface
– Maskable interrupt interface—INTR and
INTA*
– Nonmaskable interrupt interface—NMI
– Reset interface—RESET
• INTR = interrupt request input
active 1 (level triggered)
– External device signals the MPU that it
needs maskable interrupt service
• INTA* = interrupt acknowledge
output active 0
– MPU acknowledges to an external
devices that its maskable interrupt
request is being serviced
• NMI = nonmaskable interrupt input
– External device initiates NMI request
with 0 to 1 transition (edge triggered)
• RESET = reset input  active 1
– Logic 1 initiates hardware reset of MPU
– Initializes internal registers and reset
service routine
DMA INTERFACE
• Support signals for
implemented a direct
memory access interface
– Permits direct transfer of
information between parts of
memory or between memory
and I/O devices.
– External devices, such as a DMA
controller, perform these
operations independent of MPU
• HOLD= Hold request input
active 1 (level triggered)
– External device request the MPU
give it control of the system bus
• HOLDA* = Hold acknowledge
output active 1
– Acknowledges to an external
devices that the MPU bus is in
the hold state
19
Minimum Mode -8086 Interface

• Data bus (16-bit wide)

– D15-D0
– Multiplexed with A15 through A0
– Allows 3 types of data transfers
• Word—over D15-D0
• Low byte—over D7-D0
• High byte—over D15-D8
• Memory/IO Controls
– SSO* ->BHE* (bank high enable)
• Used to signal external circuitry whether
or not a byte transfer is taking place over
the upper 8 data bus lines

20
 Maximum-Mode Interface

•  signals
• In maximum-mode, MPU does not directly provide all the

• , , , ALE, and signals are no longer produced by the 8088

• Three signal lines identifies which type of bus cycle is to
follow
– MRDC – Memory Read Command
– MWTC – Memory Write Command
– AMWC – Advanced Memory Write Command

21
 Memory Control Signals (cont.)

• Maximum-mode memory control

signals

22
 Maximum-Mode Interface
• 8086 and 8088 maximum-mode
block diagram – 8288 Bus controller

23
 Interfacing Clock Generator
Typical Application of the 8284A for clock and Reset signal generati

frequency, f f/3

2.5 MHz
PCLK
Grounded when f/6
Xtal Osc is used

RESET
R

C
RC circuit for
Manual automatic Reset on power up 50 ms
Reset RC time constant large enough Min Effective
push button Digital
for 50 ms min Reset pulse #RES Input
Switch at worst trigger conditions
 Clock Generator (8284A)

Provides the following functions:

• Clock and Sync:
- Generates a CLK signal for the
8086/8088
- Provides a CLK sync signal for use on
multiprocessor 8086/8088 systems
- Provides a TTL-level peripheral clock
signal
• Provides RESET synchronization
• Provides READY synchronization
for wait state generation
 Clock Generator (8284A): Signals
Clock & Synchronization Signals
• X1 and X2: Crystal Oscillator pins. Connect a
crystal of the correct frequency between these
two terminals to generate the clock signal.
• EFI: External frequency input. Signal can be
used as the clocking source to the 8284A
instead of the crystal oscillator.
• F/#C input: Selects external EFI input (1) or the Crystal
crystal oscillator (0) as the clocking source for
the 8284A
• CLK output: The clock signal provided for
connection to the CLK input on the 8086/8088.
At 1/3 rd of the crystal or EFI input frequency
with 1:3 duty cycle: fclock = fxtal/3 = fEFI/3
• OSC: Oscillator output. Same frequency as
crystal or EFI. Connect to EFIs on other 8284As
in multiprocessor systems (synchronized clocks)
fosc = fxtal= fEFI
• PCLK output: peripheral clock signal at 1/6 th of
the crystal or EFI input frequency (1/2 clock OSC
freq) with 1:2 duty cycle. Use to drive peripheral To other mPs
equipment in the system fpclk = fxtal/6 = fEFI/6 PCLK
• CSYNC input: Clock synchronization input. XTAL 3 2 to Per
or EFI
Should be used if EFI is used, otherwise must be
grounded. CLK
to mP
 Clock Generator (8284A): Signals
RESET Signals
• #RES Reset input: Active low. Usually
connected to an RC circuit to provide
automatic reset on power on.
• RESET output: Synchronized to Clk.
Connect to the 8086/8088 RESET input.

READY Signals
• #AEN1 and #AEN2 address enable inputs:
Used with RDY1 and RDY2 inputs to
generate the READY output. The READY
output is connected to the READY input on
the 8086/8088 mP to control memory wait
states.
• #ASYNC input: for READY output
synchronization. Selects 1 or 2 stages of
synchronization for the RDY1 and RDY2
inputs.
 Clock Generator (8284A): Block Diagram
• Starts 4 clock pulses max after power up
• Must be kept High for at least 50 ms
Hysteresis to avoid
RESET

Schmitt trigger
jitter due to slowly
Switch/RC circuit varying inputs

Active High,
Synchronize to mP
Crystal with – ive clock edge Inverting buffer
CLOCK & Sync

Select clocking source Use as EFI in

Multiprocessor
systems
Select Crystal Osc
or EFI 3 2
Peripheral
External Frequency I/P Clock. f = 1/6th
of crystal or EFI
Frequency,
Synchronize clock if EFI is used with multiprocessor systems 1:2 duty cycle
READY

To processor
CLK input.
f = 1/3rd of
crystal or EFI
Frequency,
1:3 duty cycle

0 = 2 stages, 1 = 1 stage of synchronization

Typical Application of the 8284A for clock and Reset signal generation

frequency, f f/3

2.5 MHz
PCLK
Grounded when f/6
Xtal Osc is used

RESET
R

C
RC circuit for
Manual automatic Reset on power up 50 ms
Reset RC time constant large enough Min Effective
push button Digital
for 50 ms min Reset pulse #RES Input
Switch at worst trigger conditions
Bus Demultiplexing and Buffering
• Demultiplexing:
The address/data and address/status buses
are multiplexed to reduce the device pin
count. These buses must be demultiplexed
(separated) to obtain the signals required
for interfacing other circuits to the mP
– Use the ALE output from the microprocessor to
latch the address information that appear briefly
on the multiplexed bus
– This makes the latched address information
available for long enough time for correct
interfacing, e.g. to memory
• Buffering:
Fan out is limited, so output signals should
buffered in large systems
 Demultiplexing the 8088 Processor

Using the ALE signal to Demultiplex:

-The Address lines A0-7
from the AD0-7 muxed bus
-The A16-19 from the A16/S3-A19/S6
muxed bus
20-bit

Not
Muxed
Dat
a
Latch (Transparent)
Delay
Demuxed
A0-A7 Octal D-type
Transparent Latch

(not edge triggered)

Memory write cycle for the 8088
(non-muxed line are not shown)
ata and address lines must remain
alid and stable for the duration of the cycle

Use as data bus, with #DEN active

Demultiplexing the
8086 Processor

20-bit

16-bit

#DEN active
 Buffering

Since the microprocessor provides minimum drive

current, buffering is often needed if more than 10 TTL
loads are connected to any bus signal: Consider 3 types
of signals
• For muxed signals: Latches used for demuxing, e.g. ‘373,
can also provide the buffering for the demuxedSo,
lines:
Fan out = ?
Which case
– 0-level output can sink up to 32 mA (20 x 1.6 mA loads)
sets the limit?
– 1-Level output can source up to 5.2 mA (1 load = 40 mA)
• For non-muxed unidirectional (always output) address
and control signals (e.g. A8-15 on the 8088), buffering is
often accomplished with the 74ALS244.
• For bidirectional data signals (pin used for both in and
out), buffering is often accomplished with the 74ALS245
bidirectional bus buffer
Caution: Buffering introduces a small delay in the buffered
signals. This is acceptable unless memory or I/O devices
operate close to the maximum bus speed
Fully Muxed Buffered
Non-Muxed
and buffered 8088 Control Lines
(unidirectional-
Always O/Ps)

Buffered
Non-Muxed
Address Lines
(unidirectional-
Always O/Ps)

HiZ O/Ps for G = 1

Buffered
Bidirectional
Data Lines

Enable external buffers Direction

1:-->, 0: 
Fully Muxed and buffered 8086
 Use of 8086 in the Minimum Mode

Basic control signals are directly available

Address
Demultiplexing

Bidirectional
Data Buffering
Prevents
Transceiver from
driving the bus
when interrupt
controller
Is using it
RAM ROM I/O
Interrupt
Handling Interrupt
Requests
8086 Maximum Mode
8288 Bus Controller: Necessary in this mode.
Generates essential control signals not provided by mP

Control signals are more specific, e.g. separate lines for

M and I/O operations

8086 Chipset
 8288 Bus Controller

bus
20-Pin Chip

Familiar 8088/8086
Outputs
More specific Outputs,
Selects Replace #RD, #WR,
Mode: M/#IO
1. I/O Bus
2. System Bus
 8288 Bus Controller: Pin Functions
• S0, S1, S2 inputs: Status bus bits • #IORC output: Input/Output
from processor. Decoded by the read control signal.
8288 to produce the usual timing
signals
• #IOWC output: Input/Output
• CLK input: From the 8284A clock write control signal.
generator • #AIOWC output: Advanced
• ALE output: Address latch enable Input/Output control signal.
output for demuxing address/data • #MRDC output: Memory read
• DEN output: Data bus enable control signal.
output to enable data bus buffer. • #MWTC output: Memory write
Note opposite polarity to #DEN control signal.
output in minimum mode. • #AMWT output: Advanced
• DT/#R output: Data Memory write control signal.
transmit/Receive output to control
direction of the bi directional data
• MCE/#PDEN output: Master
bus. cascade/Peripheral data output.
• #INTA output: Acknowledge a Selects cascade operation if
hardware interrupt applied to the IOB=0 or enables I/O bus
INTR input of the processor. transceivers if IOB=5V
• IOB input: I/O bus mode input.
Selects operation in either I/O bus
mode or system bus mode.
• #AEN input: Address Enable input.
Used by the 8288 to enable Effective only in the system bus mode
memory control signals. Supplied
by a bus arbiter in a multiprocessor
system
• CEN input: Control Enable input.
Enables the generation of
command outputs from the 8288.
 Bus Cycle
• Microprocessors use the memory and I/O in periods called
bus cycle.
• A bus cycle defines the basic operation that a
microprocessor performs to communicate with external
devices.
• Examples of bus cycles are memory read, memory write,
input/ output read and input/ output write.
• A bus cycle corresponds to a sequence of events that starts
with an address being output on the system bus followed
by a read or write data transfer
• During these operations, a series of control signals are also
produced by the MPU to control the direction and timing of
the bus.
• Each bus cycle consists of at least four clock periods, T1,
T2, T3, and T4.
• These clock periods are also called the T- States.
• If the clock is operated at 5MHz(0.2ųs) then one bus cycle
is completed in 800ns.
• This means that the MP reads or writes data between itself
and memory or I/O at a max rate of 1.25 million times a
• T1 - start of bus cycle. Actions include setting control signals (or
S0- S2 status lines) to give the required values for ALE, DT/ R, IO/
M putting a valid address onto the address bus.

• T2 - the RD or WR control signals are issued, DEN is asserted in

the case of a write, data is put onto the data bus. The DEN turns on
the data bus buffers to connect the CPU to the external data bus, so
memory or I/O can receive the data to be written. The READY input
to the CPU is sampled at the end of T2 and if READY is low, a wait
state TW (one or more) is inserted before T3 begins.

• T3- this clock period is provided to allow memory to access the

data. If the bus cycle is a read cycle, the data bus is sampled at the
end of T3.

• T4- all bus signals are deactivated in preparation for the next clock
cycle. The 8088 also finishes samples the data bus connections for
data (in a read cycle) in this period. For the write cycle, the trailing
edge of the WR signal transfers data to the memory or I/ O, which
activates and write when WR returns to logic 1 level.
Minimum mode 8088 bus timing for a read operation
8088 Minimum-mode Memory Read Bus Cycle

43
8086 Minimum-mode Memory Read Bus Cycle

44
Simplified Write Cycle
8086/8088 Memory Write Bus Cycle

46
8086 Max-Mode Read and Write Bus Cycle

47