Microprocessor Systems

and
Interfacing

• Interfacing Memory with 8086/8088

Microprocessors

Slides courtesy:
1. Book ‘The Intel Microprocessors, Architecture,
Programming and Interfacing” , 7ed, by Barry B. Brey
2. http://www.pcpolytechnic.com/computer/ppt/micro/Chap
%203_1.pptx
8086 in the Minimum Mode

Basic control signals are directly available

Address
Demultiplexing

Bidirectional
Data Buffering
Prevents
Transceiver
From driving
the bus when
interrupt
controller
Is using it RAM ROM I/O
Interrupt
Handling Interrupt
Requests
8086 in the Maximum Mode
8288 Bus Controller: Necessary in this mode.
Generates essential control signals not provided by MP

Control signals are more specific, e.g. separate

lines for M and I/O operations
 Introduction

• Simple or complex, every microprocessor-based

system has a memory system.
• Almost all systems contain two main types of
memory: read-only memory (ROM) and
random access memory (RAM) or read/write
memory.
• Read-only memory (ROM)
– ROM, PROM, EPROM and EEPROM
• Random access memory (RAM)
– Static random access memory (SRAM)
– Dynamic random access memory (DRAM) 4
Hardware Organization of the Memory
Address Space
• 1Mx8 memory bank of the 8088

5
Hardware Organization of the Memory
Address Space
High and low
memory
banks of the
8086

6
Hardware Organization of the Memory
Address Space

Byte transfer
by the 8088

7
Hardware Organization of the Memory
Address Space
Word transfer by
the
8088

8
Hardware Organization of the Memory
Address Space
Even address
byte transfer
by the 8086

9
Hardware Organization of the Memory
Address Space
Odd address
byte transfer by
the
8086

10
Hardware Organization of the Memory
Address Space

Even address word

transfer
by
the 8086

11
Hardware Organization of the Memory
Address Space
Odd-address word transfer by the 8086

12
Decoding Memory Address – Decoders

Address decoder 74LS139

Decoding Memory Address – Decoders

Address decoder 74LS138

A Typical Memory Device

– address inputs
– data outputs or
input/outputs
– some type of
selection input
– at least one
control input to
select a read or
write operation
15
A Typical Memory Device
• The number of address pins
needed is directly related to
the number of addressable
locations in the memory chip.

• IK (1024) requires 10bits

2K (2048) requires 11bits
4K (4096) requires 12bits
512K requires 19bits
IM requires 20bits
2M requires 21bits

• Increasing the address by 1bit

doubles the number of 16
addressable locations
The Pin-Out of the 2716, 2K × 8
EPROM

17
Memory Organization
• An 8-bit-wide memory device is often
called a byte-wide memory.
– most devices are currently 8 bits wide,
– some are 16 bits, 4 bits, or just 1 bit wide
• Catalog listings of memory devices often
refer to memory locations times bits per
location.
– a memory device with 1K memory locations
and 8 bits in each location is often listed as
a 1K  8 by the manufacturer
• Memory devices are often classified
according to total bit capacity. 22
Interfacing 2k Bytes ROM
Using simple NAND decoder

A0 -- A10

To select any location in

the memory,
• A0-A10 should have a
binary address
• A11-A19 must be 0

A19 --- A11 A10 --- A0 Range of Addresses

0 --- 0 0 --- 0 Start Address (00000H)
0 --- 0 1 --- 1 Final Address (007FFH)
32
Interfacing 4k Bytes ROM
Using simple NAND decoder

A0 -- A10

If the chip has

OE pin, the RD is
connected to it.

33
8088 Interfacing 64KB ROM

34
8088 Interfacing 512KB RAM

35
8086 Interfacing 1MB RAM

36
8086 Interfacing 1MB RAM

37
80386 Interfacing 1M Bytes
RAM

38
80386 Interfacing 1M Bytes
RAM

39