NEHRU INSTITUTE OF ENGINEERING AND TECHNOLOGY

“Nehru Gardens” T. M. PALAYAM, COIMBATORE-105

(Approved by AICTE and Affiliated to Anna University, Chennai)
(Accredited by NAAC, Recognized by UGC with 2(f) and 12(B)) NBA
Accredited UG Courses: AERO, CSE, MECH DEPARTMENT OF
COMPUTER SCIENCE AND ENGINEERING

EC8691 – MICROPROCESSORS AND

MICRO CONTROLLERS
Prepared by
G.Jeevanantham,
AP/CSE,
NIET.
 UNIT I THE 8086
MICROPROCESSOR

Introduction to 8086 – Microprocessor

architecture – Addressing modes - Instruction
set and assembler directives –
Assembly language programming –
Modular Programming - Linking and
Relocation - Stacks - Procedures – Macros –
Interrupts and interrupt service routines – Byte
and String Manipulation.
 Microprocessor Fifth Generation Pentium

Fourth Generation
During 1980s
Low power version of HMOS technology
(HCMOS)
Third Generation 32 bit processors
During 1978 Physical memory space 224 bytes = 16 Mb
HMOS technology ⇒ Faster speed, Virtual memory space 240 bytes = 1 Tb
Higher Floating point hardware
packing density Supports increased number of addressing
16 bit processors ⇒ 40/ 48/ 64 modes
pins
Easier to program Intel 80386
Dynamically relatable programs
Processor has multiply/ divide arithmetic
hardware
Second Generation
More powerful interrupt
During 1973
handling
Intel 8086 (16 bit capabilities
processor) NMOS technology ⇒ Faster speed, Higher
density, Compatible with TTL
Flexible I/O port
4 / 8/ 16 bit processors ⇒ 40 pins
addressing
First Generation Ability to address large memory spaces
and I/O ports
Between 1971 – 1973
Greater number of levels of subroutine
PMOS technology, non compatible with
nesting
TTL
Better interrupt handling capabilities
4 bit processors ⇒ 16
pins
Intel 8085 (8 bit processor)
8 and 16 bit processors ⇒ 40 pins
• What is Microcomputer?

• What is Microprocessor?
 Functional blocks
Various conditions of the
Computational Unit;
results are stored as
performs arithmetic and Internal storage of data
status bits called flags in
logic operations
flag register

Register array or Data Bus

internal
ALU memory
Generates the
Instruction address of the
Flag decoding unit instructions to be
Register fetched from the
memory and send
through address
bus to the
Timing and memory
control PC/ IP
unit

Control Bus Address Bus

Generates control signals for Decodes instructions; sends

internal and external operations information to the timing and
of the microprocessor control unit
8086 Microprocessor

Overview
First 16- bit processor released
by INTEL in the year 1978

Originally HMOS, now manufactured

using HMOS III technique

Approximately 29, 000 transistors, 40

pin DIP, 5V supply

Does not have internal clock; external

asymmetric clock source with 33% duty
cycle

20-bit address to access memory ⇒ can

address up to 220 = 1 megabytes of
memory space.
Pins and signals
8086 Microprocessor
Common signals

Pins and Signals AD0-AD15 (Bidirectional)

Address/Data bus

Low order address bus; these are

multiplexed with data.

When AD lines are used to transmit

memory address the symbol A is used
instead of AD, for example A0-A15.

When data are transmitted over AD lines

the symbol D is used in place of AD, for
example D0-D7, D8-D15 or D0-D15.

A16/S3, A17/S4, A18/S5, A19/S6

High order address bus. These

are multiplexed with status signals
8086 Microprocessor

Pins and
Common signals

BHE (Active Low)/S7 (Output)

Signals Bus High Enable/Status

It is used to enable data onto the most

significant half of data bus, D8-D15. 8-bit
device connected to upper half of the
data bus use BHE (Active Low) signal. It
is multiplexed with status signal S7.

MN/ MX

MINIMUM / MAXIMUM

This pin signal indicates what mode

the processor is to operate in.

RD (Read) (Active Low)

The signal is used for read operation.

It is an output signal.
It is active when
low.
8086 Microprocessor

Pins and
Common signals

Signals

READY

This is the acknowledgement from the

slow device or memory that they
have completed the data transfer.

The signal made available by the devices

is synchronized by the 8284A clock
generator to provide ready input to the
8086.

The signal is active high. 10

8086 Microprocessor

Pins and
Common signals

RESET (Input)
Signals Causes the processor to
immediately terminate its present
activity.

The signal must be active HIGH for at

least four clock cycles.
CLK

The clock input provides the basic timing

for processor operation and bus control
activity. Its an asymmetric square wave
with 33% duty cycle.

INTR Interrupt Request

This is a triggered input. This is sampled

during the last clock cycles of each
instruction to determine the availability
of the request. If any interrupt request is
pending, the processor enters the
interrupt acknowledge cycle.

This signal is active high and internally

synchronized. 11
8086 Microprocessor
Min/ Max Pins
Pins and
Signals The 8086 microprocessor can work in two
modes of operations : Minimum mode and
Maximum mode.

In the minimum mode of operation

the microprocessor do not associate with
co-processors
any and can not be used for
multiprocessor systems.

In the maximum mode the 8086 can work

in multi-processor or co-processor
configuration.

Minimum or maximum mode operations

are decided by the pin MN/ MX(Active low).

When this pin is high 8086 operates in

minimum mode otherwise it operates in
Maximum mode.
8086 Microprocessor
Minimum mode signals

Pins and
Signals

ALE (Address Latch Enable) Used to demultiplex the

address and data lines using external latches
8086 Microprocessor
Minimum mode signals

Pins and
Signals

HOLD Input signal to the processor form the bus masters

as a request to grant the control of the bus.

Usually used by the DMA controller to get the

control of the bus.

HLDA (Hold Acknowledge) Acknowledge signal by the

processor to the bus master requesting the control
of the bus through HOLD.

The acknowledge is asserted high, when the

processor accepts HOLD.
8086 Microprocessor
Maximum mode signals
Pins and
Signals
8086 Microprocessor
Maximum mode signals

Pins and
Signals
8086 Microprocessor
Maximum mode signals
 Features of 8086
Microprocessor
• 8086 is a 16 bit μp
• 8086 has 16 bit Data Bus(D0-D15).
• 8086 has 20 bit Address Bus(A0-A19).
• 8086 has multiplexed Address and Data bus which
reduced the number of pins (AD0-AD15) & (A16-
A19).
• The memory addressing capacity is 1 MB.
• 8086 requires only one power supply +5V and one
clock phase whose frequency can be up to 5MHz.
• 8086 has 40 pin dual in line package.
• 8086 has 14, 16 bit registers.
8086 Microprocessor

Architecture

Execution Unit (EU) Bus Interface Unit (BIU)

EU executes instructions that have BIU fetches instructions, reads data

already been fetched by the BIU. from memory and I/O ports, writes
data to memory and I/ O ports.
BIU and EU functions separately.
8086 Microprocessor
Bus Interface Unit (BIU)

Architecture 20 bit
Dedicated Adder toaddress
generate

Four 16-bit segment

registers

Code Segment (CS)

Data Segment (DS)
Stack Segment
(SS) Extra
Segment (ES)

Segment Registers >>

 8086 Microprocessor
Bus Interface Unit (BIU)

Architecture
Segment

Registers

• 8086’s 1- • The 8086 can directly address • Programs obtain access

memory is divided into
megabyte four segments (256 K bytes code
to and data in the
segments of up to 64K within the 1 M byte of memory) segments by changing the
bytes each. at a particular time. segment register content to
point to the
desired segments.
8086 Microprocessor
Bus Interface Unit (BIU)

Architecture
Segment Code Segment Register
•16-bit
Registers
•CS contains the base or start of the current code segment; IP contains
the distance or offset from this address to the next instruction byte to be
fetched.

•BIU computes the 20-bit physical address by logically shifting the

contents of CS 4-bits to the left and then adding the 16-bit contents of IP.

•That is, all instructions of a program are relative to the contents of the CS
register multiplied by 16 and then offset is added provided by the IP.
8086 Microprocessor
Bus Interface Unit (BIU)

Architecture
Segment Data Segment Register

Registers
•16-bit

•Points to the current data segment; operands for most instructions are
fetched from this segment.

•The 16-bit contents of the Source Index (SI) or Destination Index (DI) or a
16-bit displacement are used as offset for computing the 20-bit physical
address.
8086 Microprocessor
Bus Interface Unit (BIU)

Architecture
Segment Stack Segment Register
•16-bit
Registers
•Points to the current stack.

•The 20-bit physical stack address is calculated from the Stack Segment
(SS) and the Stack Pointer (SP) for stack instructions such as PUSH and
POP.

•In based addressing mode, the 20-bit physical stack address is

calculated from the Stack segment (SS) and the Base Pointer (BP).
8086 Microprocessor
Bus Interface Unit (BIU)

Architecture
Segment Extra Segment Register

Registers
•16-bit

•Points to the extra segment in which data (in excess of 64K pointed to by
the DS) is stored.

•String instructions use the ES and DI to determine the 20-bit physical

address for the destination.
8086 Microprocessor
Bus Interface Unit (BIU)

Architecture
Segment Instruction Pointer
•16-bit
Registers
• Always points to the next instruction to be executed within
the currently executing code segment.

• So, this register contains the 16-bit offset address pointing to

the next instruction code within the 64Kb of the code
segment area.

• Its content is automatically incremented as the execution of

the next instruction takes place.
8086 Microprocessor
Bus Interface Unit (BIU)

Architecture
Instruction queue

• A group of First-In-First-Out
(FIFO) in which up to 6 bytes
of instruction code are pre
fetched from the memory
ahead of time.

• This is done in order to speed

up the execution by
overlapping instruction fetch
with execution.

• This mechanism is known as

pipelining.
8086 Microprocessor
Execution Unit (EU)

EU decodes and Architecture

executes instructions.

A decoder in the EU
control system
translates instructions.

16-bit ALU for

performing arithmetic
and logic operation

Four general purpose

registers(AX, BX, CX, DX);

Pointer registers (Stack

Pointer, Base Pointer);

and
Some of the 16 bit registers can be
Index registers (Source used as two 8 bit registers as :
Index, Destination Index)
each of 16-bits AX can be used as AH and AL
BX can be used as BH and BL
CX can be used as CH and CL
DX can be used as DH and
8086 Microprocessor
Execution Unit (EU)

Architecture
EU Accumulator Register (AX)
Registers
• Consistsof two 8-bit registers AL and AH, which can
be combined together and used as a 16-bit register AX.

• AL in this case contains the low order byte of the word, and
AH contains the high-order byte.

• The I/O instructions use the AX or AL for inputting

/ outputting 16 or 8 bit data to or from an I/O port.

• Multiplication and Division instructions also use the AX or AL.

8086 Microprocessor
Execution Unit (EU)

Architecture
EU Base Register (BX)
Registers
• Consistsof two 8-bit registers BL and BH, which can
be combined together and used as a 16-bit register BX.

• BL in this case contains the low-order byte of the word, and

BH contains the high-order byte.

• This is the only general purpose register whose contents can

be used for addressing the 8086 memory.

• All memory references utilizing this register content

for addressing use DS as the default segment register.
8086 Microprocessor
Execution Unit (EU)

Architecture
EU Counter Register (CX)
Registers
• Consistsof two 8-bit registers CL and CH, which can
be combined together and used as a 16-bit register CX.

• When combined, CL register contains the low order byte of

the word, and CH contains the high-order byte.

• Instructions such as SHIFT, ROTATE and LOOP use

the contents of CX as a counter.

Example:

The instruction LOOP START automatically decrements

CX by 1 without affecting flags and will check if [CX] =
0.

If it is zero, 8086 executes the next instruction;

otherwise the 8086 branches to the label START.
8086 Microprocessor
Execution Unit (EU)

Architecture
EU
Registers
8086 Microprocessor
Execution Unit (EU)

Architecture
EU Stack Pointer (SP) and Base Pointer (BP)
Registers
• SP and BP are used to access data in the stack segment.

• SP is used as an offset from the current SS during execution

of instructions that involve the stack segment in the external
memory.

• SP contents are automatically updated (incremented/

decremented) due to execution of a POP or PUSH instruction.

• BP contains an offset address in the current SS, which is used

by instructions utilizing the based addressing mode.
8086 Microprocessor
Execution Unit (EU)

Architecture
EU Source Index (SI) and Destination Index (DI)
Registers
• Used in indexed addressing.

• Instructions that process data strings use the SI and DI

registers together with DS and ES respectively in order to
distinguish between the source and destination addresses.

34
8086 Microprocessor
Execution Unit (EU)

Architecture
EU Source Index (SI) and Destination Index (DI)
Registers
• Used in indexed addressing.

• Instructions that process data strings use the SI and DI

registers together with DS and ES respectively in order to
distinguish between the source and destination addresses.
8086 Microprocessor
Execution Unit (EU)

Flag Register
Architecture Auxiliary Carry Flag

This is set, if there is a carry from the

Carry Flag

lowest nibble, i.e, bit three during This flag is set, when there is
addition, or borrow for the lowest a carry out of MSB in case of
nibble, i.e, bit three, during addition or a borrow in case
subtraction. of subtraction.

Sign Flag Zero Flag Parity Flag

This flag is set, when the This flag is set, if the result of This flag is set to 1, if the lower
result of any computation the computation or comparison byte of the result contains even
is negative performed by an instruction is number of 1’s ; for odd number
zero of 1’s set to zero.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OF DF IF TF SF ZF AF PF CF

Tarp Flag
Over flow Flag
If this flag is set, the processor
This flag is set, if an overflow occurs, i.e, if the result of a signed
enters the single step execution
operation is large enough to accommodate in a destination
mode by generating internal
register. The result is of more than 7-bits in size in case of 8-bit
signed operation and more than 15-bits in size in case of 16-bit interrupts after the execution of
sign operations, then the overflow will be set. each instruction
Direction Flag Interrupt Flag
This is used by string manipulation instructions. If this flag bit
is ‘0’, the string is processed beginning from the lowest Causes the 8086 to recognize
address to the highest address, i.e., auto incrementing mode. external mask interrupts; clearing IF
Otherwise, the string is processed from the highest address disables these interrupts.
towards the lowest address, i.e., auto incrementing mode. 36
8086 Microprocessor
Architecture

8086 registers
categorized 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

into 4 groups OF DF IF TF SF ZF AF PF CF

Sl.No. Type Register width Name of register

1 General purpose register 16 bit AX, BX, CX, DX

8 bit AL, AH, BL, BH, CL, CH, DL, DH

2 Pointer register 16 bit SP, BP

3 Index register 16 bit SI, DI

4 Instruction Pointer 16 bit IP

5 Segment register 16 bit CS, DS, SS, ES

6 Flag (PSW) 16 bit Flag register

37
8086 Microprocessor
Architecture Registers and Special Functions

Register Name of the Register Special Function

AX 16-bit Accumulator Stores the 16-bit results of arithmetic and logic operations

AL 8-bit Accumulator Stores the 8-bit results of arithmetic and logic operations

BX Base register Used to hold base value in base addressing mode to access
memory data

CX Count Register Used to hold the count value in SHIFT, ROTATE and LOOP
instructions

DX Data Register Used to hold data for multiplication and division operations

SP Stack Pointer Used to hold the offset address of top stack memory

BP Base Pointer Used to hold the base value in base addressing using SS
register to access data from stack memory

SI Source Index Used to hold index value of source operand (data) for string
instructions

DI Data Index Used to hold the index value of destination operand (data)
for string operations 38
 Addressing Modes
1) Immediate addressing mode
2) Register addressing mode
3) Direct memory addressing mode
4) Register based indirect addressing mode
5) Register relative addressing mode
6) Base indexed addressing mode
7) Relative based indexed addressing mode
 1) Immediate addressing mode
• In this mode, the operand is specified in
the
instruction itself.
• Example:
• MVI CL, 12H
• This instruction moves 12 immediately into
CL
register. CL ← 12H
 2) Register addressing mode
• In this mode, operands are specified using
registers.
• Example:
• MOV AX, BX
• This instruction copies the contents of BX
register into AX register. AX ← BX
3) Direct memory addressing mode
• In this mode, address of the operand is directly specified in
the instruction. Here only the offset address is specified,
the segment being indicated
• Example:
• MOV CL, [4321H]
• This instruction moves data from location 4321H in the
data segment into CL.
• The physical address is calculated as
• DS * 10H + 4321
• Assume DS = 5000H
• ∴PA = 50000 + 4321 = 54321H
• ∴CL ← [54321H] by the instruction.
4) Register based indirect addressing
mode
• In this mode, the effective address of the memory
may be taken directly from one of the base
register or index register specified by
instruction.
• Example:
• MOV CX, [BX]
• This instruction moves a word from the address
pointed by BX and BX + 1 in data segment into
CL and CH respectively.
• Physical address can be calculated as DS *
10H + BX.
 5) Register relative addressing mode

• In this mode, the operand address is calculated

using one of the base registers and an 8 bit or a
16 bit displacement.
• Example:
• MOV CL, [BX + 04H]
• This instruction moves a byte from the address
pointed by BX + 4 in data segment to CL.
• CL ← DS: [BX + 04H]
• Physical address can be calculated as DS * 10H +
BX + 4H.
6) Base indexed addressing mode
• Here, operand address is calculated as base
register plus an index register.
• Example:
• MOV CL, [BX + SI]
• This instruction moves a byte from the
address
pointed by BX + SI in data segment to
CL.
• CL ← DS: [BX + SI]
• Physical address can be calculated as DS *
10H +
7) Relative based indexed addressing
mode
• In this mode, the address of the operand is
calculated as the sum of base register, index
register and 8 bit or 16 bit displacement.
• Example:
• MOV CL, [BX + DI + 20]
• This instruction moves a byte from the address
pointed by BX + DI + 20H in data segment to
CL.
• CL ← DS: [BX + DI + 20H]
• Physical address can be calculated as DS * 10H +
BX + DI + 20H.
 INSTRUCTION SET OF 8086
MICRPOROCESSOR
• The INSTRUCTION set are categorized into
the following types:
• Data transfer INSTRUCTIONS
• Arithmetic INSTRUCTIONS
• Logical INSTRUCTIONS
• Jump INSTRUCTIONS
• Shift and Rotate INSTRUCTIONS
DATA TRANSFER INSTRUCTIONS
• The data transfer instructions are used to
move data between internal registers or
between internal register and the memory.
i)MOV instruction
– MOV instruction is used to transfer data from
source operand to a destination operand
–Examples:
MOV CX,DX
MOV AX,3025H
DATA TRANSFER INSTRUCTIONS
ii) XCHG instruction
Example:
XCHG BX,AX
III)LEA instruction
Example:
LEA BX,
[BETA]
IV)LDS instruction
Example:
LDS SI,[20]
V) LES instruction
Example:
LES DX,[BX]
ARITHMETIC INSTRUCTIONS
• Arithmetic instructions are used to do
arithmetic operation such as
• Addition
• Subtraction
• Multiplication
• Division
 ARITHMETIC INSTRUCTIONS
• Addition
Instruction Examples
ADD AL,BL

ADD CX,DI

ADC AX,
[BX] INC SP
ARITHMETIC INSTRUCTIONS
• SUBTRACT instruction
Examples
SUB AX, SP
SUB DH,6F
SBB AX,BX
DEC BH
ARITHMETIC INSTRUCTIONS
• MULTIPLICATION instructions
MUL CL
MUL CX
IMUL
CL
• DIVISION instructions
DIV CL
IDIV SI
 LOGICAL INSTRUCTION
• AND instruction
Example
AND AL,BL
• OR instruction
Example
OR SI,DX
• XOR instruction
XOR CH,OE
• NOT instruction
NOT CH
 Shift and Rotate Instruction
• SHL instruction
SHL AX,1
• SHR instruction
SHR AX,CL
• ROL instruction
ROL AX,1
• ROR instruction
ROR AX,CL
 Jump Instruction
• Jump instruction are used to change the
execution path of instruction in the
program.
i) Unconditional Jump
Short Jump
Near Jump
Far Jump
ii)Conditional
Jump
 String and String Handling
Instructions
• Move Operation: Move is a process of
moving a string of data from one Memory
Location to another.
Eg. MOVSB: This instruction moves a byte
of data from one memory location to
another.
MOVSW: This instruction moves a
word of data from Source to Destination
Operand.
 String and String Handling
Instructions
• Compare Operation: Compare is a process of
comparing two elements in the same or
different string.
Eg. COMPSB: This instruction compares a
byte of data from one memory location to
another.
COMPSW: This instruction compares a
word of data from one memory location to
another.
 String and String Handling
Instructions
• SCAN: SCAN is a process of comparing
elements of Destination string with
Accumulator.
Eg. SCASB: This instruction scans a byte of
data from Destination with Accumulator
Register.
SCASW: This instruction scans a
word of data from Destination with
Accumulator Register.
 String and String Handling
Instructions
• Load Operation: Load is a process of
loading string elements from Memory
Location with Accumulator.
Eg. LODSB: This instruction loads a byte of
data from Memory Location with
Accumulator.
LODSW: This instruction lods a word
of data from Memory Location with
Accumulator.
 String and String Handling
Instructions
• Store Operations: Store is a process of moving
string of elements from Accumulator to
Memory Location.
Eg.STOSB: This instruction stores a byte of
data from Accumulator to Memory Location.
STOSW: This instruction stores a word of
data from Accumulator to Memory Location.
 String and String Handling
Instructions
• AUTO INDEXING: Auto Indexing is a
process of Incrementing or Decrementing the
content of Source Index or Destination Index.
Eg.CLD: When this instruction is executed
Direction Flag is cleared to zero. Now Auto
Incrementing Source Index or Destination
Index takes place.
 Assembly Language
Programming
• 16 bit Addition
Assembly Language
Programming
 Interrupt and Interrupt Service
Routing
• While CPU is executing a program, an
interrupt breaks the normal sequence of
executing the instruction, it diverts its
execution to some other program called
Interrupt Service Routine.
• After executing, the control is transferred back
again to the main program which was being
executed at the time of interrupt.
 Interrupt and Interrupt Service
Routing
• 8086 has two types of interrupt pins NMI and INTR.
• NMI(Non Maskable Interrupt): It is a single non-
maskable interrupt pin (NMI) having higher priority
than the maskable interrupt request pin.
• The INTR is a maskable interrupt because the
microprocessor will be interrupted only if interrupts
are enabled using set interrupt flag instruction. It
should not be enabled using clear interrupt Flag
instruction.
 Interrupt and Interrupt Service
Routing
• Types of Interrupt:
1.External Interrupt: External device or
a signal interrupt the process from
outside.
Eg. Keyboard
2.Internal Interrupt. Internal Interrupt is
Interrupt:
generated internally by the processor
circuit.
Eg. Overflow Interrupt.
 Assembler Directives
• Assembler is a program which translates an
assembly language program into machine
language program.
1.ASSUME: The ASSUME directive is used to
tell the assembler that the name of the logical
segment should be used for a specified segment.
The 8086 works directly with only 4 physical
segments: a Code segment, a Data segment, a
Stack segment, and an Extra segment.
 Assembler Directives
Eg.
ASSUME CS:CODE: This tells the assembler
that the logical segment named CODE contains
the instruction statements for the program and
should be treated as a code segment.

ASSUME DS:DATA: This tells the

assembler that forany instruction which
refers to a data in the data segment, data will
found in the logical segment DATA.
 Assembler Directives
2. END Directives:
END – It signifies the end of the program
module
ENDP - Indicates the end of a procedure
ENDS - Indicates the end of a logical
segment
 Assembler Directives
3. Equate (EQU) Directive: EQU - This EQU
directive is used to give a name to some value
or to a symbol. Each time the assembler finds
the name in the program, it will replace the
name with the value or symbol you given to
that name.
Eg. FACTOR EQU 03H: You has to write this
statement at the starting of your program.
 Assembler Directives
4.PROC - The PROC directive is used to
identify the start of a procedure. The term near
or far is used to specify the type of the
procedure.
Eg. SMART PROC FAR: This identifies
that the start of a procedure named as SMART
and instructs the assembler that the procedure
is far .
SMART ENDP: This PROC is used with
ENDP to indicate the break of the
 Procedure
• Procedure is a group of instruction stored at a separate program in
memory and it is called from main program whenever it required.
• To use the Procedure CALL & RET instruction is used.
• It occupies Less Memory.
• Stack is used in Procedure.
• To mark end of the procedure type ENDP.
• Overtime is required to call the procedure and return to the calling
program.
Syntax:
proc_name:
procedure body
...
ret
 Macro
• A Single instruction that expands automatically in to a set
instructions of
to perform a particular task.
• To use Macro just type Macro.
• It requires more memory.
• Stack is not used in Macro.
• To end of Macro type ENDM.
• No overtime is required during execution.
• Syntax:
Macro definition
Name MACO[Parameters…]
<Statements>
ENDM
 Linking and Relocation
• Linking links the library and header file.
• Most critical function of the linker is to ensure
that labels in all modules are properly
interrupted.
• In constructing a program some program
modules may be put in the same source
module and assembled together.
• Other may be in different source module
and assembled separately.
 Linking and Relocation
• If they are assembled separately, then the main
module which has the first instruction to be
executed, must be terminated by END
statement with the entry specified and each of
the other module must be terminated by an END
statement with no operand.
• Find the object modules to be linked
• Construct the load module by assiging the
positions of all of the segments in all of the object
modules being linked.
 Linking and Relocation
• Fill in all offsets that could not be
determined by the assembler.
• Fill in all segment address.
• Load the program for execution.
Linking and Relocation
 Stack
• Stack is a dynamic data structure in which
data can be placed and retrieved in LIFO(Last
In First Out).
• Data elements are added to the stack by
pushing them on to the stack are retrieved by
popping them.
Stack
 MODULAR PROGRAMMING

•Modular Programming
•Need of Modular Programming
•Why Modular Programming?
•Modularity
•Advantages of Modular Programming
•Disadvantages of Modular Programming
 MODULAR PROGRAMMING

• Modular programming a software

is design technique emphasizes
that
separating the functionality of a program
into independent, interchangeable
modules, such that each contains
everything necessary to execute.
Need for Modular Programming
• When a program becomes very large and complex,
it becomes very difficult task for the programmers
to design, test and debug such a program.
• Therefore a long program can be divided into a

smaller program called modules as the

modules can be designed, tested and
debugged separately, the task of programmer
becomes easy and convenient.
• It makes your program easy to understand.
 Why Modular Programming?
• Helps manage complexity
Smaller blocks of code
Easier to read
•Encourages re-use of code
Within a particular program or across
different programs
•Allows independent development of code
 Modularity
• How do you solve a big/complex
problem?
• Divide it into small tasks and solve each
task. Then combine these solutions.
•In 8086 microprocessor we use functions also referred to
as
modules to perform specific tasks that we determined in our solution.
•This strategy is essentially based on the divide-and-conquer
approach to problem solving and has many advantages over
developing a program for the entire problem.

•We will assign a name to each module and combine the named
modules in a program structure under the control of a main program.

•Such a program structure consists of a set of modules and an order

of execution.

•When all modules are tested ‘OK’, they are linked together to form a
large functioning program.
 1.Assembling Process
• As mentioned earlier, assembler translates a source file that was created
using the editor into machine language such as binary or object
code. The assembler reads the source file of our program from the disk
where we saved it after editing. An assembler usually reads our source file
more than once.
• The assembler generates two files on the floppy or hard disk during these
two passes. The first file is called the object file. The object file
contains the binary codes for the instructions. The second file generated by
the assembler is called assembler list file. This file contains the
assembly language statements, the binary code for each
instruction, and the offset for each instruction.
• In the first pass, the assembler performs the following operations
 1.Assembling Process
• Reading the source program instructions.
• Creating a symbol table in which all
symbols used in
the program, together with their attributes, are
stored.
• Replacing all mnemonic codes by their binary
codes.
• Detecting any syntax errors in the
source program.
• Assigning relative addresses to
instructions
 2.Linking Process

• A linker is a program used to join together several object files

into one large object file. When writing large programs, it is
usually much more efficient to divide the large program into
smaller modules. Each Modular Programming can be
individually written, tested and debugged. When all the
Modular Programming work, they can be linked together to
form a large functioning program.
• The linker produces a link file which contains the binary codes
for all the combined modules.
 3.Debugging Process
• A debugger is a program which allows us to load our object
code program into system memory, execute the program, and debug it.
• How does a debugger help in debugging a program ?
• The debugger allows us to look at the contents of registers and memory
locations after our program runs.
• It allows us to change the contents of register and memory locations and
rerun the program.
• Some debugger allows us to stop execution after each instruction so we can check
or alter memory and register contents.
 Advantages of using Modular
Programming
•Modules can be written and tested separately
•Modules can be reused
•Large projects can be developed in parallel
•Reduces length of program, making it more
readable
•Promotes the concept of abstraction
Disadvantages of using Modular
Programming
• The documentation of modules must
be systematic.
• It Can lead the problems when
modules
are linked because link must thoroughly
tested.
• Since separate map
modules certain repeat the
functions,
programming often need modular
extra time and
memory.
Thank
You