3/3/2021

Ho Chi Minh City University of Technology

Department of Electrical and Electronics

1. CPU
2. Memory
3. Input / Output devices
4. Computer Software

Chapter 4 1

1. CPU
1.1. History of CPUs
 1950s:
 Ferranti Mark 1, 1951: from University of Manchester
 single 80-bit accumulator , the 40-bit "multiplicand/quotient
register"
 UNIVAC I (UNIVersal Automatic Computer I) designed
principally by J. Presper Eckert and John Mauchly, the
inventors of the ENIAC
 1,905 operations per second running on a 2.25 MHz clock.
 IBM 704 in 1957:

Ferranti Mark 1, c. 1951 Ferranti Mark 1, c. 1951 An IBM 704 computer

at NACA in 1957
Chapter 4 2

1
 3/3/2021

1. CPU
1.1. History of CPUs
 1960s:
 IBM System/360 (S/360): 34,500 instructions per
second, with memory from 8 to 64 KB
 PDP-11: developed by Digital Equipment Corporation
 32 bit processor, allow 4 MB of physical memory
 Motorola 68000:
 Initial speed grades were 4, 6, and 8 MHz.
 68k instruction set

IBM System/360 PDP-11/40 Motorola MC68000

Chapter 4 3

1. CPU
1.1. History of CPUs
 1970s:
 Intel 4004 (1971):
 a single instruction cycle was 10.8 microseconds
 Clock rate is 1 MHz

 Intel 8008 (1972)/ 8080(1974)/8086(1976): 8-bit CPU with an

external 14-bit address
 8008 clock frequency: 0.2 - 0.8MHz
 8080 clock frequency: 2 MHz
 8086 clock frequency : 5-10MHz
 32-bit VAX (1977): based on DEC's earlier PDP-11, support
virtual memory

Intel 4004 Intel 8088 Intel 8086

Chapter 4 4

2
 3/3/2021

A Brief History of Computer

Link YouTube: https://www.youtube.com/watch?v=iK0PT5q7GlE

Chapter 4 5

1. CPU
1.2. Intel x86 Processors
 Dominate laptop/desktop/server market

 Evolutionary design
 Backwards compatible up until 8086, introduced in 1978
 Added more features as time goes on

 Complex instruction set computer (CISC)

 Many different instructions with many different formats
 But, only small subset encountered with Linux programs
 Hard to match performance of Reduced Instruction Set
Computers (RISC)
 But, Intel has done just that!
 In terms of speed. Less so for low power.
Chapter 4 6

3
 3/3/2021

Intel x86 Evolution: Milestones

Name Date Transistors MHz
 8086 1978 29K 5-10
 First 16-bit Intel processor. Basis for IBM PC & DOS
 1MB address space
 386 1985 275K 16-33
 First 32 bit Intel processor , referred to as IA32
 Added “flat addressing”, capable of running Unix
 486
 32-bit register, 32-bit data
 486DX include FPU (Floating Point Unit)
 Pentium 4E 2004 125M 2800-3800
 First 64-bit Intel x86 processor, referred to as x86-64
 Core 2 2006 291M 1060-3500
 First multi-core Intel processor
 Core i3, i5, i7 2008 731M 1700-3900
 Two cores / four cores

Chapter 4 7

Intel x86 Processors, cont.

 Machine Evolution
 386 1985 0.3M
 Pentium 1993 3.1M
 Pentium/MMX 1997 4.5M
 Pentium Pro 1995 6.5M
 Pentium III 1999 8.2M
 Pentium 4 2001 42M
 Core 2 Duo 2006 291M
 Core i7 2008 731M
 Added Features
 Instructions to support multimedia operations
 Instructions to enable more efficient conditional operations
 Transition from 32 bits to 64 bits
 More cores

Chapter 4 8

4
 3/3/2021

2015 State of the Art

 Core i7 Broadwell 2015

 Desktop Model
 4 cores
 Integrated graphics
 3.3-3.8 GHz
 65W

 Server Model
 8 cores
 Integrated I/O
 2-2.6 GHz
 45W

Chapter 4 9

1. CPU
1.3. x86 Processors
 8086 processor
 40 pin dual in-line package
 16-bit wide data bus
 16-bit registers
 20-bit external address bus
provides a 1 MB physical
address space
 The maximum linear address
space is limited to 64 KB
 Max CPU clock: 5- 10 MHz

Chapter 4 10

5
 3/3/2021

1. CPU - x86 Processor

 CPU, memory, input/output devices
 Instruction set, interfacing C to assembly, macros, stack
frame and calling convention
 Interrupt, exception

Chapter 0 11

1. CPU
1.3. x86 Processors - 8086
 Instructions:
 One-address or two addresses operations
 Support Assembly and high-level programming language (C,
Pascal)
 Main registers: are called data register or general register
 16 bit data
 Can be accessed by 8-bit registers

AH AL AX (primary accumulator)
BH BL BX (base, accumulator)
CH CL CX (counter, accumulator)
DH DL DX (accumulator, other functions

Chapter 4 12

6
 3/3/2021

1. CPU
1.3. 8086 Processors - 8086
 Index registers: for addressing

SI Source Index
DI Destination Index
BP Base Pointer
SP Stack Pointer
 Program counter:

IP Instruction Pointer

 Segment registers:
CS Code Segment
DS Data Segment
ES Extra Segment
SS Stack Segment
Chapter 4 13

1. CPU
1.3. 8086 Processors
 Segment registers:
 a way to allow programs to address more than 64 KB
 the registers CS, DS, SS, and ES point to the currently used program code
segment (CS), the current data segment (DS), the current stack segment
(SS), and one extra segment determined by the programmer (ES).

CS Code Segment
DS Data Segment
ES Extra Segment
SS Stack Segment

0110 1000 1000 0111 0000 Segment, 16 bits, shifted 4 bits left
+ 0011 0100 1010 1001 Offset, 16 bits

0110 1011 1101 0001 1001 Address, 20 bits

Chapter 4 14

7
 3/3/2021

1. CPU
1.3. 8086 Processors - 8086
 Examples for x86
memory segmentation

Chapter 4 15

1. CPU
1.3. x86 Processors
 x86-32: 80386, 80486
 Register extend to 32-bit
 EAX. EBX ECX, EDX
 ESI, EDI, EBP, ESP, EIP, EFLAGS
 Two new segment registers (FS and GS) were added
 FS, GS is extra data for segment registers
 x86-64: AMD64, Core i5, Core i7,
 An R-prefix identifies the 64-bit registers (RAX, RBX,
RCX, RDX, RSI, RDI, RBP, RSP, RFLAGS, RIP)
 Add eight additional 64-bit general registers (R8-R15)

Chapter 4 16

8
 3/3/2021

Some History: IA32 Registers

Origin
(mostly obsolete)
%eax %ax %ah %al accumulate

%ecx %cx %ch %cl counter

general purpose

%edx %dx %dh %dl data

%ebx %bx %bh %bl base

source
%esi %si index

destination
%edi %di index
stack
%esp %sp
pointer
base
%ebp %bp
pointer

16-bit virtual registers

Chapter 4 (backwards compatibility) 17

x86-64 Integer Registers

%rax %eax %r8 %r8d

%rbx %ebx %r9 %r9d

%rcx %ecx %r10 %r10d

%rdx %edx %r11 %r11d

%rsi %esi %r12 %r12d

%rdi %edi %r13 %r13d

%rsp %esp %r14 %r14d

%rbp %ebp %r15 %r15d

 Can reference low-order 4 bytes (also low-order 1

& 2 bytes) Chapter 4 18

9
 3/3/2021

2. Memory

 Memory - Purpose of memory is data storage. Two major

types of memory :

 Primary memory - to hold data and instructions during

processing
 eg RAM. Relatively limited capacity and volatile

 Secondary memory - to provide permanent long term

storage
 eg hard disk. High capacity and non-volatile

Chapter 4 19

2. Memory

Main Memory (RAM)

1. Different from disk storage

2. used to temporarily store Data
3. in modern computers memory is 512 MB.

Chapter 4 20

10
 3/3/2021

2. Memory

 Primary memory consists of a set of locations defined

by sequentially numbered addresses. Each location
contains a binary number that can be interpreted as data
or an instruction.
 8086 uses 20-bit physical address
 Manage 1MB of memory
 80386 uses 32-bit physical address
 Manage 4GB of memory
 X86-64 uses 64-bit physical address
 Manage ??? of memory

Chapter 4 21

 Memory locations are called words. Words are 8 bits (one byte) in size, or
a multiple of 8. Common word sizes are 16, 32 and 64 bits.

0 1 0 0 1 0 0 0 1

1
1 1 0 1 0 0 1 1
2
0 1 0 0 0 0 0 0
3

4 1 0 1 0 0 1 1 1

5 1 1 1 0 1 0 1 0

1 1 0 0 1 0 1 0

Memory locations, using an 8 bit word

Chapter 4 22

11
 3/3/2021

2. Memory

 Memory is commonly measured in multiples of bits

and bytes.
1 bit = 1 binary digit (0 or 1).

1. 1 byte = 8 bits

2. 1KB = 1024 bytes = 210

3. 1MB = 1024 KB= 220

4. 1GB = 1024 MB = 230

5. 1TB = 1024 GB = 240

Chapter 4 23

Big Endian vs. Little Endian

• x86 processors are little-endian
• IBM z/Architecture mainframes are big-endian processors

Big Endian Little Endian

(Others) High Memory (Intel)
Addresses
Register Register

FE ED FA CE
00 0x5 00 FE ED FA CE
00 0x4 00
CE 0x3 FE
FA 0x2 ED
ED 0x1 FA
FE 0x0 CE
Low Memory Addresses
Chapter 4 24

12
 3/3/2021

2. Memory

 Secondary storage consists of non-volatile high-capacity

devices to store programs and data not currently
required by CPU.

 Hard and floppy disks, and tapes store data as

magnetized spots.

 CD’s and DVD’s store data as pits or surface marks

detectable by laser light.

Chapter 4 25

Quiz
1) Pick the correct choice for the 8086 CPU.
A 16 bit word size, 8 bit data path
B 8 bit word size, 8 bit data path
C 16 bit word size, 16 bit data path
D 4 bit word size, 8 bit data path
E 8 bit word size, 16 bit data path
2) Pick the correct choice for the 80386SX CPU.
A 16 bit word size, 16 bit data path
B 32 bit word size, 16 bit data path
C 8 bit word size, 32 bit data path
D 32 bit word size, 8 bit data path
E 32 bit word size, 32 bit data path
3) Pick the correct choice for the 80486DX CPU.
A 32 bit word size, 16 bit data path
B 64 bit word size, 32 bit data path
C 32 bit word size, 32 bit data path
D 32 bit word size, 16 bit data path
E 32 bit word size, 64 bit data path
Chapter 4 26

13
 3/3/2021

Quiz
4) What is the first CPU to include an internal math
coprocessor?
A 386DX
B 486SX
C 486DX
D Pentium
5) What are the two main components of the CPU?
A The Control Unit and ALU
B The Registers and Output/Input management
C The ALU and FPU
6) What are the two main desktop CPU manufacturers?
A Intel and AMD
B Via and Power PC Address Content
C Marek and Sun UltraSparc 0x4000 2F
7) What are the 32-bit data when we read a double-word at 0x4001 65
the address 0x4000 with Big Endian mode?
0x4002 7E
A 0xAC7E652F
B 0x2F657EAC 0x4003 AC
C 0xCAE756F2 Chapter 4 27

Exercises
1. Suppose that you discover that RAM addresses 000C0000 to 000C7FFF are
reserved for a PC’s video adapter. How many bytes of memory is this?
2. Suppose that you have an Intel 8086. Find the five-hex-digit address that
corresponds to each of these segment:offset pairs:
(a) 2B8C:8D21 (b) 059A:7A04 (c) 1234:5678
3. In an 8086 program, suppose that the data segment register DS contains the
segment number 23D1 and that an instruction fetches a word at offset 7B86
in the data segment. What is the five-hex-digit address of the word that is
fetched?
4. In an 8086 program, suppose that the code segment register CS contains the
segment number 014C and that the instruction pointer IP contains 15FE.
What is the five-hex-digit address of the next instruction to be fetched?
5. What are advantages and disadvantage of secondary memory?

Chapter 4 28

14
 3/3/2021

3. Input / Output Devices

 Input Devices collect & translate raw data into form

useable by computer. e.g keyboard accepts letters and
numbers and converts them to a binary code such as
Unicode.

 Output devices produce results in useable form for user

(or another device). e.g. monitor converts binary codes
to characters and images, whilst modem converts digital
data to analog form for transmission over telephone
lines.

Chapter 4 29

3. Input / Output Devices

Hardware – I/O Peripherals
1 Input Devices
 Mouse
 Keyboard

2 Output Devices
 Monitor (VDU)
 Printer

3 Secondary Storage Devices

 Hard Disk
 CD / DVD / Floppy

Chapter 4 30

15
 3/3/2021

3. Input / Output Devices

I/O Hardware

Chapter 4 31

3. Input / Output Devices

 Interface between System Bus and other Peripherals

 example
 Sound cards
 Video cards
 Network cards
 PCI cards

Chapter 4 32

16
 3/3/2021

3. Input / Output Devices

 series of electronic path ways and connecting other

components of the computer.

Chapter 4 33

3. Input / Output Devices

What are Computer Ports ?

 Connection point

 examples
1. Serial port (Com)
2. Parallel Port
3. USB port
4. Ethernet Port

Chapter 4 34

17
 3/3/2021

3. Input / Output Devices

Basic concepts - communication
 Most modern computers no longer operate in isolation - they
connect to other computers via modem or a network.

 To enable this communication, specialized hardware and

software must be added to computers.

 In combination with other devices such as telephones,

cabling, satellites, microwaves etc. , a communications
network is created

Chapter 4 35

4. Computer Software
Assembly/Machine Code View
CPU Memory
Addresses
Registers
Data Code
PC Data
Condition Instructions Stack
Codes

Programmer-Visible State
 PC: Program counter  Memory
 Address of next instruction  Byte addressable array
 Called “RIP” (x86-64)
 Code and user data
 Register file
 Stack to support procedures
 Heavily used program data
 Condition codes
 Store status information about most
recent arithmetic or logical operation
 Used for conditional branching
Chapter 4 36

18
 3/3/2021

4. Computer Software
Turning C into Object Code
 Code in files p1.c p2.c
 Compile with command: gcc –Og p1.c p2.c -o p
 Use basic optimizations (-Og) [New to recent versions of GCC]
 Put resulting binary in file p

text C program (p1.c p2.c)

Compiler (gcc –Og -S)

text Asm program (p1.s p2.s)

Assembler (gcc or as)

binary Object program (p1.o p2.o) Static libraries

(.a)
Linker (gcc or ld)

binary Executable program (p)

Chapter 4 37

4. Computer Software
Compiling Into Assembly
C Code (sum.c) Generated x86-64 Assembly
long plus(long x, long y); sumstore:
pushq %rbx
void sumstore(long x, long y, movq %rdx, %rbx
long *dest) call plus
{ movq %rax, (%rbx)
long t = plus(x, y); popq %rbx
*dest = t; ret
}
Obtain (on shark machine) with command
gcc –Og –S sum.c
Produces file sum.s
Warning: Will get very different results on non-Shark machines (Andrew Linux,
Mac OS-X, …) due to different versions of gcc and different compiler settings.

Chapter 4 38

19
 3/3/2021

Creating a new project - 1

Creating a new project 1

Chapter 4 39

Creating a new project - 2

Creating a new project 2

Chapter 4 40

20
 3/3/2021

Creating a new project - 3

Creating a new project 3

Chapter 4 41

Adding files to the project

Chapter 4 42

21
 3/3/2021

Setting project properties - 1

Setting project properties

Chapter 4 43

Setting project properties - 2

Setting project properties 2

Unfortunately the debug

information format alters the code
which gets generated too much,
making it not as simple as I would
like for this class.

Chapter 4 44

22
 3/3/2021

Setting project properties - 3

Setting project properties 3

This would just add

extra complexity to the
asm which we don't
want for now

Chapter 4 45

Setting project properties - 4

Setting project properties 4

Click this to
change which
It's all just a wrapper config set is
to set command line active
options

Different
options can be
set for release
vs debug
builds

Chapter 4 46

23
 3/3/2021

Setting project properties - 5

Setting project properties 5

C++ has more complicated

compiler-generated code,
and while our stuff is
simple enough that the
compiler probably
wouldn't do anything
different, it's good to do
this just to be safe

Chapter 4 47

Setting project properties - 6

Setting project properties 6

Another thing where I found

out the hard way that it will
increase the asm complexity

Chapter 4 48

24
 3/3/2021

Building the project - 1

Building project

Chapter 4 49

Building the project - 2

Building project 2
Information about whether the build
succeeded will be here. If it fails, a
separate error tab will open up

Chapter 4 50

25
 3/3/2021

Setting breakpoints & start debugger

Click to the left of

the line to break
at.

Chapter 4 51

Step into Step over Step out

Debugging the program 2

Continue

Stop debugging

Restart debugging

Current stopped location

Chapter 4 52

26
 3/3/2021

Showing assembly

Right click: Only

available while
debugging

Chapter 4 53

Watching registers

Note that it knows the ebp register is

going to be used in this instruction

Chapter 4 54

27
 3/3/2021

Showing registers

Here you can enter

register names or
variable names

Chapter 4 55

Watching the stack change - 1

Watching the stack change 1

Chapter 4 56

28
 3/3/2021

Watching the stack change - 2

Right click on the

body of the data in the

Watching the stack change 2 window and make

sure everything's set
like this

Set address to esp

(will always be
the top of the
stack) Set to 1

Click “Reevaluate
Automatically” so that it
Chapter 4
will change the display as 57
esp changes

29