1.

General overview of microprocessor

2. Memory interfacing
 What Microprocessor is ?

Multipurpose, Programmable, Clock driven

Electronics device or IC
Basic Operations of Microprocessor

Fetch: Microprocessor first brings the

instruction from Memory to CPU

Decode: Understands that instruction

Execution: Performs the required task

 Basic parts of a μP Based System
• CPU (μP)
• Memory
• I/O devices
Bus
According to computer architecture, a bus is defined as a single
or set of wires that transfers data between hardware
components of a computer or between two separate computers.

Types of Buses
Address Bus

Data Bus

Control Bus
Control Bus

 Generally contains one wire

 Generates control signals

 Some control signals are Read, Write and

Opcode fetch etc.
 Data Bus
A set of bidirectional wires

Sends or receives data or information

Number of wires used in a data bus is known as its

width

A microprocessor is generally known with its data bus

width

There are two types of data transfer; Serial data

transfer and Parallel data transfer
Address Bus

 A set of unidirectional wires are used to

select a device

 With n – digit numbering system we can

addressed maximum 2n number of houses

 Microprocessor having 16 bit address bus

can communicate with 216 or 65,536
numbers of devices
 Microprocessor Architecture
Contains various
registers that store
data temporarily
Register
ALU during program
Array
execution.
It performs various
arithmetic and
logical functions

Control Unit

It provides necessary timing and control

signals during program execution
 First Generation
Between 1971 – 1973 Historical Background
PMOS technology, non compatible with TTL
Second Generation
4 bit processors  16 pins
During 1973
8 and 16 bit processors  40 pins
NMOS technology  Faster speed, Higher
Due to limitations of pins, signals are
density, Compatible with TTL
multiplexed
4 / 8/ 16 bit processors  40 pins
Ability to address large memory spaces
and I/O ports
Greater number of levels of subroutine
Third Generation
nesting
During 1978
Better interrupt handling capabilities
HMOS technology  Faster speed, Higher
packing density
Intel 8085 (8 bit processor)
16 bit processors  40/ 48/ 64 pins
Easier to program
Dynamically relatable programs
Fourth Generation
Processor has multiply/ divide arithmetic
During 1980s
hardware
Low power version of HMOS technology
More powerful interrupt handling
(HCMOS)
capabilities
32 bit processors
Flexible I/O port addressing
Physical memory space 224 bytes = 16 Mb
Virtual memory space 240 bytes = 1 Tb
Intel 8086 (16 bit processor)
Floating point hardware
Supports increased number of addressing
modes

Intel 80386
Fifth Generation Pentium
MEMORY
A single Flip-Flop / Capacitor can store one
bit – 0 or 1

8 Flip-Flops together will form an 8-bit

Register

An 8-bit register can stores 8-bit or 1 Byte

data
 A set of 8-bit register will form a
Memory
Ten 8-bit registers

i.e. 10 bytes of
memory

can store 10 bytes

of data
10 x 8 bit memory
Or
10 byte memory
Accessing Memory or Memory Interfacing
11 Register 3
10 Register 2
01 Register 1
00 Register 0

00
A1
01

2 to 4 Decoder
10
A0
11
Calculate the address lines required for 10 K Byte
memory chip
1 K Byte = 1024 Byte of memory
Then 10 K Byte = 10 x 1024 Byte of memory

i.e. this memory chip has 10240 number of 8-bit registers

(default register size is 8-bit)

Consider n number of address lines required

Then 2n = 10240
Or n = 13.32 ≈ 14

So 14 number of address lines required

Consider the number of address lines are 13. Calculate
the number of memory chips required to access total
address space if each memory chip is 1024 x 8 bit

Total addressable space using 13 address line is

213 Byte = 23 x 210 Byte = 8 x 1024 Byte = 8 K Byte

Each memory chip is 1024 x 8 bit

= 1024 Byte

Number of memory chip required

(8 x 1024)
=8
1024
Accessing memory can be summarized into the following
three steps:
 Select the chip.
 Identify the memory register.
 Enable the appropriate buffer.

The microprocessor having N number of wires in its

address bus; uses part of the address bus to select the
chip and the remaining part goes through the address
decoder to select the register.

The control signals IO/M (to select I/O device or

memory), WR (enable writing) and RD (enable reading)
are used to activate the operation.
Consider a microprocessor having 16 bit Address Bus

 Maximum addressable memory space

216 Byte = 210. 26 Byte = 26 KByte = 64 KByte

 Starting address will be

0000 0000 0000 0000
 And last address will be
1111 1111 1111 1111

 It is more convenient to use Hexadecimal number

 In Hex code starting and last address will be

0000 H and FFFF H
 Explain the memory address range

A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000H
0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0FFFH
 Draw the memory map to access 256 Byte
memory using 16 bit address line
A15
A14
A13
A12 CS
A7
A11
A6
A10
A5
A9 256 Byte
A4
A8 Memory
A3
For addressing 256 Byte memory we A2
required only 8 address line (A0 to A7).
A1
Remaining 8 address lines (A8 to A15) is
A0
used of chip selection
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address

0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 7F00H

0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 7FFFH
Memory
Classification Memory

Primary Secondary
Memory Memory

RAM ROM Hard Disk,

Floppy, CD

Dynamic
Static RAM Erasable Permanent
RAM

Flash Masked
EPROM EEPROM PROM
Memory ROM
Random Access Memory (RAM)
Static RAM (SRAM)

• Stores bit as voltage

• High speed
• More expensive
• High power consumption

Dynamic RAM (DRAM)

• Stores bit as charge

• Low speed
• Less expensive
• Low power consumption
• Requires frequent refreshing
 Read Only Memory (ROM)
Masked ROM
• Bit pattern is permanently masked

Programmable ROM (PROM)

• Program is burnt into the memory only once

Erasable PROM (EPROM)

• Program can be erased using UV ray

Electrically EPROM (EEPROM)

• Program can be erased using electrical signals

Flash Memory
• It can be erased and reprogrammed a million times